JPH0990410A - Active matrix type liquid crystal display device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an active matrix type liquid crystal display device of a horizontal electric field system high in contrast and high in picture quality without causing any brightness unevenness. SOLUTION: This active matrix type liquid crystal display device has one pair of substrates(SUB1, SUB2), a liquid crystal layer(LC) held in between one pair of substrates, plural active elements(TFTs) formed in a matrix shape on the substrate of one side, plural pixels (PXs) to be respectively connected to plural active elements(TFTs) and plural counter electrodes(CTs) formed on either of the pair substrates and impressing electric fields almost parallel with the substrate to the liquid crystal layer(LC) in between pixel electrode (PXs) and the electrodes (CTs). Then, the angle formed by the side faces of the electrodes of at least either one of the pixel electrodes (PXs) and the counter electrodes (CTs) and the substrate face is defined as >0 deg. to <90 deg..

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device,
In particular, the present invention relates to a technique effectively applied to a horizontal electric field type active matrix liquid crystal display device.

[0002]

2. Description of the Related Art An active matrix type liquid crystal display device using an active element represented by a thin film transistor (TFT) is widely used as a display terminal device such as OA equipment because of its thin and lightweight characteristics and high image quality comparable to a cathode ray tube. It is becoming popular.

The display system of this active matrix type liquid crystal display device is roughly classified into the following two display systems.

First, by enclosing a liquid crystal layer between a pair of substrates having two transparent electrodes formed thereon, and applying a drive voltage to the two transparent electrodes, an electric field in a direction substantially perpendicular to the substrate interface causes a liquid crystal. This is a method of driving the layer, modulating the light that has passed through the transparent electrode and entering the liquid crystal layer (hereinafter referred to as the vertical electric field method), and all currently popular products adopt this method. There is.

However, in the active matrix type liquid crystal display device adopting the vertical electric field method, there is a remarkable change in luminance when the viewing angle direction is changed. Particularly, when halftone display is performed, the gradation level varies depending on the viewing angle direction. There was a problem in practical use, such as being reversed.

The other is that a liquid crystal layer is enclosed between a pair of substrates and a driving voltage is applied to two electrodes formed on the same substrate or both substrates, whereby a direction substantially parallel to the substrate interface is obtained. Is a method of driving the liquid crystal layer by the electric field of (2) and modulating the light incident on the liquid crystal layer through the gap between the two electrodes (hereinafter referred to as the "horizontal electric field method"). Type liquid crystal display device has not been put to practical use yet.

However, the active matrix type liquid crystal display device adopting this lateral electric field system has characteristics such as a wide viewing angle and a low load capacitance, and this lateral electric field system is promising for the active matrix type liquid crystal display device. Technology.

Regarding the features of the active matrix type liquid crystal display device adopting the lateral electric field method, refer to Japanese Patent Application Publication No. 5-505247, Japanese Patent Publication No. 63-21907, and Japanese Patent Application Laid-Open No. 6-160878. .

[0009]

However, in the active matrix type liquid crystal display device adopting the horizontal electric field system, unlike the active matrix type liquid crystal display device adopting the vertical electric field system, the comb-shaped elongated electrodes are shielded from light. Since it is formed in the effective pixel region that cannot be covered with the film (black matrix), a step is generated in the alignment film due to the thickness of the electrode.

Therefore, when the alignment film is rubbed, buff cloth bristles do not easily come into contact with the side of the electrode, which makes it difficult to rub the part, resulting in poor alignment, which results in a poor alignment region (domain). However, there is a problem in that the light leakage occurs and the black display does not sink, so that the contrast ratio is lowered, or unevenness in brightness is likely to occur due to the distribution of the rubbing intensity.

The present invention has been made to solve the above-mentioned problems of the prior art. An object of the present invention is to improve contrast in an active matrix type liquid crystal display device adopting a horizontal electric field system. In addition, it is to provide a technique capable of preventing the occurrence of uneven brightness.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0013]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

(1) A pair of substrates, a liquid crystal layer sandwiched between the pair of substrates, a plurality of active elements formed in a matrix on the one substrate, and connected to the plurality of active elements, respectively. A plurality of pixel electrodes, and a plurality of counter electrodes that are formed on one of the pair of substrates and that apply an electric field substantially parallel to the substrate surface to the liquid crystal layer between the pixel electrodes, In at least the active matrix liquid crystal display device having the above, the angle formed between the side surface of at least one of the pixel electrode and the counter electrode and the substrate surface is more than 0 degree and less than 90 degrees.

(2) In the means of (1) above, the angle formed between the side surface of at least one of the pixel electrode and the counter electrode and the substrate surface is 45 degrees.

(3) In the means of (1) or (2), the counter electrode is formed in the same layer as the pixel electrode on the one substrate on which an active element is formed. And

(4) A pair of substrates, a liquid crystal layer sandwiched between the pair of substrates, a plurality of active elements formed in a matrix on the one substrate, and connected to the plurality of active elements, respectively. A plurality of pixel electrodes, and a plurality of counter electrodes that are formed on one of the pair of substrates and that apply an electric field substantially parallel to the substrate surface to the liquid crystal layer between the pixel electrodes, In the method for manufacturing an active matrix type liquid crystal display device having at least the above-mentioned pixel, a conductive film is formed, a photoresist film patterned by photolithography is formed on the conductive film, and then wet etching is performed with an etchant containing nitric acid. By forming at least one electrode of the electrode and the counter electrode, at least one electrode of the pixel electrode and the counter electrode The angle of the side surface and the substrate surface, characterized in that form less than 90 degrees than 0 degrees.

(5) A pair of substrates, a liquid crystal layer sandwiched between the pair of substrates, a plurality of active elements formed in a matrix on the one substrate, and connected to the plurality of active elements, respectively. A plurality of pixel electrodes, and a plurality of counter electrodes that are formed on one of the pair of substrates and that apply an electric field substantially parallel to the substrate surface to the liquid crystal layer between the pixel electrodes, In the method for manufacturing an active matrix type liquid crystal display device having at least the above-mentioned pixel, a conductive film is formed, and a patterned photoresist film is formed on the conductive film by photolithography, and then the pixel is formed by dry etching simultaneously with oxygen asher. A side surface of at least one of the pixel electrode and the counter electrode by forming at least one of the electrode and the counter electrode The angle of the substrate surface, characterized in that form less than 90 degrees than 0 degrees.

[0019]

According to each of the above means, in the active matrix type liquid crystal display device adopting the horizontal electric field system, at least one of the pixel electrode and the counter electrode is formed by taper etching, and at least the pixel electrode and the counter electrode are formed. The angle between the side of one of the electrodes and the surface of the substrate exceeds 0 degrees and 90
Since the acute angle is less than or equal to 40 degrees, it is possible to smoothly apply buff bristles to the side of at least one of the pixel electrode and the counter electrode when rubbing the alignment film. Since the rubbing treatment is performed smoothly and reliably near the end face of the liquid crystal layer, it is possible to improve the orientation of the liquid crystal molecules in the liquid crystal layer on the side of the electrode.

As a result, the defective alignment region is eliminated, the contrast ratio is improved, and the uneven brightness due to the rubbing intensity distribution can be eliminated.

[0021]

Embodiments of the present invention will be described below in detail with reference to the drawings.

In all the drawings for explaining the embodiments, parts having the same function are designated by the same reference numerals, and the repeated description thereof will be omitted.

[Embodiment 1] In Embodiment 1, the end face of only the pixel electrode is provided with a taper angle to suppress rubbing defects,
This is an example in which the contrast is improved.

First, an outline of a horizontal electric field type active matrix type color liquid crystal display device constructed in this embodiment will be described.

<< Plane Configuration of Display Matrix Part (Pixel Part) >> FIG. 1 is a plan view showing one pixel and its periphery of an active matrix type color liquid crystal display device which is an embodiment (embodiment 1) of the present invention. Is.

As shown in FIG. 1, each pixel has two adjacent scanning signal lines (gate signal lines or horizontal signal lines) (G
L) and an adjacent two video signal lines (drain signal lines or vertical signal lines) (DL) are arranged in an intersecting region (in a region surrounded by four signal lines).

Each pixel has a thin film transistor (TFT),
Storage capacitor (Cstg), pixel electrode (PX), counter electrode (CT) and counter voltage signal line (common signal line) (C
L).

Here, the scanning signal lines (GL) and the counter voltage signal lines (CL) extend in the horizontal direction in FIG. 1 and are arranged in the vertical direction.

Further, the video signal lines (DL) extend in the vertical direction and a plurality of video signal lines (DL) are arranged in the horizontal direction.

The pixel electrode (PX) is connected to the source electrode (SD1) of the thin film transistor (TFT), and the counter electrode (CT) is formed integrally with the counter voltage signal line (CL).

The pixel electrode (PX) and the counter electrode (CT) face each other, and each pixel electrode (PX) and the counter electrode (CT).
The optical state of the liquid crystal layer (LC) is controlled by the electric field between and to control the display.

The pixel electrode (PX) and the counter electrode (CT) are formed in a comb-teeth shape, and each is a vertically long electrode in FIG.

In this embodiment, the pixel electrode (PX) has a U-shape that opens downward and the counter electrode (CT) has a counter voltage signal line (C).
L) has a comb-like shape protruding downward, and a region between the pixel electrode (PX) and the counter electrode (CT) is divided into four in one pixel.

<< Cross-Sectional Structure of Display Matrix Part (Pixel Part) >> FIG. 2 is a cross-sectional view showing a cross section taken along the line 3-3 shown in FIG. 1, and FIG. FIG. 4 is a sectional view showing a section of (TFT).
Is the storage capacitance (Cst
It is sectional drawing which shows the cross section of g).

As shown in FIGS. 2 to 4, a liquid crystal layer (LC)
On the lower transparent glass substrate (SUB1) side,
A thin film transistor (TFT), a storage capacitor (Cstg) and an electrode group are formed, and an upper transparent glass substrate (SUB) is formed.
On the 2) side, a color filter (FIL) and a black matrix pattern for light shielding (BM) are formed.

Further, transparent glass substrates (SUB1, SUB)
On the surface of each inner side (liquid crystal layer (LC) side) of 2), an alignment film (ORI1, OR) for controlling the initial alignment of the liquid crystal is formed.
I2) is provided, and a transparent glass substrate (SUB1,
Polarizing plates (POL1, POL2) are provided on the outer surface of each SUB2).

Here, as shown in FIG. 2, the pixel electrode (P
A taper angle is given to the end surface of (X).

In this embodiment, the angle formed by the end surface of the pixel electrode (PX) and the substrate surface is 45 °.

As a result, an alignment film (ORI1) described later is formed.
In rubbing, the rubbing process near the end face of the pixel electrode (PX) is performed smoothly and surely, and it becomes possible to eliminate the defective alignment region.

A more detailed structure will be described below.

<< TFT Substrate >> First, the structure of the lower transparent glass substrate (SUB1) side (TFT substrate) will be described in detail.

<< Thin Film Transistor (TFT) >> When a positive bias is applied to the gate electrode (GT) of the thin film transistor (TFT), the channel resistance between the source and the drain becomes small, and when the bias is zero, the channel resistance becomes large. Works like.

As shown in FIG. 3, the thin film transistor (TFT) includes a gate electrode (GT) and a gate insulating film (G).
I), i-type (intrinsic, intrinsic, i-type semiconductor layer (AS) made of amorphous silicon (Si) not doped with conductivity determining impurities), a pair of source electrodes (SD)
1), and has a drain electrode (SD2).

The source electrode (SD1) and the drain electrode (SD2) are originally determined by the bias polarity between them, and the polarity is reversed during operation in the circuit of this liquid crystal display device, so the source electrode (SD1) and drain It should be understood that the electrodes (SD2) switch during operation.

However, in the following description, for convenience, one is fixed as the source electrode (SD1) and the other is fixed as the drain electrode (SD2).

In this embodiment, an amorphous silicon thin film transistor element is used as a thin film transistor (TFT), but the invention is not limited to this, and a polysilicon thin film transistor element, a MOS type transistor on a silicon wafer, an organic thin film transistor, TFT or MIM
It is also possible to use a two-terminal element (strictly not an active element, but an active element in the present invention) such as a (Metal-Insulator-Metal) diode.

<< Gate Electrode (GT) >> Gate Electrode (G
T) is formed continuously with the scanning signal line (GL), and a partial region of the scanning signal line (GL) is a gate electrode (G).
T).

The gate electrode (GT) is a portion that exceeds the active region of the thin film transistor (TFT), and is formed larger than it so as to completely cover the i-type semiconductor layer (AS) (when viewed from below). .

Thus, in addition to the role of the gate electrode (GT), the i-type semiconductor layer (AS) is devised so as not to be exposed to external light or backlight light.

In this embodiment, the gate electrode (GT) is formed of a single-layer conductive film (g1), and the conductive film (g1) is used.
For example, an aluminum (Al) -based conductive film formed by sputtering is used, and an anodized film (AOF) of aluminum (Al) is provided thereon.

<< Scanning Signal Line (GL) >> Scanning Signal Line (G)
L) is composed of a conductive film (g1), and the conductive film (g1) of this scanning signal line (GL) is a gate electrode (GT).
The conductive film (g1) is formed in the same manufacturing process and is integrally formed.

By this scanning signal line (GL), the gate voltage (VG) is supplied to the gate electrode (GT) from the external circuit.

An aluminum (Al) anodic oxide film (AOF) is also provided on the scanning signal line (GL).

The portion intersecting with the video signal line (DL) is made thin to reduce the probability of short circuit with the video signal line (DL), and even if the short circuit occurs, it can be separated by laser trimming. Has been forked.

<< Counter Electrode (CT) >> Counter Electrode (CT)
Is composed of a conductive film (g1) in the same layer as the gate electrode (GT) and the scanning signal line (GL).

An aluminum (Al) anodic oxide film (AOF) is also provided on the counter electrode (CT).

A counter voltage (Vco) is applied to the counter electrode (CT).
m) is applied.

In this embodiment, the counter voltage (Vcom) is
From the intermediate DC potential between the minimum level drive voltage (VDmin) and the maximum level drive voltage (VDmax) applied to the video signal line (DL), the thin film transistor element (TFT)
The voltage is set to a lower potential by the feedthrough voltage (ΔVs) generated when the power supply is turned off, but if you want to reduce the power supply voltage of the integrated circuit used in the video signal drive circuit to about half, change the AC voltage to It may be applied.

<< Counter Voltage Signal Line (CL) >> The counter voltage signal line (CL) is composed of a conductive film (g1).

The conductive film (g of this counter voltage signal line (CL)
1) is formed in the same manufacturing process as the conductive film (g1) of the gate electrode (GT), the scanning signal line (GL) and the counter electrode (CT), and is formed integrally with the counter electrode (CT).

The counter voltage signal line (CL) supplies a counter voltage (Vcom) from the external circuit to the counter electrode (CT).

An aluminum (Al) anodic oxide film (AOF) is also provided on the counter voltage signal line (CL).

The portion intersecting with the video signal line (DL) is made thin in order to reduce the probability of short circuit with the video signal line (DL) as in the case of the scanning signal line (GL). , Bifurcated so that it can be separated by laser trimming.

The counter electrode (CT) and the counter voltage signal line (CL) may be formed on the upper transparent glass substrate (SUB2) (color filter substrate) side.

<< Insulating Film (GI) >> The insulating film (GI) is used for the gate electrode (G) in the thin film transistor (TFT).
It is used as a gate insulating film for applying an electric field to the semiconductor layer (AS) together with T).

The insulating film (GI) is formed in the upper layer of the gate electrode (GT) and the scanning signal line (GL), and the insulating film (GI) is, for example, a silicon nitride film formed by plasma CVD. It is selected and formed to a thickness of 1200 to 2700 angstroms (about 2400 angstroms in this embodiment).

The gate insulating film (GI) is formed so as to surround the entire display matrix portion (AR), and the peripheral portion is removed so that the external connection terminals (DTM, GTM) are exposed.

The insulating film (GI) also contributes to electrical insulation between the scanning signal line (GL) and the counter voltage signal line (CL) and the video signal line (DL).

<< i-Type Semiconductor Layer (AS) >> The i-type semiconductor layer (AS) is formed of amorphous silicon to a thickness of 200 to 2200 Å (in this embodiment, a film thickness of about 2000 Å). It

The layer (d0) is an N (+) type amorphous silicon semiconductor layer doped with phosphorus (P) for ohmic contact, the i type semiconductor layer (AS) is present on the lower side, and the upper side is on the upper side. It is left only where the conductive films (d1, d2) exist.

The i-type semiconductor layer (AS) is provided with the scanning signal line (G
L) and the counter voltage signal line (CL) and the video signal line (D
It is also provided between both the intersections (L) and the crossover portions.

The i-type semiconductor layer (AS) at the intersection reduces the short circuit between the scanning signal line (GL) and the counter voltage signal line (CL) and the video signal line (DL) at the intersection.

<< Source Electrode (SD1), Drain Electrode (SD2) >> Source Electrode (SD1), Drain Electrode (S
Each of D2) is a conductive film (d1) in contact with the N (+) type semiconductor layer (d0) and a conductive film (d) formed thereon.
2).

The conductive film (d1) is a chromium (Cr) film formed by sputtering and is formed to a thickness of 500 to 1000 angstroms (about 600 angstroms in this embodiment).

Since the stress of the chromium (Cr) film increases when the film is formed thick, the chromium (Cr) film is formed within the range of about 2000 angstroms.

The chromium (Cr) film improves the adhesiveness to the N (+) type semiconductor layer (d0) and is made of aluminum (Al).
The aluminum (Al) in the conductive film (d2) of the system is N
It is used for the purpose of preventing diffusion into the (+) type semiconductor layer (d0) (so-called barrier layer).

As the conductive film (d1), in addition to the chromium (Cr) film, refractory metal (molybdenum (Mo), titanium (T) is used.
i), tantalum (Ta), tungsten (W) film, refractory metal silicide (MoSi2, TiSi2, TaS)
i2, WSi2) film may be used.

As the conductive film (d2), an aluminum (Al) -based conductive film is sputtered from 3000 to 50.
To a thickness of 00 Å (in this example, 400
0 angstrom).

The aluminum (Al) -based conductive film has a smaller stress than the chromium (Cr) film and can be formed to have a thick film thickness, and the source electrode (SD1), the drain electrode (SD2) and the video signal can be formed. To reduce the resistance value of the line (DL), the gate electrode (GT) and the i-type semiconductor layer (AS)
It has the function of ensuring that the vehicle is able to climb over steps caused by (improving the step coverage).

Here, taper angles are given to the end faces of the source electrode (SD1) and the drain electrode (SD2),
In this embodiment, the angle formed between the end face and the substrate surface is 45 °.

This is because when the alignment film (ORI1) described later is rubbed, the rubbing process near the end face of the pixel electrode (PX) is performed smoothly and surely to eliminate the defective alignment region.

In this embodiment, the pixel electrode (PX),
Video signal line (DL), source electrode (SD1), and
Since the drain electrode (SD2) is formed in the same layer in the same process, the video signal line (DL) and the source electrode (SD
1), the end face of the drain electrode (SD2) is also given the same taper angle.

Further, after patterning the conductive film (d1) and the conductive film (d2) with the same mask pattern, the same mask is used, or the conductive film (d1) and the conductive film (d2).
The N (+) type semiconductor layer (d0) is removed using the as a mask.

That is, in the N (+) type semiconductor layer (d0) remaining on the i type semiconductor layer (AS), the portions other than the conductive film (d1) and the conductive film (d2) are removed by self-alignment.

At this time, since the N (+) type semiconductor layer (d0) is etched so that the entire thickness thereof is removed, the i type semiconductor layer (AS) is also slightly etched on its surface portion. The degree may be controlled by the etching time.

<< Video Signal Line (DL) >> Video Signal Line (D)
L is a source electrode (SD1) and a drain electrode (SD
2), similarly, it is composed of a conductive film (d1) and a conductive film (d2) formed thereon.

The video signal line (DL) is formed in the same layer as the source electrode (SD1) and the drain electrode (SD2), and the image signal line (DL) is formed in the drain electrode (SD).
2) is integrally configured.

As described above, the source electrode (SD1),
Similar to the drain electrode (SD2), the end surface of the video signal line (DL) has a taper angle of 45 °.

<< Pixel Electrode (PX) >> Pixel Electrode (PX)
Is a source electrode (SD1), a drain electrode (SD2)
Similarly, it is composed of a conductive film (d1) and a conductive film (d2) formed thereon.

The pixel electrode (PX) is formed in the same layer as the source electrode (SD1) and the drain electrode (SD2), and the pixel electrode (PX) is the source electrode (SD).
It is configured integrally with 1).

As described above, the taper angle of 45 ° is given to the end surface of the pixel electrode (PX).

This is because when the alignment film (ORI1) is rubbed, the rubbing process in the vicinity of the end face of the pixel electrode (PX) is smoothly and surely performed to eliminate the defective alignment region.

As a result, light leakage near the pixel electrode (PX) electrode is eliminated, and the contrast ratio can be greatly improved.

<< Storage Capacitance (Cstg) >> Pixel Electrode (P
X) is configured to overlap the counter voltage signal line (CL) at the end opposite to the end connected to the thin film transistor (TFT).

In this superposition, as apparent from FIG. 4, the pixel electrode (PX) is used as one electrode (PL2),
A storage capacitor (electrostatic capacitance element) (Cstg) having the opposite voltage signal (CL) as the other electrode (PL1) is configured.

The dielectric film of this storage capacitor (Cstg) is
It is composed of an insulating film (GI) used as a gate insulating film of a thin film transistor (TFT) and an anodized film (AOF).

As shown in FIG. 1, the storage capacitance (C
stg) is a conductive film (g1) of the counter voltage signal line (CL)
Is formed in the part where the width of is widened.

<< Protective Film (PSV) >> A protective film (PSV) is provided on the thin film transistor (TFT).

The protective film (PSV) is provided mainly for protecting the thin film transistor (TFT) from moisture and the like, and a film having high transparency and good moisture resistance is used.

The protective film (PSV) is formed of, for example, plasma C
It is formed of a silicon oxide film or a silicon nitride film formed by a VD device and has a film thickness of about 1 μm.

The protective film (PSV) is formed so as to surround the entire display matrix portion (AR), and the peripheral portion is removed so as to expose the external connection terminals (DTM, GTM).

Protective film (PSV) and gate insulating film (GI)
As for the thickness relation of, the former is thickened considering the protection effect, and the latter is the transconductance (gm) of the transistor.
Think thin.

Therefore, a protective film (PSV) having a high protective effect
Are formed to be larger than the gate insulating film (GI) so as to protect the peripheral portion as widely as possible.

<< Color Filter Substrate >> Next, referring to FIGS.
Returning to, the configuration of the upper transparent glass substrate (SUB2) side (color filter substrate) will be described in detail. << Light-shielding film (BM) >> On the upper transparent glass substrate (SUB2) side, unnecessary gaps (pixel electrode (PX) and counter electrode (C)
Transmitted light from a gap other than between T) is emitted to the display surface side and the contrast ratio and the like are not lowered, so that the light shielding film (B
M) (so-called black matrix) is formed.

The light shielding film (BM) also plays a role of preventing external light or backlight light from entering the i-type semiconductor layer (AS).

That is, the i-type semiconductor layer (AS) of the thin film transistor (TFT) is sandwiched by the upper and lower light-shielding films (BM) and the large gate electrode (GT) so that external natural light or backlight light is not exposed.

The closed polygonal contour line of the light-shielding film (BM) shown in FIG. 1 indicates an opening inside which the light-shielding film (BM) is not formed.

The boundary line in the vertical direction shown in FIG. 1 is determined by the alignment accuracy of the upper and lower substrates. If the alignment accuracy is better than the electrode width of the counter electrode (CT) adjacent to the video signal line (DL), the counter electrode. If it is set within the width of, the opening can be enlarged.

The light-shielding film (BM) has a light-shielding property and is formed of a film having a high insulating property so as not to affect the electric field between the pixel electrode (PX) and the counter electrode (CT). Therefore, in this embodiment, a black pigment is mixed into the resist material to form a thickness of about 1.2 μm.

The light-shielding film (BM) is formed in a lattice shape around each pixel, and the effective display area of one pixel is partitioned by this lattice.

Therefore, the contour of each pixel is made clear by the light shielding film (BM).

That is, the light shielding film (BM) has two functions of a black matrix and a light shielding for the i-type semiconductor layer (AS).

The light-shielding film (BM) is also formed in a frame shape in the peripheral portion, and its pattern is formed continuously with the pattern of the matrix portion shown in FIG. 1 in which a plurality of dots-like openings are provided.

The light-shielding film (BM) in the peripheral portion is formed in the seal portion (S
L) is extended to the outside to prevent leak light such as reflected light caused by a mounting machine such as a personal computer from entering the display matrix portion.

On the other hand, this light-shielding film (BM) is kept inside by about 0.3 to 1.0 mm from the edge of the upper transparent glass substrate (SUB2), and is formed so as to avoid the cut region of the upper transparent substrate (SUB2). Has been done.

<< Color Filter (FIL) >> The color filter (FIL) is formed in a stripe shape by repeating red, green, and blue at a position facing a pixel, and the color filter (FIL) is a light-shielding film (BM). ) Is formed so as to overlap the edge portion.

The color filter (FIL) can be formed as follows.

First, a dyeing base material such as acrylic resin is formed on the surface of the upper transparent glass substrate (SUB2), and the dyeing base material other than the red filter forming region is removed by photolithography technique.

After that, the dyed substrate is dyed with a red dye, and a fixing process is performed to form a red filter (R).

Next, by performing the same steps,
A green filter (G) and a blue filter (B) are sequentially formed.

<< Overcoat Film (OC) >> The overcoat film (OC) prevents the dye from leaking from the color filter (FIL) to the liquid crystal layer (LC), and the color filter (FIL) and the light shielding film. It is provided to flatten the step due to (BM).

The overcoat film (OC) is made of a transparent resin material such as acrylic resin or epoxy resin.

<< Liquid Crystal Layer and Polarizing Plate >> Next, the liquid crystal layer, the alignment film, the polarizing plate and the like will be described.

<< Liquid Crystal Layer >> As the liquid crystal material of the liquid crystal layer (LC), the dielectric anisotropy (Δε) is positive and its value is 13.
2. The refractive index anisotropy (Δn) is 0.081 (589 nm,
A nematic liquid crystal of 20 ° C.) is used.

The thickness (gap) of the liquid crystal layer is 3.9 μm.
And the retardation (Δn · d) is 0.316.

The value of this retardation (Δn · d) is
It is set to be half the average wavelength of the wavelength characteristic of the backlight light, and the color tone of the transmitted light of the liquid crystal layer is white (C light source, by combination with the wavelength characteristic of the backlight light).
The chromaticity coordinates x = 0.3101 and y = 0.3163) are set.

The maximum transmittance can be obtained when the angle formed by the polarization transmission axis of the polarizing plate and the long axis direction of the liquid crystal molecules is 45 °, and transmitted light having almost no wavelength dependence within the visible light range can be obtained. be able to.

The thickness (gap) of the liquid crystal layer is controlled by polymer beads.

The liquid crystal material of the liquid crystal layer (LC) is not particularly limited, and the dielectric anisotropy Δε may be negative.

Further, the dielectric anisotropy (Δε) has a larger value, the driving voltage can be reduced, and the refractive index anisotropy (Δn) has a smaller value, the thickness (gap) of the liquid crystal layer.
Can be made thicker, the liquid crystal filling time can be shortened, and the gap variation can be reduced.

<< Alignment Film >> Polyimide is used as the alignment film (ORI).

As shown in FIG. 19, the rubbing direction (RDR) is parallel to each other on the upper and lower substrates, and the angle with the applied electric field direction (EDR) is 75 °.

The angle formed by the rubbing direction (RDR) and the applied electric field direction (EDR) is 45 ° C. or more 90 if the dielectric anisotropy (Δε) of the liquid crystal material of the liquid crystal layer (LC) is positive. 0 ° C if the dielectric anisotropy (Δε) is less than ℃ and negative.
Must be over 45 ° and less than 45 °.

Further, in this embodiment, since the taper angle is given to the pixel electrode (PX), the step portions at both ends of the pixel electrode (PX) are eliminated, and the buff cloth buffs of the rubbing machine can be smoothly smoothed. (PX) Since it is in contact with both ends, rubbing failure is eliminated.

As a result, the alignment state of the liquid crystal molecules is stable and good display can be performed.

<< Polarizing Plate >> As shown in FIG. 19, the polarization transmission axis (MAX1) of the lower polarizing plate (POL1) is aligned with the rubbing direction (RDR), and the upper polarizing plate (POL2).
The polarization transmission axis (MAX2) of is orthogonal to it.

As a result, in the present embodiment, the normally closed characteristic in which the transmittance increases as the voltage applied to the pixel (voltage between the pixel electrode (PX) and the counter electrode (CT)) is increased. Obtainable.

<< Structure around display matrix section (AR) >>
FIG. 5 is a diagram showing a main part plane around a display matrix (AR) part of a display panel (PNL) including upper and lower glass substrates (SUB1, SUB2).

FIG. 6 is a diagram showing a cross section near the external connection terminal (GTM) to which the scanning circuit is to be connected on the left side and a cross section near the seal portion where there is no external connection terminal on the right side.

In the manufacture of this panel, if the size is small, a plurality of devices are simultaneously processed on one glass substrate for the purpose of improving the throughput, and then divided. after processing the glass substrate of a standardized size in any breed for shared, reducing the size to suit each model, in either case the glass is cut through the one way process.

FIG. 5 and FIG. 6 show the latter example, and both upper and lower transparent glass substrates (SUB1 and S) are shown in FIG. 5 and FIG.
UB2) is shown after cutting, and LN shown in FIG. 5 shows the edges of both substrates before cutting.

In any case, in the completed state, the external connection terminal group (Tg, Td) and the terminal (CTM) (subscripts omitted) are present (the upper side and the left side in the figure) so that they are exposed. The size of the upper transparent glass substrate (SUB2) is limited to the inside of the lower transparent glass substrate (SUB1).

In the terminal groups (Tg, Td), a scanning circuit connecting terminal (GTM), a video signal circuit connecting terminal (DTM), and their lead-out wiring portion, which are integrated circuit chips (CHI), are mounted, respectively, which will be described later. Tape carrier package (T
CP) (FIGS. 16 and 17) are collectively named.

The lead wiring from the display matrix portion of each group to the external connection terminal portion is inclined toward both ends.

This is to match the terminals (DTM, GTM) of the display panel (PNL) with the arrangement pitch of the packages (TCP) and the connection terminal pitch of each package (TCP).

The counter electrode terminal (CTM) is a terminal for applying a counter voltage (Vcom) to the counter electrode (CT) from an external circuit.

The counter voltage signal line (C
L) is led out to the opposite side (right side in the figure) of the scanning circuit terminal (GTM), and the respective counter voltage signal lines (CL) are grouped together by a common bus line (CB) (counter electrode connection signal line) to face each other. It is connected to the electrode terminal (CTM).

A liquid crystal sealing port (INJ) is removed between the transparent glass substrates (SUB1, SUB2) along the edge thereof.
A seal pattern (S) is formed so as to seal the liquid crystal layer (LC).
L) is provided.

The seal pattern (SL) is made of, for example, epoxy resin.

The layers of the orientation films (ORI1 and ORI2) are formed inside the seal pattern (SL), and the polarizing plates (POL1 and POL2) are the lower transparent glass substrate (SUB1) and the upper transparent glass substrate (SUB1), respectively. It is formed on the outer surface of the SUB2).

The liquid crystal layer (LC) is composed of a lower alignment film (ORI1) and an upper alignment film (ORI2) for setting the orientation of liquid crystal molecules.
It is enclosed in the area partitioned by the seal pattern (SL) between the and.

The lower alignment film (ORI1) is formed on the lower transparent glass substrate (SUB1) side of the protective film (PSV).

In the liquid crystal display device of this embodiment, the lower transparent glass substrate (SUB1) and the upper transparent glass substrate (SUB) are used.
2) After separately forming various layers by stacking, a seal pattern (SL) is formed on the upper transparent glass substrate (SUB2) side, and a lower transparent glass substrate (SUB1) and an upper transparent glass substrate (SUB2) are formed. It is assembled by stacking, injecting liquid crystal (LC) from the opening (INJ) of the seal pattern (SL), sealing the injection port (INJ) with epoxy resin, and cutting the upper and lower substrates.

<< Gate Terminal (GTM) Section >> FIG. 7 is a diagram showing a connection structure from the scanning signal line (GL) of the display matrix section (AR) to the gate terminal (GTM) which is an external connection terminal thereof. FIG. 7A is a plan view.
7B is a cross-sectional view taken along the line BB shown in FIG.

Note that FIG. 7 corresponds to the vicinity of the lower side in FIG. 5, and the diagonal wiring portions are shown in a straight line for convenience.

In FIG. 7, AO is a boundary line of direct photoresist writing, in other words, a photoresist pattern of selective anodic oxidation.

Therefore, this photoresist is removed after anodic oxidation, and the pattern (AO) shown in FIG. 7 does not remain as a finished product, but an oxide film (AOF) is formed on the gate wiring (GL) as shown in the sectional view. Since it is selectively formed, its locus remains.

In the plan view of FIG. 7A, the left side is a region which is covered with the resist and is not anodized, and the right side is a region which is exposed from the resist and is anodized with respect to the photoresist boundary line (AO).

The anodized aluminum (AL) type conductive film (g1) has an aluminum oxide film (Al2
O3) is formed, and the volume of the lower conductive portion is reduced.

Of course, the anodic oxidation is carried out by setting an appropriate time and voltage so that the conductive portion remains.

In FIG. 7, the aluminum (AL) -based conductive film (g1) is hatched for easy understanding, but the non-anodized region is patterned into a comb shape.

This is because whiskers are generated on the surface when the width of the aluminum (Al) -based conductive film is wide, so that the width of each one is made narrow and a plurality of them are bundled in parallel. The aim is to minimize the probability of wire breakage and the sacrifice of conductivity while preventing the occurrence of whiskers.

The gate terminal (GTM) protects the aluminum (Al) -based conductive film (g1) and the surface thereof, and further, the TCP (Tape Carrier Pac).
The transparent conductive film (g2) for improving the reliability of the connection with the

This transparent conductive film (g2) is a transparent conductive film (Indium-Tin-O) formed by sputtering.
xide ITO: Nesa film), 1000 to 20
To a thickness of 00 angstrom (140 in this embodiment).
The film thickness is about 0 angstrom).

Further, the conductive film (d1) formed on the aluminum (Al) -based conductive film (g1) and on the side surface thereof has a poor connection between the conductive film (g1) and the transparent conductive film (g2). In order to compensate for this, a chromium (Cr) layer (d) having good connectivity is provided on both the conductive film (g1) and the transparent conductive film (g2).
1) is connected to reduce the connection resistance, and the conductive film (d2) remains because it is formed with the same mask as the conductive film (d1).

In the plan view of FIG. 7A, the gate insulating film (GI) is formed on the right side of the boundary line (AO) and the protective film (PSV) is formed on the left side of the boundary line (AO). The terminal portion (GTM) located at the left end is exposed from them and can be electrically contacted with an external circuit.

In FIG. 7, only one pair of the gate line (GL) and the gate terminal is shown, but in reality, a plurality of such pairs are arranged vertically to form the terminal group (Tg) shown in FIG.
In the manufacturing process, the left end of the gate terminal is extended beyond the cutting region of the substrate and short-circuited by the wiring (SHg) (not shown).

Such a short-circuit line (SH
g) is useful for supplying power during anodization and preventing electrostatic breakdown during rubbing of the alignment film (ORI1).

<< Drain Terminal (DTM) Section >> FIG. 8 is a diagram showing a connection from the video signal line (DL) of the display matrix section (AR) to the drain terminal (DTM) which is an external connection terminal thereof. 8 (A) is a plan view of FIG.
8B is a cross-sectional view taken along the line BB shown in FIG.

Note that FIG. 8 corresponds to the vicinity of the upper right of FIG. 5, and although the orientation of the drawing is changed for convenience, the right end direction corresponds to the upper end of the lower transparent glass substrate (SUB1).

In FIG. 8, TSTd is an inspection terminal, which is not connected to an external circuit, but is wider than the wiring portion so that a probe needle or the like can come into contact therewith.

Similarly, the width of the drain terminal (DTM) is wider than that of the wiring portion so that it can be connected to an external circuit.

A plurality of drain terminals (DTM) are vertically arranged to form a terminal group (Td) (subscripts omitted) shown in FIG. 5, and the drain terminals (DTM) are lower transparent glass substrates (SUB1). Are extended beyond the cutting line of No. 1 and all of them are short-circuited to each other by a wiring (SHd) (not shown) during the manufacturing process to prevent electrostatic breakdown.

The inspection terminal (TSTd) is provided on every other video signal line (DL) as shown in FIG.

The drain connection terminal (DTM) is formed of a single layer of the transparent conductive film (g2), and the gate insulating film (G2).
The part where I) is removed is connected to the video signal line (DL).

The semiconductor layer (AS) formed on the end portion of the gate insulating film (GI) is for etching the edge of the gate insulating film (GI) in a tapered shape.

On the drain connection terminal (DTM), the protective film (PSV) is, of course, removed for connection with an external circuit.

The lead wiring from the display matrix portion (AR) to the drain terminal portion (DTM) is a video signal line (DL).
Conductive films (d1, d2) of the same level as the protective film (PS
V) is formed halfway and is connected to the transparent conductive film (g2) in the protective film (PSV).

This is aluminum (Al), which is easy to contact with electricity.
The purpose is to protect the conductive film (d2) of the system with a protective film (PSV) or a seal pattern (SL) as much as possible.

<< Counter Electrode Terminal (CTM) >> FIG. 9 is a diagram showing a connection from the counter voltage signal line (CL) to the counter electrode terminal (CTM) which is an external connection terminal thereof.
9A is a plan view thereof, and FIG. 9B is a plan view thereof.
It is sectional drawing in the BB cutting line shown to (A).

FIG. 9 corresponds to the vicinity of the upper left of FIG.

The counter voltage signal lines (CL) are grouped together by a common bus line (CB) and led out to the counter electrode terminals (CTM).

The common bus line (CB) is a conductive film (g).
It has a structure in which a conductive film (d1) and a conductive film (d2) are laminated on 1).

This reduces the resistance of the common bus line (CB), and the counter voltage is transferred from the external circuit to each counter voltage signal line (C).
This is to ensure sufficient supply to L).

This structure is characterized in that the resistance of the common bus line (CB) can be lowered without adding a new conductive film.

Conductive film (g1) of common bus line (CB)
Is not joined to the anode so as to be electrically connected to the conductive film (d1) and the conductive film (d2), and is also exposed from the gate insulating film (GI).

The counter electrode terminal (CTM) is a conductive film (g
The transparent conductive film (g2) is laminated on 1).

As described above, the transparent conductive film (g2) having a good durability for protecting the surface and preventing electrolytic corrosion,
It covers the conductive film (g1).

<< Equivalent Circuit of Entire Display Device >> FIG. 10 is a diagram showing a connection diagram of an equivalent circuit of the display matrix portion (AR) and its peripheral circuits.

Although FIG. 10 is a circuit diagram, it is drawn corresponding to the actual geometrical arrangement.

In FIG. 10, AR indicates a display matrix section (matrix array) in which a plurality of pixels are two-dimensionally arranged.

In FIG. 10, X means a video signal line (DL), and subscripts G, B and R are added corresponding to green, blue and red pixels, respectively.

Y represents a scanning signal line (GL), and subscripts 1, 2, 3, ..., End are added according to the order of scanning timing.

The scanning signal line (Y) (subscript omitted) is connected to the vertical scanning circuit (V), and the video signal line (X) (subscript omitted) is connected to the video signal drive circuit (H).

The circuit (SUP) is a CRT (cathode ray tube) from a power supply circuit or a host (upper processing unit) for obtaining a plurality of divided and stabilized voltage sources from one voltage source.
Is a circuit including a circuit for exchanging information for use in (TFT) liquid crystal display device.

<< Driving Method >> FIG. 11 is a diagram showing driving waveforms during driving in the liquid crystal display device of the present embodiment.
1 (a) and FIG. 11 (b) show the gate voltage (scanning signal voltage) (VG) applied to the (i-1) th and (i) th scanning signal lines (GL), respectively. .

FIG. 11C shows the video signal line (D
FIG. 11 shows the video signal voltage (VD) applied to L).
(D) is a counter voltage (V) applied to the counter electrode (CT).
com) is shown.

Further, FIG. 11 (e) shows row (i),
The pixel electrode voltage (Vs) applied to the pixel electrode (PX) in the pixel in the (j) column is shown, and FIG.
The voltage (VLC) applied to the liquid crystal layer (LC) of the pixels in the row and column (j) is shown.

In the driving method of the liquid crystal display device of the present embodiment, as shown in FIG. 11D, the counter voltage (Vcom) applied to the counter electrode (CT) is set to the binary AC rectangular wave of VCH and VCL. Gate electrode (GT) with a shaped wave and synchronized with it
The non-selection voltage of the gate voltage (VG) applied to is changed by one of two values, VGLH and VGLL, for each scanning period.

In this case, the amplitude value of the counter voltage (Vcom) and the amplitude value of the non-selection voltage of the gate voltage (VG) are made the same.

The video signal voltage (VD) applied to the video signal line (DL) is a voltage (VSIG) obtained by subtracting 1/2 of the amplitude of the counter voltage (VC) from the voltage desired to be applied to the liquid crystal layer (LC). Is.

Counter voltage (V) applied to counter electrode (CT)
com) may be direct current, but the maximum amplitude of the video signal voltage (VD) can be reduced by making it alternating current, and it is possible to use a video signal drive circuit (signal side driver) having a low withstand voltage.

<< Function of Storage Capacitor (Cstg) >> The storage capacitor (Cstg) is provided to store video information written in a pixel (after the thin film transistor (TFT) is turned off) for a long time.

Unlike the method of applying the electric field perpendicularly to the substrate surface, the method of applying the electric field parallel to the substrate surface as in this embodiment is composed of the pixel electrode (PX) and the counter electrode (CT). Since there is almost no capacitance (so-called liquid crystal capacitance (Cpix)), the video information cannot be stored in the pixel without the storage capacitance (Cstg).

Therefore, in the system in which the electric field is applied parallel to the substrate surface, the storage capacitance (Cstg) is an essential constituent element.

The storage capacitor (Cstg) also works to reduce the influence of the gate potential change (ΔVG) on the pixel electrode potential (Vs) when the thin film transistor (TFT) switches.

This situation is expressed by the following equation.

ΔVs = {Cgs / (Cgs + Cstg +
Cpix)} × ΔVG where Cgs is the parasitic capacitance formed between the gate electrode (GT) and the source electrode (SD1) of the thin film transistor (TFT), and Cpix is the pixel electrode (PX) and the counter electrode (CT). ΔVs, which is a capacitance formed during the period, represents a so-called feedthrough voltage corresponding to a change in the pixel electrode potential due to ΔVG.

This variation (ΔVs) is the liquid crystal layer (LC).
Cause a direct current component added to the storage capacitor (Cst
The larger g) is, the smaller the value can be.

The reduction of the direct current component applied to the liquid crystal layer (LC) can improve the life of the liquid crystal layer (LC) and reduce the so-called burn-in in which the previous image remains when the liquid crystal display screen is switched.

As described above, the gate electrode (GT) is
The source electrode (SD1) and the drain electrode (SD2) are large enough to completely cover the i-type semiconductor layer (AS).
The overlapping area with
s) is increased, and the pixel electrode potential (Vs) is easily affected by the gate voltage (scanning signal voltage) (VG), which has the opposite effect.

However, by providing the storage capacitor (Cstg), this demerit can be eliminated.

<< Manufacturing Method >> Next, a manufacturing method of the lower transparent glass substrate (SUB1) side of the above-described liquid crystal display device will be described with reference to FIGS.

12 to 14, the central character is an abbreviation for the process name, the left side is the thin film transistor (TFT) portion shown in FIG. 3, and the right side is the processing viewed from the sectional shape near the gate terminal shown in FIG. Shows the flow of.

Except for Process B and Process D, Process A to Process I are classified according to each photographic process, and all the cross-sectional views of each process are the stages after processing after photographic process and removal of photoresist. Is shown.

In the following description, photographic processing refers to a series of operations from application of photoresist to selective exposure using a mask to development thereof, and repeated description will be omitted.

The process will be described below in accordance with the divided steps.

(Step A, FIG. 12) On a lower transparent glass substrate (SUB1) made of glass, aluminum (Al) -palladium (P) having a film thickness of 3000 angstrom is formed.
d), a conductive film (g1) made of aluminum (Al) -silicon (Si), aluminum (Al) -tantalum (Ta), aluminum (Al) -titanium (Ti) -tantalum (Ta), etc. is formed by sputtering. .

After the photographic processing, the conductive film (g1) is selectively etched with a mixed acid solution of phosphoric acid, nitric acid, glacial acetic acid and water.

Thereby, the gate electrode (GT), scanning signal line (GL), counter electrode (CT), counter voltage signal line (CL), electrode (PL1), gate terminal (GTM), common bus line (CB). Of the first conductive film and the counter electrode terminal (C
A first conductive film of TM), an anodizing bus line (SHg) (not shown) connecting the gate terminal (GTM), and an anodizing pad (not shown) connected to the anodizing bus line (SHg) are formed. To do.

(Step B, FIG. 12) After forming the anodic oxidation mask (AO) by direct drawing, a solution of 3% tartaric acid adjusted to pH 6.25 ± 0.05 with ammonia was diluted 1: 9 with ethylene glycol solution. The lower transparent glass substrate (SUB1) is dipped in an anodizing solution composed of the above solution and adjusted so that the formation current density is 0.5 mA / cm ² (constant current formation).

Next, an aluminum oxide film (A
Anodization is performed until the formation voltage of 125 V required to obtain OF) is reached.

After that, it is desirable to hold this state for several tens of minutes (constant voltage formation).

This is a uniform aluminum oxide film (AO
It is important in obtaining F).

Thereby, the conductive film (g1) is anodized, and the gate electrode (GT), the scanning signal line (GL), the counter electrode (CT), the counter voltage signal line (CL) and the electrode (P).
An anodized film (AOF) having a film thickness of 1800 angstrom is formed on L1).

(Step C, FIG. 12) A transparent conductive film (g2) made of an ITO film having a film thickness of 1400 Å is formed by sputtering.

After the photographic processing, the transparent conductive film (g2) is selectively etched with a mixed acid solution of hydrochloric acid and nitric acid as an etching solution, whereby the uppermost layer of the gate terminal (GTM),
Drain terminal (DTM) and counter electrode terminal (CTM)
Second conductive film is formed.

(Process D, FIG. 13) Ammonia gas, silane gas and nitrogen gas are introduced into the plasma CVD apparatus to form a silicon nitride film (Si) having a film thickness of 2200 Å.
NX) and silane gas and hydrogen gas are introduced into the plasma CVD apparatus, and the film thickness is 2000 angstrom i.
Type amorphous silicon (Si) film, plasma C
Hydrogen gas and phosphine gas are introduced into the VD apparatus to form an N (+)-type amorphous silicon (Si) film having a film thickness of 300 Å.

(Step E, FIG. 13) After the photoprocessing, sulfur hexafluoride (SF6) and carbon tetrachloride (CCl4) were used as dry etching gas, and N (+) type amorphous silicon (S) was used.
The island of the i-type semiconductor layer (AS) is formed by selectively etching the i) film and the i-type amorphous silicon (Si) film.

(Step F, FIG. 13) After photographic processing, using sulfur hexafluoride (SF6) as a dry etching gas,
The silicon nitride film is selectively etched.

(Step G, FIG. 14) A conductive film (d1) made of chromium (Cr) having a film thickness of 600 angstroms is provided by sputtering, and aluminum (Al) -tantalum (T) having a film thickness of 4000 angstroms (T).
a), a conductive film (d2) made of aluminum (Al) -titanium (Ti) -tantalum (Ta) or the like is provided by sputtering.

After the photographic treatment, the conductive film (d2) was etched with a mixed acid solution containing phosphoric acid, nitric acid, glacial acetic acid, and water in which the ratio of nitric acid was higher than that of the mixed acid solution of step A to form the conductive film (d1). Etching with a cerium-ammonium nitrate solution, video signal line (DL), source electrode (SD1), drain electrode (S
D2), a pixel electrode (PX), an electrode (PL2), a second conductive film of the common bus line (CB), a third conductive film and a bus line (SHd) (not shown) that short-circuits the drain terminal (DTM). Form.

By increasing the ratio of nitric acid to the mixed acid solution in step A, the resist material begins to peel off from the edge during etching, and the etching solution permeates from the edge to form a taper angle on the conductive film (d2). Granted.

In this embodiment, aluminum (Al) -tantalum (Ta), aluminum (Al) -titanium (T) is used.
i) -using a material such as tantalum (Ta), the conductive film (d
Although the taper is applied to 2), the taper can be applied to other metals by mixing nitric acid with the etching solution.

As the resist material used in this example, a semiconductor resist OFPR800 (trade name) manufactured by Tokyo Ohka Kogyo Co., Ltd. was used.

The taper angle can be controlled by changing the nitric acid concentration of the etching solution.

Next, carbon tetrachloride (CCl4) and sulfur hexafluoride (SF6) were introduced into the dry etching apparatus, and N
By etching the (+) type amorphous silicon (Si) film, the N (+) type semiconductor layer (d0) between the source and the drain is selectively removed.

(Step H, FIG. 14) Ammonia gas, silane gas and nitrogen gas are introduced into the plasma CVD apparatus to form a silicon nitride film having a film thickness of 1 μm.

After the photographic processing, the protective film (PSV) is formed by selectively etching the silicon nitride film by a photo-etching technique using sulfur hexafluoride (SF6) as a dry etching gas.

<< Display Panel (PNL) and Drive Circuit Board P
CB1 >> FIG. 15 is a display panel (PNL) shown in FIG.
FIG. 6 is a plan view showing a state in which a video signal drive circuit (H) and a vertical scanning circuit (V) are connected to each other.

In FIG. 15, CHI is a display panel (P
NL) are driving IC chips, the lower five in FIG. 15 are driving IC chips on the vertical scanning circuit side, and the ten left ones are driving IC chips on the video signal driving circuit side.

TCP is a tape carrier package in which a driving IC chip (CHI) is mounted by a tape automated bonding method (TAB) as will be described later with reference to FIGS. 16 and 17, and PCB1 is the tape carrier package (TCP). ), A capacitor, etc. are mounted on the drive circuit board, which is divided into two parts, one for the video signal drive circuit and one for the scanning signal drive circuit.

FGP is a frame ground pad,
The spring-like fragments provided by cutting in the shield case (SHD) are soldered.

FC is a flat cable that electrically connects the lower drive circuit board (PCB1) and the left drive circuit board (PCB1).

As the flat cable (FC), a plurality of lead wires (phosphor bronze material plated with tin (Sn)) sandwiched between a striped polyethylene layer and a polyvinyl alcohol layer are supported. use.

<< TCP Connection Structure >> FIG. 16 shows a scanning signal drive circuit (V) and a video signal drive circuit (H).
FIG. 17 is a cross-sectional view showing a cross-sectional structure of a tape carrier package (TCP) in which an integrated circuit chip (CHI) is mounted on a flexible wiring board, and FIG. 17 is a state in which it is connected to a liquid crystal display panel (PNL) (in FIG. 16, FIG. 3 is a cross-sectional view of essential parts showing a state where the scanning signal circuit terminal (GTM) is connected.

In FIG. 16, TTB is an integrated circuit (CH
I) is an input terminal / wiring part, and TTM is an integrated circuit (C
HI) output terminal / wiring part, and terminals (TTB, TT)
M) is made of, for example, copper (Cu), and each of the inner tip parts (commonly called inner leads) has an integrated circuit (CH).
The bonding pad (PAD) of I) is connected by the so-called face-down bonding method.

The tips (commonly called outer leads) outside the terminals (TTB, TTM) correspond to the input and output of the semiconductor integrated circuit chip (CHI), respectively, and are soldered to form a CRT / TFT conversion circuit / power supply circuit. (SUP),
Alternatively, the liquid crystal display panel (PNL) is connected by an anisotropic conductive film (ACF).

The tip of the package (TCP) is
The connection terminal (GTM) on the panel (PNL) side is connected to the panel so as to cover the exposed protective film (PSV), and therefore the external connection terminal (GTM) (or DTM).
Is covered with at least one of the protective film (PSV) and the package (TCP), and thus is resistant to electric contact.

BF1 is a base film made of polyimide or the like, and SRS is a solder resist film for masking the solder so that it will not stick to an unnecessary place during soldering.

The gap between the upper and lower glass substrates outside the seal pattern (SL) is protected by epoxy resin (EPX) after cleaning, and the package (TCP) and the upper substrate (SUB) are protected.
Silicone resin (SIL) is further filled between 2) to multiplex protection.

<< Drive Circuit Board (PCB2) >> The drive circuit board (PCB2) is mounted with electronic parts such as ICs, capacitors and resistors.

This drive circuit board (PCB2) has a power supply circuit for obtaining a plurality of divided and stabilized voltage sources from one voltage source, and a CRT (cathode ray tube) from a host (upper processing unit). The circuit (SUP) including a circuit for converting the information for (1) to the information for the (TFT) liquid crystal display device is mounted.

CJ is a connector connecting portion to which a connector (not shown) connected to the outside is connected.

The drive circuit board (PCB1) and the drive circuit board (PCB2) are electrically connected by a flat cable (FC).

<< Overall Structure of Liquid Crystal Display Module (MDL) >> FIG. 18 is an exploded perspective view showing each component of the liquid crystal display module (MDL).

SHD is a frame-shaped shield case (metal frame) made of a metal plate, LCW display window, PNL is a liquid crystal display panel, SPB is a light diffusion plate, LCB is a light guide,
RM is a reflection plate, BL is a backlight fluorescent tube, LCA is a backlight case, and the respective members are stacked in a vertical arrangement as shown in the figure to assemble a module MDL.

The entire module (MDL) is fixed by the claws and hooks provided on the shield case (SHD).

The backlight case (LCA) has a shape for accommodating a backlight fluorescent tube (BL), a light diffusion plate (SPB), a light guide (LCB), and a reflection plate (RM). The light of the backlight fluorescent tube (BL) arranged on the side surface of (LCB) is guided by the light guide (LCB) and the reflector (R).
M), a uniform diffusion backlight is provided on the display surface by the light diffusion plate (SPB), and the light is emitted to the liquid crystal display panel (PNL) side.

An inverter circuit board (PCB3) is connected to the backlight fluorescent tube (BL) and serves as a power source for the backlight fluorescent tube (BL).

As described above in detail, in this embodiment, when the alignment film (ORI1) is rubbed by giving a taper angle to the end face portion of the pixel electrode (PX),
A rubbing process near the end face of the pixel electrode (PX) can be smoothly and surely performed to eliminate the defective alignment region.
It is possible to obtain an active matrix type liquid crystal display device having a good contrast ratio.

[Embodiment 2] In this embodiment, the pixel electrode (P
By imparting a taper angle to both X) and the counter electrode (CT), misalignment in the vicinity of the counter electrode (CT) can be eliminated and a better contrast ratio can be obtained.

The present embodiment is the same as the first embodiment except for the configuration of the counter electrode (CT) and the manufacturing method related thereto, except for the following items.

FIG. 20 is a sectional view showing a section of a pixel (section taken along section line 3-3 shown in FIG. 1) of an active matrix type color liquid crystal display device which is another embodiment (Example 2) of the present invention. Is.

The counter electrode (CT) is the gate electrode (GT).
And a conductive film (g1) in the same layer as the scanning signal line (GL).

An aluminum (Al) anodic oxide film (AOF) is formed on the counter electrode (CT), and the conductive film (g1) of the counter electrode (CT) has a taper angle of 45 °. Is given.

Next, the manufacturing method of this embodiment will be described.

A lower transparent glass substrate (SU
Aluminum (Al) -tantalum (Ta) and aluminum (A) having a film thickness of 3000 angstroms on B1).
l) -Titanium (Ti) -Tantalum (Ta) or the like is used to form a conductive film (g1) by sputtering.

After the photographic treatment, the conductive film (g1) was etched with a mixed acid solution containing phosphoric acid, nitric acid, glacial acetic acid, and water in which the proportion of nitric acid was increased from that of the mixed acid solution of step A in Example 1 described above. The gate electrode (GT), the scanning signal line (GL), the counter electrode (CT), the counter voltage signal line (C
L), electrode (PL1), gate terminal (GTM), first conductive film of common bus line (CB), counter electrode terminal (CT)
M) a first conductive film, an anodizing bus line (SHg) (not shown) connecting the gate terminal (GTM), and an anodizing pad (not shown) connected to the anodizing bus line (SHg) are formed. To do.

As described above, in this embodiment, since the taper angle is also given to the end face portion of the counter electrode (CT), the pixel electrode (PX) is rubbed when the alignment film (ORI1) is rubbed.
Further, it is possible to obtain an active matrix type liquid crystal display device in which the rubbing treatment near the end face of the counter electrode (CT) can be smoothly and surely performed to eliminate the defective alignment region and the contrast ratio is better than that of the first embodiment. it can.

[Third Embodiment] The third embodiment is the same as the second embodiment.
Similarly to the above, by providing a taper angle to both the pixel electrode (PX) and the counter electrode (CT), the counter electrode (C
T) The alignment defect in the vicinity thereof is eliminated, and a better contrast ratio is obtained.

However, in the third embodiment, the pixel electrode (P
By forming the X) and the counter electrode (CT) in the same step, a taper angle is given to both of them at the same time, and it is the same as the first embodiment except for the following items.

FIG. 21 is a plan view showing a pixel portion and its periphery in the present embodiment, and FIG. 22 is a 3-dimensional view shown in FIG.
It is sectional drawing which shows the cross section in 3 cutting lines.

Here, as shown in FIG. 22, the pixel electrode (PX) and the counter electrode (CT) are formed in the same layer,
A taper angle is given to both end faces of the pixel electrode (PX) and the counter electrode (CT).

As a result, in the same manner as in Example 2, when rubbing the alignment film described later, the rubbing process was smoothly and surely performed near the end faces of the pixel electrode (PX) and the counter electrode (CT), and the alignment failure was caused. The area can be eliminated.

In this example, the pixel electrode (PX),
Since the counter electrode (CT), the video signal line (DL), the source electrode (SD1) and the drain electrode (SD2) are formed in the same layer in the same process, the video signal line (DL) and the source electrode (SD1) A similar taper angle is also given to the end surface of the drain electrode (SD2).

The counter electrode (CT) and the counter voltage signal line (CL) form a through hole (SH) in the gate insulating film (GI) and electrically connect them.

When the counter voltage signal line (CL) is made of an aluminum (Al) based conductive film (g1),
In order to establish the connection between the counter electrode (CT) and the counter voltage signal line (CL), the counter voltage signal line (CL) and the same material as the counter voltage signal line (CL) are not anodized.

In this case, the counter voltage signal line (C
L), and if chromium (Cr) is used as the conductive film formed in the same process with the same material, it is not necessary to perform anodic oxidation.

Further, by providing the counter voltage signal line (CL) in the same layer as the pixel electrode (PX), it is possible not to form the through hole (SH).

As described above, in this embodiment, in addition to the effect of the second embodiment, the step of taper etching is only one step.

In this embodiment, the counter electrode (CT) is formed in the same layer as the pixel electrode (PX) to give the taper angle in the same process.
Even if X) is formed in the same layer as the counter electrode (CT) in the same step, the same effect is obtained.

[Embodiment 4] This Embodiment 4 is different from Embodiment 1 in the manufacturing method by taper etching, and is therefore the same as Embodiment 1 except for the following manufacturing method.

In the fourth embodiment, the pixel electrode (PX) is etched by dry etching.
In this embodiment, when the pixel electrode (PX) is dry-etched, the oxygen asher simultaneously causes a chemical reaction with oxygen in the resist material to evaporate the side surface.

As a result, the resist is gradually removed from the side surfaces, and the electrodes are tapered and etched.

As a result, the same effects as those of the first embodiment can be obtained in the fourth embodiment.

The fourth embodiment can be combined with the second embodiment and the third embodiment, and the combination is within the scope of the present invention.

[Embodiment 5] In each of the above embodiments, a counter voltage is applied to the counter electrode (CT) which applies an electric field to the liquid crystal layer (LC) in a direction substantially parallel to the substrate between the pixel electrode (PX). In an active matrix color liquid crystal display device that supplies a counter voltage (Vcom) from a signal line (CL), at least one of the pixel electrode (PX) and the counter electrode (CT) has a taper angle.

On the other hand, in the present embodiment, in order to improve the aperture ratio of the pixel, the active matrix color which supplies the counter voltage (Vcom) from the adjacent scanning signal line (GL) to the counter electrode (CT). In liquid crystal display devices,
A taper angle is provided to at least one of the pixel electrode (PX) and the counter electrode (CT).

Structure of the present embodiment (electrode structure, or
Electrode materials, etc.) are the same as those in Example 1 except for the following items.
Alternatively, it is the same as in the second embodiment.

Next, the present embodiment will be described focusing on the points different from the first or second embodiment.

FIG. 23 is a plan view showing one pixel and its periphery of an active matrix type color liquid crystal display device which is another embodiment (embodiment 5) of the present invention.

As shown in FIG. 23, in the liquid crystal display device according to the present embodiment, the gate electrode (GT) and the counter electrode (CT) are continuously formed integrally with the check signal line (GL). It

Here, the counter electrode (CT) is connected to the scanning signal line (GL) of the immediately preceding line.

The cross section of the pixel in this embodiment (see FIG.
The cross section along the 3-3 section line) is the same as FIG. 3 or FIG.

FIG. 24 is a diagram showing an equalizing circuit of the display matrix portion (AR) and its peripheral circuits in the liquid crystal display device of this embodiment.

FIG. 24 is also a circuit diagram, but is drawn corresponding to the actual geometrical arrangement.

In FIG. 24, AR indicates a display matrix section (matrix array) in which a plurality of pixels are two-dimensionally arranged.

In FIG. 24, PX is a pixel electrode, and subscripts G, B and R are added corresponding to green, blue and red pixels, respectively.

GL is a scanning signal line, and y0, y2, y
3, ... Yend indicate the order of the scanning timing.

The scanning signal line (GL) is a vertical scanning circuit (V).
The video signal line (DL) is connected to the video signal drive circuit (H).

The circuit (SUP) is a power supply circuit for obtaining a plurality of divided and stabilized voltage sources from one voltage source and a CRT (cathode ray tube) from a host (upper processing unit).
Is a circuit including a circuit for exchanging information for use in (TFT) liquid crystal display device.

FIG. 25 is a diagram showing driving waveforms during driving in the liquid crystal display device of this embodiment. FIGS. 25 (a) and 25 (b) are (i-1) th and (i), respectively. The gate voltage (scanning signal voltage) (VG) supplied to the) th scanning signal line (GL) is shown.

In FIG. 25, (i) is an even number,
Therefore, the (i-1) th scanning signal line (GL) is an odd scanning signal line (GL), and the (i) th scanning signal line (GL) is an even scanning signal line (GL). Shows.

Further, FIG. 25C shows a video signal line (D
FIG. 25D shows a pixel electrode voltage (Vs) applied to the pixel electrode (PX) in the pixel on the (i) th row and the (j) th column. )
25E shows the voltage (VLC) applied to the liquid crystal layer (LC) of the pixel at row (i) and column (j).

In the driving method of the liquid crystal display device of this embodiment, since the counter voltage (Vcom) must be applied from the scan signal line (GL) to the counter electrode (CT), the scan signal line (GL) is supplied. The non-selection voltage of the gate voltage (VG) is changed for each frame by a binary rectangular wave of VGLH and VGLM or a binary rectangular wave of VGLM and VGLL.

Furthermore, the change of the non-selection voltage of the gate voltage (VG) supplied to the adjacent scanning signal line (GL) is prevented from becoming the same.

In the example shown in FIGS. 25A and 25B, the non-selection voltage of the gate voltage (VG) supplied to the (i-1) th scanning signal line (GL) is an odd frame. , VG
The non-selection voltage of the gate voltage (VG) supplied to the (i) th scan signal line (GL) is changed to an odd value by changing the binary value of LM and VGLL and the binary value of VGLH and VGLM in the even frame. Binary values of VGLH and VGLM for frames, VGLM, for even frames
Change with the binary value of VGLL.

In this case, the central potential of VGLH and VGLM is V
The central potential of GL1, VGLM and VGLL is VGL2, and the amplitude value of VGHL and VGLM and the amplitude value of VGLM and VGLL are equal to 2VB.

As described above, also in the fifth embodiment, it is possible to obtain the same effect as that of the first embodiment or the second embodiment.

[Embodiment 6] In this embodiment, as in Embodiment 5, as in Embodiment 3, the pixel electrode (PX) and the counter electrode (CT) are formed in the same step, so that both of them are simultaneously formed. Is provided with a taper angle, and is the same as the third and fifth embodiments except for the following items.

Next, the present embodiment will be described focusing on the points different from the third and fifth embodiments.

FIG. 26 is a plan view showing one pixel and its periphery of an active matrix type color liquid crystal display device which is another embodiment (embodiment 6) of the present invention.

As shown in FIG. 26, in the liquid crystal display device of this embodiment, the gate electrode (GT) is connected to the check signal line (G).
L) and is constructed continuously and integrally.

The counter electrode (CT) is connected to the previous scanning signal line (GL) via the through hole (SH).

The cross section of the pixel in this embodiment (see FIG.
22 is the same as that of FIG. 22.

In this case, when the scanning signal line (GL) is formed of the aluminum (Al) -based conductive film (g1), the counter electrode (CT) and the scanning signal line (GL) are connected to each other. In addition, the scanning signal line (GL), the same material as the scanning signal line (GL), and those formed in the same process are not anodized.

In this case, the scanning signal line (GL),
Further, if chromium (Cr) is used for the conductive film formed in the same process as the same material as that, it is not necessary to perform anodic oxidation.

As described above, also in the sixth embodiment, the same effect as in the third embodiment can be obtained.

Although the present invention has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and it goes without saying that various modifications can be made without departing from the scope of the invention.

[0321]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

(1) According to the present invention, in the active matrix type liquid crystal display device adopting the horizontal electric field method, at least one of the pixel electrode and the counter electrode is formed by taper etching, and the pixel electrode and the counter electrode are formed. Since the taper angle is given to at least one of the electrodes, when rubbing the alignment film, it is possible to smoothly and reliably perform the rubbing treatment near the end face of at least one of the pixel electrode and the counter electrode. It will be possible.

As a result, since the defective alignment region can be eliminated, light leakage in the vicinity of at least one of the pixel electrode and the counter electrode can be eliminated, the contrast ratio can be greatly improved, and the luminance due to rubbing can be improved. (Contrast) unevenness can be prevented.

This makes it possible to provide an active matrix type liquid crystal display device with high image quality.

[Brief description of drawings]

FIG. 1 is a plan view showing one pixel and its periphery of an active matrix type color liquid crystal display device which is an embodiment (embodiment 1) of the present invention.

2 is a cross-sectional view showing a cross section taken along a line 3-3 shown in FIG.

3 is a cross-sectional view showing a cross section of the thin film transistor (TFT) taken along section line 4-4 shown in FIG.

FIG. 4 shows a storage capacitance (C
It is sectional drawing which shows the cross section of stg).

FIG. 5 is a plan view for explaining the configuration of the matrix peripheral portion of the display panel (PNL) in the liquid crystal display device of the first embodiment.

FIG. 6 is a cross-sectional view showing a scanning signal terminal on the left side and a panel edge portion having no external connection terminal on the right side in the liquid crystal display device of the first embodiment.

FIG. 7 is a diagram showing a connection structure from a scanning signal line (GL) of a display matrix section (AR) to a gate terminal (GTM) which is an external connection terminal thereof in the liquid crystal display device of Example 1;

FIG. 8 is a diagram showing a connection from a video signal line (DL) of a display matrix section (AR) to a drain terminal (DTM) which is an external connection terminal thereof in the liquid crystal display device of Example 1;

FIG. 9 is a diagram showing a connection from a counter voltage signal line (CL) to a counter electrode terminal (CTM) which is an external connection terminal thereof in the liquid crystal display device of the first embodiment.

FIG. 10 is a diagram showing an equalizing circuit of a display matrix unit (AR) and its peripheral circuits in the liquid crystal display device of Example 1;

FIG. 11 is a diagram showing drive waveforms during driving in the liquid crystal display device of Example 1.

FIG. 12 is a flow chart of a cross-sectional view of a pixel portion and a gate terminal portion showing a manufacturing process of steps A to C on the lower transparent glass substrate (SUB1) side in the liquid crystal display device of Example 1.

FIG. 13 is a flow chart of a cross-sectional view of a pixel portion and a gate terminal portion showing a manufacturing process of steps D to F on the lower transparent glass substrate (SUB1) side in the liquid crystal display device of Example 1.

FIG. 14 is a flow chart of a cross-sectional view of a pixel portion and a gate terminal portion showing manufacturing steps of steps G to H on the lower transparent glass substrate (SUB1) side in the liquid crystal display device of Example 1.

FIG. 15 is a liquid crystal display panel (PNL) according to the first embodiment.
FIG. 4 is a plan view showing a state in which a peripheral drive circuit is mounted on the.

FIG. 16 is a tape carrier package (TCP) in which an integrated circuit chip (CHI) forming a drive circuit in the liquid crystal display device of Example 1 is mounted on a flexible wiring board.
It is sectional drawing which shows the cross-section of this.

FIG. 17 shows a liquid crystal display panel (PNL) of the tape carrier package (TCP) in the liquid crystal display device of the first embodiment.
FIG. 3 is a cross-sectional view of a main part showing a state in which it is connected to the scanning signal circuit terminal (GTM) of FIG.

FIG. 18 is an exploded perspective view of the liquid crystal display module in the liquid crystal display device of the first embodiment.

FIG. 19 is a diagram showing a relationship among an applied electric field direction, a rubbing direction, and a polarizing plate transmission axis in the liquid crystal display device of Example 1.

FIG. 20 is a cross-sectional view showing a cross section of a pixel (cross section taken along section line 3-3 of FIG. 1) in an active matrix type color liquid crystal display device which is another embodiment (Embodiment 2) of the present invention.

FIG. 21 is a plan view showing one pixel and its periphery of an active matrix type color liquid crystal display device which is another embodiment (Embodiment 3) of the present invention.

22 is a cross-sectional view of the pixel taken along the line 3-3 in FIG.

FIG. 23 is a plan view showing one pixel and its periphery of an active matrix type color liquid crystal display device which is another embodiment (embodiment 5) of the present invention.

FIG. 24 is a diagram showing an equalizing circuit of a display matrix section (AR) and its peripheral circuits in a liquid crystal display device of Example 5;

FIG. 25 is a diagram showing drive waveforms during driving in the liquid crystal display device of Example 5.

FIG. 26 is a plan view showing one pixel and its periphery of an active matrix type color liquid crystal display device which is another embodiment (embodiment 6) of the present invention.

[Explanation of symbols]

SUB ... Transparent glass substrate, GL ... Scanning signal line, DL ... Video signal line, CL ... Opposing voltage signal line, PX ... Pixel electrode, C
T ... Counter electrode, GI ... Insulating film, GT ... Gate electrode, AS
... i-type semiconductor layer, SD ... Source electrode or drain electrode, ORI ... Alignment film, POL ... Polarizing plate, OC ... Overcoat film, PSV ... Protective film, BM ... Light-shielding film, FIL ... Color filter, LC ... Liquid crystal layer, TFT ... Thin film transistor, g, d ... Conductive film, Cstg ... Storage capacitor, AOF ... Anodized film, AO ... Anodized mask, GTM ... Gate terminal, DTM ... Drain terminal, CB ... Common bus line, C
TM: counter electrode terminal, SHD: shield case, PNL
... Liquid crystal display panel, SPB ... Light diffusion plate, LCB ... Light guide, BL ... Backlight fluorescent tube, LCA ... Backlight case, RM ... Reflector.

Front Page Continuation (72) Inventor Kazuhiko Yanagawa 3300 Hayano, Mobara-shi, Chiba, Hitachi Ltd. Electronic Device Division (72) Inventor Masahiro Yanai 3300, Hayano, Mobara-shi, Chiba Hitachi Ltd. Electronic Device Division (72) ) Inventor Nobutake Konishi 3300 Hayano, Mobara-shi, Chiba Hitachi, Ltd. Electronic Devices Division

Claims (5)

[Claims] 1. A pair of substrates, a liquid crystal layer sandwiched between the pair of substrates, a plurality of active elements formed in a matrix on the one substrate, and connected to the plurality of active elements, respectively. A plurality of pixel electrodes, and a plurality of counter electrodes that are formed on one of the pair of substrates and that apply an electric field substantially parallel to the substrate surface to the liquid crystal layer between the pixel electrodes. In the active matrix liquid crystal display device having the above, the angle formed between the side surface of at least one of the pixel electrode and the counter electrode and the substrate surface is more than 0 degree and less than 90 degrees. . 2. The active matrix type liquid crystal display device according to claim 1, wherein an angle between a side surface of at least one of the pixel electrode and the counter electrode and a substrate surface is 45 degrees. 3. The method according to claim 1, wherein the counter electrode is formed in the same layer as the pixel electrode on the one substrate on which an active element is formed. Active matrix liquid crystal display device. 4. A pair of substrates, a liquid crystal layer sandwiched between the pair of substrates, a plurality of active elements formed in a matrix on the one substrate, and connected to the plurality of active elements, respectively. A plurality of pixel electrodes, and a plurality of counter electrodes that are formed on one of the pair of substrates and that apply an electric field substantially parallel to the substrate surface to the liquid crystal layer between the pixel electrodes. In the method for manufacturing an active matrix liquid crystal display device having the above-mentioned pixel electrode, a conductive film is formed, a photoresist film patterned by photolithography is formed on the conductive film, and then wet etching is performed using an etchant containing nitric acid. And a side surface of at least one of the pixel electrode and the counter electrode by forming at least one electrode of the counter electrode. The angle between the substrate surface and 0 degrees exceeds 90 degrees
A method for manufacturing an active matrix type liquid crystal display device, wherein 5. A pair of substrates, a liquid crystal layer sandwiched between the pair of substrates, a plurality of active elements formed in a matrix on the one substrate, and connected to the plurality of active elements, respectively. A plurality of pixel electrodes, and a plurality of counter electrodes that are formed on one of the pair of substrates and that apply an electric field substantially parallel to the substrate surface to the liquid crystal layer between the pixel electrodes. In the method of manufacturing an active matrix type liquid crystal display device having the above-mentioned pixel electrode, a conductive film is formed, a patterned photoresist film is formed on the conductive film by photolithography, and then dry etching is performed at the same time as the oxygen asher. And forming at least one electrode of the counter electrode so that the side surface of at least one of the pixel electrode and the counter electrode and the substrate. A method for manufacturing an active matrix type liquid crystal display device, characterized in that an angle formed by the surfaces is more than 0 degree and less than 90 degrees.