KR100538292B1 - In-plane switching mode liquid crystal display device and manufacturing method - Google Patents

In-plane switching mode liquid crystal display device and manufacturing method Download PDF

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KR100538292B1
KR100538292B1 KR1019970031684A KR19970031684A KR100538292B1 KR 100538292 B1 KR100538292 B1 KR 100538292B1 KR 1019970031684 A KR1019970031684 A KR 1019970031684A KR 19970031684 A KR19970031684 A KR 19970031684A KR 100538292 B1 KR100538292 B1 KR 100538292B1
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electrode
pixel electrode
pixel
liquid crystal
crystal display
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KR19990009313A (en
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심정욱
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삼성전자주식회사
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134363—Electrodes characterised by their geometrical arrangement for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13458—Terminal pads
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits

Abstract

게이트 공정에서 게이트 전극과 공통 전극을 형성하는 과정에서 화소 전극(sub-pixel data electrode)을 함께 형성하고, 콘택 공정에서 화소 전극의 일부에 접촉 구멍을 형성하여 데이터선과 전기적으로 접촉하도록 하여 평면내 스위칭 모드박막 트랜지스터 액정 표시 장치의 박막 트랜지스터 기판을 제조한다. 공통 전극과 화소 전극을 같은 층에 형성하면 오정렬(miss-align)이 발생하지 않으므로 사진 식각 공정의 각 샷(shot)에서 전극 사이의 거리가 동일하게 되고 이에 따라 샷별 전기 광학적 특성이 동일하게 되므로 패널의 시각 특성이 향상되고, 단일의 공정 조건으로 금속 식각을 하여 전극 간격을 안정적으로 유지할 수 있어 공정적 안정성을 확보할 수 있다. Sub-pixel data electrodes are formed together in the process of forming the gate electrode and the common electrode in the gate process, and contact holes are formed in a part of the pixel electrode in the contact process to make electrical contact with the data lines. A thin film transistor substrate of a mode thin film transistor liquid crystal display device is manufactured. If the common electrode and the pixel electrode are formed on the same layer, no misalignment occurs, and thus the distance between the electrodes is the same in each shot of the photolithography process, and thus the electro-optical characteristics of each shot are the same. The visual characteristics of the can be improved, and the electrode gap can be stably maintained by etching the metal under a single process condition, thereby ensuring the process stability.

Description

평면내 스위칭 모드 액정 표시 장치 및 제조 방법In-plane switching mode liquid crystal display device and manufacturing method

이 발명은 액정 표시 장치 및 그 제조 방법에 관한 것으로서, 특히 평면내 스위칭 모드 액정 표시 장치 및 그 제조 방법에 관한 것이다.TECHNICAL FIELD This invention relates to a liquid crystal display device and its manufacturing method. Specifically, It is related with the in-plane switching mode liquid crystal display device and its manufacturing method.

최근 개발된 평면내 스위칭(IPS ; in-plane switching) 모드 박막 트랜지스터 액정 표시 장치에서는 전기장이 액정 표시 장치의 패널에 평행하게 형성되도록 전극을 배치한다. 이러한 평행한 방향의 전기장을 얻기 위해서는 종래의 박막 트랜지스터 액정 표시 장치와는 달리 한쪽 기판, 즉 박막 트랜지스터 기판 쪽에만 전극을 형성하며, 화소 내에서 공통 전극과 화소 전극이 평행하게 교대로 위치해야 한다. 또한, 박막 트랜지스터 액정 표시 장치에서는 또한 축적 용량(storage capacitor)이 필요한데, 이는 두 금속층 사이, 즉 공통 전극선과 화소 전극선 사이에 형성된다. In the recently developed in-plane switching (IPS) mode thin film transistor liquid crystal display device, an electrode is disposed so that an electric field is formed parallel to the panel of the liquid crystal display device. Unlike the conventional thin film transistor liquid crystal display, in order to obtain the electric field in the parallel direction, electrodes are formed only on one substrate, that is, the thin film transistor substrate, and the common electrode and the pixel electrode are alternately positioned in the pixel. In addition, a thin film transistor liquid crystal display also requires a storage capacitor, which is formed between the two metal layers, that is, between the common electrode line and the pixel electrode line.

종래 기술에 따른 IPS 박막 트랜지스터 액정 표시 장치가 도 1에 나타나 있다. 이 장치는 다음과 같은 순서에 의해 제조된다. 먼저 게이트 공정에서 게이트 전극(1)과 공통 전극(2)을 형성한다. 다음 액티브 공정에서 절연막을 형성하고, 비정질 실리콘층과 저항 접촉층(ohmic contact layer)을 연속적으로 증착하여 액티브층(3)을 형성한다. 다음 콘택 공정에서 패드 부분을 형성하기 위하여 절연막을 식각한다. 그 후, 소스/드레인 공정에서 데이터선(4)과 화소 전극(5)을 형성한다. 마지막으로 보호막 공정에서 보호막을 형성한다. A conventional IPS thin film transistor liquid crystal display device is shown in FIG. 1. This device is manufactured in the following order. First, the gate electrode 1 and the common electrode 2 are formed in the gate process. Next, an insulating film is formed in an active process, and an active layer 3 is formed by continuously depositing an amorphous silicon layer and an ohmic contact layer. Next, the insulating film is etched to form the pad portion in the contact process. Thereafter, the data line 4 and the pixel electrode 5 are formed in the source / drain process. Finally, a protective film is formed in the protective film process.

위와 같은 공정 순서에 의해 박막 트랜지스터 기판을 형성하면 공통 전극과 화소 전극이 별도의 공정에서 진행되므로 공통 전극선과 화소 전극선이 서로 다른 층에 형성되어 그에 따른 문제점이 발생한다. When the thin film transistor substrate is formed by the above process sequence, the common electrode and the pixel electrode are processed in separate processes, and thus the common electrode line and the pixel electrode line are formed on different layers, thereby causing a problem.

우선, 각 층을 식각하기 위해서는 사진 식각(photolithography) 공정을 거치는데 각층의 오정렬(miss-align)에 의해 전극 사이의 거리가 사진 식각 공정의 각 샷(shot)마다 다르면 샷별 전기 광학적 특성이 달라 패널 구동시 휘도의 노광 샷별 유의차가 발생하여 시인성이 나빠진다. 이는 평면내 구동 방식을 이용하는 경우 전극 간격에 의하여 전기 광학적 특성이 변하기 때문이다. 또한 식각 공정에서 식각의 정도가 하부막에 의해 영향을 받게 되므로 다른 하부막에서의 각 층별 식각 조건을 확립해야 한다. 그리고, 전극과 전극 사이에 절연막에 의한 높이 차이가 존재하므로 전기장의 왜곡이 발생하고, 그에 따라 잔상의 요인으로 작용한다. First, each layer is etched through photolithography process. If the distance between electrodes is different for each shot in the photolithography process due to the misalignment of each layer, the electro-optical characteristics of each shot are different. Significant differences in the exposure shots of the luminance are generated during driving, resulting in poor visibility. This is because the electro-optic characteristic is changed by the electrode spacing when using the in-plane driving method. In addition, since the degree of etching is affected by the lower layer in the etching process, it is necessary to establish the etching conditions for each layer in the other lower layer. In addition, since there is a height difference between the electrodes and the electrodes due to the insulating film, distortion of the electric field occurs, thereby acting as an afterimage factor.

본 발명에서는 표시 장치의 특성을 향상시키고 제조 공정을 안정화시킬 수 있는 IPS 모드 박막 트랜지스터 액정 표시 장치 및 그 제조 방법을 제공하고자 한다.An object of the present invention is to provide an IPS mode thin film transistor liquid crystal display and a method of manufacturing the same, which can improve characteristics of a display device and stabilize a manufacturing process.

위와 같은 과제를 해결하기 위하여 본 발명에서는 공통 전극과 화소 전극을 동일한 공정을 통해 동일한 층으로 형성한다.In order to solve the above problems, in the present invention, the common electrode and the pixel electrode are formed in the same layer through the same process.

이제 첨부한 도면을 참고로 하여, 본 발명의 실시예에 대하여 상세히 설명한다. Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

본 발명의 실시예에 따른 액정 표시 장치의 제조 공정은 도 2에 나타난 바와 같은 5단계의 공정으로 이루어진다. 즉, 게이트 공정, 액티브 공정, 콘택 공정, 소스/드레인 공정 및 보호막 공정이다. The manufacturing process of the liquid crystal display according to the exemplary embodiment of the present invention includes a five step process as shown in FIG. 2. That is, it is a gate process, an active process, a contact process, a source / drain process, and a protective film process.

먼저, 게이트 공정에서는 게이트 전극(1)과 공통 전극(2)을 형성하며, 이 때 화소 전극(5)을 함께 형성한다. 화소 전극(5)과 공통 전극(2)은 같은 공정에서 함께 형성되므로 같은 층에 위치하게 된다. 이와 같이 공통 전극(2)과 화소 전극(5)이 같은 층에 위치하게 되면, 층별 오정렬(miss-align)이 발생하지 않으므로 사진 식각(photolithography) 공정의 각 샷(shot)에서 전극 사이의 거리가 동일하게 되고 이에 따라 샷별 전기 광학적 특성이 동일하게 되므로 패널의 시각 특성이 향상된다. 이 때 전극 재료로는 전극의 테이퍼(taper) 각을 조정하기 위해 몰리브덴-텅스텐(Mo-W)을 사용한다.First, in the gate process, the gate electrode 1 and the common electrode 2 are formed, and the pixel electrode 5 is formed together. Since the pixel electrode 5 and the common electrode 2 are formed together in the same process, they are positioned on the same layer. As such, when the common electrode 2 and the pixel electrode 5 are positioned on the same layer, the distance between the electrodes in each shot of the photolithography process does not occur because layer misalignment does not occur. The visual characteristics of the panel are improved because the same and thus the electro-optical characteristics for each shot are the same. At this time, as the electrode material, molybdenum-tungsten (Mo-W) is used to adjust the taper angle of the electrode.

다음 액티브 공정에서 절연막을 형성하고, 비정질 실리콘층(a-Si)과 저항 콘택층(n+ a-Si)을 연속적으로 증착하여 액티브층(3)을 형성한다. 이 때 절연막은 SiNx, SiOx 또는 유기 절연막 등을 사용할 수 있다. Next, an insulating film is formed in the active process, and the active layer 3 is formed by successively depositing an amorphous silicon layer (a-Si) and a resistive contact layer (n + a-Si). At this time, SiNx, SiOx, an organic insulating film, etc. can be used for an insulating film.

다음으로 콘택 공정을 실시하는데, 패드 부분을 형성하기 위하여 절연막을 식각하고, 화소 전극(5) 위의 절연막 일부분을 식각하여 데이터선과 접촉하기 위한 접촉 구멍(6)을 형성한다. Next, a contact process is performed, in which an insulating film is etched to form a pad portion, and a portion of the insulating film on the pixel electrode 5 is etched to form a contact hole 6 for contacting the data line.

다음, 소스/드레인 공정에서 데이터선(4) 및 소스 전극(7)을 형성하고 이 소스 전극(7)이 콘택 공정에서 형성된 화소 전극(6) 위의 접촉 구멍과 전기적으로 접촉된다. 이 때의 식각 공정은 동일한 층에 형성된 절연막을 식각하는 것이므로 동일한 조건에서 식각이 이루어지게 되어 층별로 별도의 식각 조건을 확립할 필요가 없으며 전극 간격을 안정적으로 유지할 수 있으므로 공정적 안정성을 확보할 수 있다. Next, the data line 4 and the source electrode 7 are formed in the source / drain process, and the source electrode 7 is in electrical contact with the contact hole on the pixel electrode 6 formed in the contact process. At this time, since the etching process is to etch the insulating film formed on the same layer, etching is performed under the same conditions, so it is not necessary to establish separate etching conditions for each layer, and it is possible to secure process stability because the electrode gap can be maintained stably. have.

마지막으로 보호막 공정에서 보호막을 형성한다. 보호막으로는 SiNx, SiOx, 유기 절연막 등을 사용한다. Finally, a protective film is formed in the protective film process. SiNx, SiOx, an organic insulating film, etc. are used as a protective film.

본 발명에서는 공통 전극과 화소 전극을 같은 층에 형성하여 박막 트랜지스터 기판을 제작함으로써 오정렬(miss-align)에 의한 전기 광학 특성의 유의차를 없애고, 단일의 공정 조건으로 금속 식각을 하여 전극 간격을 안정적으로 유지할 수 있어 공정적 안정성을 확보할 수 있다. In the present invention, the common electrode and the pixel electrode are formed on the same layer to fabricate a thin film transistor substrate, thereby eliminating significant differences in electro-optic characteristics due to miss-alignment, and etching the metal under a single process condition to stabilize the electrode gap. Can be maintained to ensure process stability.

도 1은 종래 기술에 따른 평면내 스위칭 모드 박막 트랜지스터 액정 표시 장치의 박막 트랜지스터 기판의 평면도이고,1 is a plan view of a thin film transistor substrate of an in-plane switching mode thin film transistor liquid crystal display device according to the prior art,

도 2는 본 발명의 실시예에 따른 평면내 스위칭 모드 박막 트랜지스터 액정 표시 장치의 박막 트랜지스터 기판의 제조 과정을 나타낸 흐름도이고,2 is a flowchart illustrating a manufacturing process of a thin film transistor substrate of an in-plane switching mode thin film transistor liquid crystal display device according to an exemplary embodiment of the present invention.

도 3은 본 발명의 실시예에 따른 평면내 스위칭 모드 박막 트랜지스터 액정 표시 장치의 박막 트랜지스터 기판의 평면도이다.3 is a plan view of a thin film transistor substrate of an in-plane switching mode thin film transistor liquid crystal display according to an exemplary embodiment of the present invention.

Claims (4)

기판 위에 게이트 전극과 공통 전극 및 화소 전극을 동일한 물질로 동일한 공정을 통하여 동일한 층에 형성하는 단계,Forming a gate electrode, a common electrode, and a pixel electrode on the same layer using the same material on the substrate through the same process; 상기 게이트 전극, 상기 공통 전극 및 상기 화소 전극을 덮는 절연막을 형성하는 단계,Forming an insulating layer covering the gate electrode, the common electrode, and the pixel electrode; 상기 절연막의 상부에 상기 게이트 전극과 중첩하는 비정질 실리콘층과 저항 콘택층을 연속적으로 증착하는 단계,Continuously depositing an amorphous silicon layer and an ohmic contact layer overlapping the gate electrode on the insulating layer; 상기 화소 전극 위의 상기 절연막의 일부분을 식각하여 접촉 구멍을 형성하는 단계,Etching a portion of the insulating film on the pixel electrode to form a contact hole; 데이터선 및 소스 전극을 형성하는 단계를 포함하며,Forming a data line and a source electrode; 상기 소스 전극은 상기 접촉 구멍을 통하여 화소 전극과 전기적으로 연결되도록 형성하고,The source electrode is formed to be electrically connected to the pixel electrode through the contact hole. 상기 게이트 전극, 공통 전극, 화소 전극, 데이터선 및 소스 전극은 몰리브덴-텅스텐으로 형성하는 액정 표시 장치의 제조 방법.The gate electrode, the common electrode, the pixel electrode, the data line and the source electrode are formed of molybdenum-tungsten. 제1항에서,In claim 1, 상기 절연막은 질화규소, 산화규소, 유기 절연막으로 형성하는 액정 표시 장치의 제조 방법.And the insulating film is formed of silicon nitride, silicon oxide, or an organic insulating film. 제1항에서,In claim 1, 상기 게이트 전극, 공통 전극, 화소 전극, 데이터선 및 소스 전극은 테이퍼지도록 형성되어 있으며, 몰리브덴-텅스텐으로 형성되어 테이퍼각을 조절할 수 있는 액정 표시 장치의 제조 방법.The gate electrode, the common electrode, the pixel electrode, the data line and the source electrode are formed to be tapered, and formed of molybdenum-tungsten to control the taper angle. 게이트 전극 및 소스 전극을 포함하는 박막 트랜지스터 소자; A thin film transistor element including a gate electrode and a source electrode; 상기 소스 전극과 전기적으로 연결된 화소 전극; 및 A pixel electrode electrically connected to the source electrode; And 상기 화소 전극과 평행하게 형성되어 있는 공통 전극을 포함하며, A common electrode formed in parallel with the pixel electrode; 상기 화소 전극, 상기 게이트 전극 및 상기 공통 전극은 동일한 물질로 동일한 공정을 통하여 동일한 층에 형성되어 있으며, The pixel electrode, the gate electrode and the common electrode are formed on the same layer through the same process using the same material. 상기 화소 전극, 상기 게이트 전극 및 상기 공통 전극은 기판 위에 형성되어 있는 액정 표시 장치.And the pixel electrode, the gate electrode, and the common electrode are formed on a substrate.
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07128683A (en) * 1993-11-04 1995-05-19 Matsushita Electric Ind Co Ltd Thin film transistor integrated device
JPH0961842A (en) * 1995-08-21 1997-03-07 Matsushita Electric Ind Co Ltd Active matrix type liquid crystal display device
JPH0990410A (en) * 1995-09-20 1997-04-04 Hitachi Ltd Active matrix type liquid crystal display device and its manufacture
JPH09236820A (en) * 1996-02-29 1997-09-09 Hosiden Corp Liquid crystal display device
KR19990003546A (en) * 1997-06-25 1999-01-15 김영환 Liquid Crystal Display and Manufacturing Method Thereof

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07128683A (en) * 1993-11-04 1995-05-19 Matsushita Electric Ind Co Ltd Thin film transistor integrated device
JPH0961842A (en) * 1995-08-21 1997-03-07 Matsushita Electric Ind Co Ltd Active matrix type liquid crystal display device
JPH0990410A (en) * 1995-09-20 1997-04-04 Hitachi Ltd Active matrix type liquid crystal display device and its manufacture
JPH09236820A (en) * 1996-02-29 1997-09-09 Hosiden Corp Liquid crystal display device
KR19990003546A (en) * 1997-06-25 1999-01-15 김영환 Liquid Crystal Display and Manufacturing Method Thereof

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