JP2001033824A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To embody a technique of forming pixel regions of a high aperture ratio by providing a method for forming holding capacitors with a liquid crystal display device of an IPS system. SOLUTION: The surfaces of common electrodes 103 formed on insulating films, more particularly resin films, used for the respective circuits of an electro- optic device as represented by an LCD consisting of the IPS system are covered with anodically oxidized films by executing an anodic oxidation stage at >=11 V/min in impressed voltage/power feed time, by which the infiltrating amount may be decreased and the liquid crystal display device having the electrodes of an excellent adhesion property and having high reliability may be manufactured.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a circuit constituted by thin film transistors (hereinafter, referred to as TFTs) and a method for manufacturing the same. For example, the present invention relates to an electro-optical device typified by a liquid crystal display panel and an electronic device equipped with such an electro-optical device as a component.

[0002] In this specification, a semiconductor device generally refers to a device that can function by utilizing semiconductor characteristics, and an electro-optical device, a semiconductor circuit, and an electronic device are all semiconductor devices.

[0003]

2. Description of the Related Art In recent years, a technique of forming a thin film transistor (TFT) using a semiconductor thin film (having a thickness of several to several hundred nm) formed on a substrate having an insulating surface has attracted attention. Thin film transistors are widely applied to electronic devices such as ICs and electro-optical devices, and are particularly rapidly developed as switching elements for image display devices.

For example, in a liquid crystal display device, a TFT is arranged in each of millions of pixels arranged in a matrix, and the electric charge applied to each pixel electrode is controlled by a switching function of the TFT, so that a liquid crystal display device has a liquid crystal display device. Change the electro-optical properties,
The image is displayed by controlling the light transmitted through the liquid crystal panel.

In such a method of driving a liquid crystal display device, an IPS system for driving a liquid crystal display device by controlling an electric field in a lateral direction with respect to a substrate by a parallel electrode structure (Japanese Patent Application Laid-Open No. Hei 6-1994).
No. 160878).

A liquid crystal display device driven by this IPS system can be driven at a low voltage, and can be driven by another driving system (TN system,
STN method, etc.).

The IPS type liquid crystal display device includes a TFT, a gate line, a source line, a pixel electrode, a common line, and a common electrode extending from the common line in a pixel region on the same substrate. In order to prevent an electric field applied to the pixel electrode from affecting other pixels, each pixel electrode is sandwiched between common electrodes arranged in parallel with the pixel electrode. Therefore, the IPS mode liquid crystal display device
The electrode area of these electrodes is required, and the aperture ratio is reduced.

Generally, in a liquid crystal display device, it is necessary to form a storage capacitor in order to secure a charge holding time. Also in the IPS type liquid crystal display device, a sufficient electrode area is required to form a storage capacitor, so that the aperture ratio is reduced.

Further, when the wiring and electrodes are miniaturized to improve the aperture ratio, it is difficult to secure a sufficient storage capacitance.

[0010]

The invention disclosed in this specification provides a technique for solving the above-mentioned conventional problems. That is, an object of the present invention is to propose a method for forming a storage capacitor in an IPS mode liquid crystal display device and provide a technique for forming a pixel region having a high aperture ratio.

[0011]

The invention disclosed in this specification has a pair of substrates and a liquid crystal layer sandwiched between the pair of substrates. One of the pair of substrates has one of the substrates. In a semiconductor device in which a pixel electrode is formed and an electric field parallel to a substrate surface is applied between the pixel electrode and the common electrode,
A common electrode, an oxide film on at least a part of the common electrode,
A semiconductor device including a capacitor formed by a pixel electrode provided on the oxide film.

Further, in the above structure, the common electrode is made of a material that can be anodized.

According to another aspect of the present invention, there is provided a liquid crystal display device having a pair of substrates and a liquid crystal layer sandwiched between the pair of substrates, wherein a pixel electrode is formed on one of the pair of substrates. ,
In a semiconductor device for applying an electric field parallel to a substrate surface between the pixel electrode and the common electrode, a common electrode, an anodic oxide film on at least a part of the common electrode, and provided on the anodic oxide film A semiconductor device comprising a capacitor formed with a pixel electrode, wherein the liquid crystal layer is surrounded by a sealing material, and a spacer is formed in a region where the sealing material is formed.

According to another aspect of the invention, a pixel electrode is formed on one of the pair of substrates having a pair of substrates and a liquid crystal layer sandwiched between the pair of substrates. ,
In a semiconductor device for applying an electric field parallel to a substrate surface between the pixel electrode and the common electrode, a common electrode, an anodic oxide film on at least a part of the common electrode, and provided on the anodic oxide film A capacitor formed with a pixel electrode, wherein a spacer is formed in a region between a pixel portion provided with the pixel electrode and a driver circuit and a region where no element of the driver circuit exists. It is a semiconductor device.

According to another aspect of the present invention, there is provided a liquid crystal display device having a pair of substrates and a liquid crystal layer sandwiched between the pair of substrates, wherein a pixel electrode is formed on one of the pair of substrates. ,
In a semiconductor device for applying an electric field parallel to a substrate surface between the pixel electrode and the common electrode, a common electrode, an anodic oxide film on at least a part of the common electrode, and provided on the anodic oxide film A semiconductor device, comprising: a capacitor formed by a pixel electrode; and a spacer on a contact portion of the pixel electrode.

Further, in each of the above structures, the oxide film is formed through an anodizing step in which an applied voltage / power supply time is 11 V / min or more.

Further, the invention for realizing the above structure includes a step of forming a resin film above the TFT, a step of forming a common electrode on the resin film, and a step of forming an oxide film of the common electrode. And forming a pixel electrode covering at least a part of the oxide film, wherein a capacitor is formed by the common electrode, the oxide film of the common electrode, and the pixel electrode. This is a method for manufacturing a semiconductor device, which is a feature.

In another aspect of the invention, a step of forming a resin film above the TFT, a step of forming an inorganic film on the resin film, a step of forming a common electrode on the inorganic film, Forming an oxide film of the common electrode, and forming a pixel electrode covering at least a part of the oxide film, wherein the capacitance is the common electrode, the oxide film of the common electrode, and the pixel A method for manufacturing a semiconductor device, which is formed using electrodes.

Further, in each of the above structures, the step of forming the inorganic film on the resin film is formed by a sputtering method.

In each of the above structures, the step of forming the oxide film of the common electrode includes the step of applying an applied voltage / power supply time of 11 times.
The anodic oxidation step is at least V / min.

[0021]

Embodiments of the present invention will be described below.

In the present invention, FIG. 1 (A) and FIG.
As shown in (B), a first material made of an anodizable material is used.
(Common electrode 103), an oxide film 105 is provided on the surface of the electrode, and a second electrode (pixel electrode 104) is further provided on the oxide film. It is characterized in that a storage capacitor 106 as a body is formed. 1A and 1B, 1
01 is a gate line, 101a and 101b are gate electrodes extending from the gate line, and 102 is a source line.

In the present invention, a liquid crystal display device is controlled by controlling an electric field in a lateral direction (a direction parallel to a substrate) formed by a first electrode (common electrode 103) and a second electrode (pixel electrode 104). A driving IPS method is used. In addition, FIG.
FIG. 2 is an equivalent circuit diagram corresponding to FIG. 1 (A) and FIG. 1 (B).

The anodizable material used in the present invention includes a valve metal film (for example, aluminum, tantalum film, niobium film, hafnium film, zirconium film, chromium film, titanium film, etc.) and a conductive silicon film ( For example, a phosphorus-doped silicon film, a boron-doped silicon film, or the like) may be used, or a silicide film obtained by silicidizing the valve metal film or a nitrided valve metal film (such as a tantalum nitride film, a tungsten nitride film, or a titanium nitride film) may be used as a main component. Can be used. Further, an alloy (eg, a molybdenum tantalum alloy or the like) which is a eutectic with another metal element (such as a tungsten film or a molybdenum film) can also be used.
Further, these may be freely combined and laminated.

The term "valve metal" refers to a metal in which a barrier-type anodic oxide film formed as an anode allows a cathode current to flow but does not allow an anode current to flow, that is, a metal exhibiting a valve action.
(Electrochemical Handbook 4th edition; edited by The Electrochemical Society, p370,
Maruzen, 1985)

The structure of the first electrode (common electrode 103) made of the above-mentioned anodizable material may be a single-layered electrode or a multi-layered electrode. In FIG. 1A, the first electrode (the common electrode 103) can be operated in a floating state (an electrically isolated state); however, the pixel electrode shown in FIG. May be set to a level near the common potential (intermediate potential of the image signal sent as data) without flicker. Further, as in the case of the electrode shape shown in FIG. 13, a function of a shielding film for shielding light or electromagnetic waves may be provided. In FIG. 1A, the second
Although the example in which the shape of the electrode (pixel electrode 104) is T-shaped is shown, the present invention is not particularly limited. For example, the shape of the pixel electrode may be a zigzag shape as shown in FIG. 14, a "-" shape as shown in FIG. 15, or a shape as shown in FIG.

[0027] In this specification, the term "electrode" refers to
It is a part of the “wiring” and refers to a portion where electrical connection with another wiring or a portion intersecting with a semiconductor layer is made. Therefore,
For convenience of explanation, we use "wiring" and "electrode" properly,
It is assumed that the term “electrode” always includes “wiring”.

Further, the anodic oxidation method of the present invention is a conventional method (a method in which a current and a voltage flowing between an anode and a cathode immersed in an anodizing solution are shifted from a constant current state to a constant voltage state).
Use a different method. In a conventional method, a material film having poor adhesion to an anodizable material, for example, an organic resin film is used as a base and an electrode is provided thereon, and when the electrode is anodized, the nonuniform anodic oxidation at the electrode end is inevitable. Was performed, and film peeling occurred due to the wraparound of the anodic oxide film.

Therefore, in the present invention, as compared with the prior art,
In the anodic oxidation step of the present invention, the current value per unit area of the electrode to be anodized and the applied voltage value per unit time are set to large values, and when the process is completed when the target voltage is reached, the amount of wrap around is reduced. Was completed. In addition, in order to reduce the time required for the anodic oxidation step, the anodic oxide film is formed by setting the time in the constant voltage state to several seconds to several minutes or setting the time in the constant voltage state to zero.

An example of the forming method of the present invention will be described below with reference to FIG. It should be noted that the voltage becomes zero when the anodic oxidation step is completed, but it is not shown in FIG.

Specifically, the current density (current amount per unit area) of the electrode to be anodized is 1 to 20 mA.
/ Cm ² . Note that the current density is higher than the conventional current density (about 0.3 mA / cm ² ).

The voltage increase rate (voltage value increased per unit time) is set to 11 V / min or more, preferably 100 V / min or more. Similarly, it is larger than the conventional voltage rising rate (about 10 V / min).

FIG. 8 is a sectional view of an LCD using an anodic oxide film utilizing the present invention as a dielectric of a storage capacitor arranged in a pixel portion. Here, a CMOS circuit is shown as a basic circuit constituting a driver circuit, and a double-gate TFT is shown as a TFT in a pixel portion. Of course, not only the double gate structure but also a triple gate structure or a single gate structure may be used. Also, TF
The structure of T is not limited to a top gate type TFT, but can be applied to other structures, for example, a bottom gate type TFT.

The present invention having the above configuration will be described in more detail with reference to the following embodiments.

[0035]

[Embodiment 1] FIG. 4 shows an embodiment of the present invention.
This will be described with reference to FIG. Here, a method for simultaneously manufacturing a pixel portion and a driver circuit for driving the pixel portion over the same substrate will be described. However, for the sake of simplicity, the driving circuit shows a CMOS circuit which is a basic circuit such as a shift register circuit and a buffer circuit, and an n-channel TFT forming a sampling circuit.

In FIG. 4A, it is desirable to use a quartz substrate or a silicon substrate for the substrate 401. In this embodiment, a quartz substrate was used. Alternatively, a substrate obtained by forming an insulating film on the surface of a metal substrate or a stainless steel substrate may be used as the substrate. In the case of this embodiment, since heat resistance that can withstand a temperature of 800 ° C. or more is required, any substrate may be used as long as it meets the requirement.

The surface of the substrate 401 where the TFT is to be formed is 20 to 100 nm (preferably 40 to 80 nm).
A semiconductor film 402 having an amorphous structure with a thickness of m) is formed by a low pressure thermal CVD method, a plasma CVD method, or a sputtering method. In this embodiment, an amorphous silicon film having a thickness of 60 nm is formed. However, since a thermal oxidation step is performed later, this film thickness does not necessarily become the final film thickness of the active layer of the TFT.

The semiconductor film having an amorphous structure includes an amorphous semiconductor film and a microcrystalline semiconductor film, and further includes a compound semiconductor film having an amorphous structure such as an amorphous silicon germanium film. . Further, it is also effective to continuously form a base film and an amorphous silicon film on a substrate without exposing them to the atmosphere. By doing so, it becomes possible to prevent contamination of the substrate surface from affecting the amorphous silicon film, and it is possible to reduce the variation in characteristics of the TFT to be manufactured.

Next, a mask film 403 made of an insulating film containing silicon (silicon) is formed on the amorphous silicon film 402, and openings 404a and 404b are formed by patterning. The opening serves as an addition region for adding a catalyst element that promotes crystallization in the next crystallization step.
(FIG. 4 (A))

Note that as the insulating film containing silicon, a silicon oxide film, a silicon nitride film, or a silicon nitride oxide film can be used. The silicon nitride oxide film is an insulating film containing silicon, nitrogen, and oxygen in predetermined amounts, and is an insulating film represented by SiOxNy. Silicon nitride oxide film is Si
H ₄ , N ₂ O, and NH ₃ can be produced as source gases, and the nitrogen concentration is 25 atomic% or more and 50 a
It is good to be less than tomic%.

At the same time as the patterning of the mask film 403 is performed, a marker pattern to be used as a reference in a subsequent patterning step is formed. When the mask film 403 is etched, the amorphous silicon film 402 is also slightly etched, but this step can be used as a marker pattern later when the mask is aligned.

Next, a semiconductor film having a crystal structure is formed according to the technique described in Japanese Patent Application Laid-Open No. Hei 10-247735 (corresponding to US application Ser. No. 09 / 034,041). The technology described in the publication discloses a catalyst element (nickel, cobalt, germanium, tin, lead, palladium, etc.) that promotes crystallization during crystallization of a semiconductor film having an amorphous structure.
Crystallization means using one or more elements selected from iron and copper).

Specifically, heat treatment is performed in a state where a catalyst element is held on the surface of the semiconductor film including the amorphous structure, and the semiconductor film including the amorphous structure is changed to a semiconductor film including the crystalline structure. It is to let. As the crystallization means, the technique described in Example 1 of JP-A-7-130652 may be used. In addition, a semiconductor film including a crystalline structure includes a so-called single crystal semiconductor film and a polycrystalline semiconductor film, and a semiconductor film including a crystal structure formed in the publication has a crystal grain boundary.

In this publication, a spin-coating method is used when a layer containing a catalytic element is formed on a mask film.
Means for forming a thin film containing a catalytic element by a gas phase method such as a sputtering method or an evaporation method may be employed.

The amorphous silicon film is preferably subjected to a heat treatment at 400 to 550 ° C. for about one hour to crystallize after sufficient desorption of hydrogen although it depends on the hydrogen content. . In this case, the hydrogen content is preferably set to 5 atom% or less.

The crystallization step is first performed at 400 to 500 ° C. for 1 hour.
After performing a heat treatment process for about an hour to desorb hydrogen from the film, the heat treatment is performed at 500 to 650 ° C. (preferably 550 to 600 ° C.).
C.) for 6 to 16 hours (preferably 8 to 14 hours).

In this embodiment, nickel is used as a catalyst element, and a heat treatment is performed at 570 ° C. for 14 hours. as a result,
From the openings 404a and 404b as starting points, crystallization proceeds in a direction substantially parallel to the substrate (the direction indicated by the arrow), and a semiconductor film having a crystal structure in which macroscopic crystal growth directions are aligned (in this embodiment, a crystalline film). Silicon films 405a to 405d are formed. (FIG. 4 (B))

Next, a gettering step of removing nickel used in the crystallization step from the crystalline silicon film is performed.
In this embodiment, a step of adding an element belonging to Group 15 (phosphorus in this embodiment) is performed by using the mask film 403 formed earlier as a mask as it is, and a 1 × 10 5 ¹⁹ to 1 × 10 ²⁰ at
Phosphorus-added regions (hereinafter referred to as gettering regions) 406a and 406b containing phosphorus at a concentration of oms / cm ³ are formed.
(FIG. 4 (C))

Next, at 450 to 650 ° C. in a nitrogen atmosphere.
(Preferably 500 to 550 ° C.) and a heat treatment step for 4 to 24 hours (preferably 6 to 12 hours) are performed. By this heat treatment step, nickel in the crystalline silicon film moves in the direction of the arrow and is captured in the gettering regions 406a and 406b by the gettering action of phosphorus. That is, since nickel is removed from the crystalline silicon film, the concentration of nickel contained in the crystalline silicon films 407a to 407d after gettering is 1 × 10 ¹⁷ atms / cm ³ or less, preferably 1 × 10 ¹⁷ atms / cm ³ or less.
It can be reduced to × 10 ¹⁶ atms / cm ³ .

Next, the mask film 403 is removed, and a protective film 408 is formed on the crystalline silicon films 407a to 407d for the later addition of impurities. The protective film 408 is 100 to 2
It is preferable to use a silicon nitride oxide film or a silicon oxide film with a thickness of 00 nm (preferably 130 to 170 nm). The protective film 408 has a meaning to prevent the crystalline silicon film from being directly exposed to plasma at the time of adding an impurity and to enable fine concentration control.

Then, a resist mask 409 is formed thereon, and an impurity element imparting p-type (hereinafter, referred to as a p-type impurity element) is added via a protective film 408. As the p-type impurity element, an element belonging to Group 13 typically, typically, boron or gallium can be used.
This step (called a channel doping step) is a step for controlling the threshold voltage of the TFT. Here, boron is added by an ion doping method in which diborane (B ₂ H ₆ ) is plasma-excited without mass separation. Of course, an ion implantation method for performing mass separation may be used.

By this step, 1 × 10 ¹⁵ to 1 × 10 ¹⁸ at
oms / cm ³ (typically 5 × 10 ^{16 to} 5 × 10 ¹⁷ atoms / c
Impurity regions 410a and 410b containing a p-type impurity element (boron in this embodiment) at a concentration of m ³ ) are formed. Note that in this specification, an impurity region containing a p-type impurity element within the above concentration range (a region not containing phosphorus) is defined as a p-type impurity region (b). (FIG. 4 (D))

Next, the resist mask 409 is removed, and the crystalline silicon film is patterned to form island-shaped semiconductor layers (hereinafter, referred to as active layers) 411 to 414. In addition,
The active layers 411 to 414 are formed of a crystalline silicon film having very good crystallinity by selectively adding nickel and crystallizing. Specifically, it has a crystal structure in which rod-shaped or columnar crystals are arranged with a specific direction. Further, after crystallization, nickel is removed or reduced by the gettering action of phosphorus.
The concentration of the catalyst element remaining in 414 is 1 × 10 ¹⁷ atms
/ cm ³ or less, preferably 1 × 10 ¹⁶ atms / cm ³ . (FIG. 4E)

The active layer 411 of the p-channel TFT
Is a region not containing an impurity element intentionally added, and the active layers 412 to 414 of the n-channel TFT are p-type impurity regions (b). In this specification, the active layers 411 to 414 in this state are all defined as being intrinsic or substantially intrinsic. That is, a region to which an impurity element is intentionally added to such an extent that the operation of the TFT is not hindered may be considered as a substantially intrinsic region.

Next, an insulating film containing silicon having a thickness of 10 to 100 nm is formed by a plasma CVD method or a sputtering method. In this embodiment, a 30-nm-thick silicon nitride oxide film is formed. As the insulating film containing silicon, another insulating film containing silicon may be used as a single layer or a stacked layer.

Next, at 800-1150 ° C. (preferably 9 ° C.)
A heat treatment step at a temperature of (00 to 1000 ° C.) for 15 minutes to 8 hours (preferably 30 minutes to 2 hours) is performed in an oxidizing atmosphere (thermal oxidation step). In this embodiment, a heat treatment step is performed at 950 ° C. for 80 minutes in an atmosphere in which 3% by volume of hydrogen chloride is added in an oxygen atmosphere. Note that boron added in the step of FIG. 4D is activated during this thermal oxidation step. (FIG. 5
(A))

The oxidizing atmosphere may be a dry oxygen atmosphere or a wet oxygen atmosphere, but a dry oxygen atmosphere is suitable for reducing crystal defects in the semiconductor layer.
Further, in this embodiment, an atmosphere in which a halogen element is included in an oxygen atmosphere is used, but the atmosphere may be performed in a 100% oxygen atmosphere. Moreover, you may perform by a high pressure oxidation method.

During this thermal oxidation step, an oxidation reaction also proceeds at the interface between the insulating film containing silicon and the active layers 411 to 414 thereunder. In the present invention, in consideration of this, the thickness of the gate insulating film 415 finally formed is 50 to 200 n.
m (preferably 100 to 150 nm). In the thermal oxidation step of this embodiment, 25 nm of the active layer having a thickness of 60 nm is oxidized, and the thickness of the active layers 411 to 414 becomes 35 nm. Further, since a 50-nm-thick thermal oxide film is added to the 30-nm-thick silicon-containing insulating film, the final gate insulating film 415 has a thickness of 80 nm.

Next, resist masks 416 to 41 are newly added.
9 is formed. Then, an n-type impurity element (hereinafter, referred to as an n-type impurity element) is added to form n-type impurity regions 420 to 422. Note that as the n-type impurity element, an element belonging to Group XV, typically, phosphorus or arsenic can be used. (FIG. 5
(B))

The impurity regions 420 to 422 will be
N-channel type TF of MOS circuit and sampling circuit
T is an impurity region for functioning as an LDD region. The impurity region formed here has n
The type impurity element is contained at a concentration of 2 × 10 ^{16 to} 5 × 10 ¹⁹ atoms / cm ³ (typically, 5 × 10 ^{17 to} 5 × 10 ¹⁸ atoms / cm ³ ). In this specification, an impurity region containing an n-type impurity element in the above concentration range is defined as an n-type impurity region (b).

Here, phosphorus is added at a concentration of 1 × 10 ¹⁸ atoms / cm ³ by an ion doping method in which phosphine (PH ₃ ) is plasma-excited without mass separation. Of course, an ion implantation method for performing mass separation may be used. In this step, phosphorus is added to the crystalline silicon film via the gate film 415.

Next, at 600 to 1000 ° C. (preferably 7 ° C.)
Heat treatment is performed in an inert atmosphere (at 00 to 800 ° C.) to activate the phosphorus added in the step of FIG. In this embodiment, the heat treatment at 800 ° C. for 1 hour is performed in a nitrogen atmosphere.
(FIG. 5 (C))

At this time, it is possible to repair the active layer damaged at the time of adding phosphorus and the interface between the active layer and the gate insulating film. In this activation step, furnace annealing using an electric heating furnace is preferable, but optical annealing such as lamp annealing or laser annealing may be used together.

By this step, n-type impurity region (b) 42
The boundary portion between 0 and 422, that is, the junction with the intrinsic or substantially intrinsic region (including the p-type impurity region (b)) existing around the n-type impurity region (b) becomes clear. . This means that when the TFT is completed later, LDD
This means that the region and the channel forming region can form a very good junction.

Next, a conductive film to be a gate wiring is formed. Note that the gate wiring may be formed using a single-layer conductive film, but is preferably a stacked film such as two layers or three layers as necessary. In this embodiment, a stacked film including the first conductive film 423 and the second conductive film 424 is formed. (FIG. 5 (D))

Here, the first conductive film 423 and the second conductive film 42
4 include tantalum (Ta), titanium (Ti), molybdenum (Mo), tungsten (W), chromium (C
r), an element selected from silicon (Si), or a conductive film containing the above element as a main component (typically, a tantalum nitride film, a tungsten nitride film, a titanium nitride film), or an alloy film combining the above elements ( Typically, a Mo-W alloy film, a Mo-Ta alloy film, a tungsten silicide film, etc.)
Can be used.

The first conductive film 423 has a thickness of 10 to 50 nm.
(Preferably 20 to 30 nm), and the second conductive film 424
Is 200 to 400 nm (preferably 250 to 350 n
m). In this embodiment, a 50 nm thick tungsten nitride (WN) film is used as the first conductive film 423, and a 350 nm thick tungsten film is used as the second conductive film 424. Although not shown, it is effective to form a silicon film under the first conductive film 423 with a thickness of about 2 to 20 nm. This can improve the adhesion of the conductive film formed thereon and prevent oxidation.

It is also effective to use a tantalum nitride film as the first conductive film 423 and a tantalum film as the second conductive film.

Next, the first conductive film 423 and the second conductive film 42
4 are collectively etched to form gate wirings 425 to 428 having a thickness of 400 nm. At this time, gate wirings 426 and 427 formed in the drive circuit are n-type impurity regions (b).
The gate insulating film 415 is formed so as to overlap with part of 420 to 422. This overlapping portion will later become a Lov region. Although the gate wirings 428a and 428b appear to be two in cross section, they are actually formed from one continuous pattern. (FIG. 5E)

Next, a resist mask 429 is formed, and p
The impurity regions 430 and 431 containing boron at a high concentration are formed by adding a type impurity element (boron in this embodiment).
In this embodiment, 3 × 10 ^{20 to} 3 × 10 ²¹ atoms / cm ³ (typically, 5 × 10 ^{21 to} 3 × 10 ²¹ atoms / cm ³ ) by an ion doping method (of course, an ion implantation method) using diborane (B ₂ H ₆ ).
Boron is added at a concentration of (× 10 ²⁰ to 1 × 10 ²¹ atoms / cm ³ ). In this specification, an impurity region containing a p-type impurity element in the above concentration range is defined as a p-type impurity region (a). (FIG. 6 (A))

Next, the resist mask 429 is removed, and the
To cover the area that will become the gate wiring and p-channel TFT.
The resist masks 432 to 434 are formed. And n
Type impurity element (phosphorus in this example)
The impurity regions 435 to 441 containing phosphorus are formed. here
But phosphine (PH_Three) -Based ion doping method
(Of course, ion implantation may be used)
The concentration of phosphorus in this region is 1 × 10²⁰~ 1 × 10^{twenty two}at
oms / cm^Three(Typically 2 × 10²⁰~ 5 × 10^{Two 1}atoms / c
m^Three). (FIG. 6 (B))

In this specification, an impurity region containing an n-type impurity element in the above concentration range is defined as an n-type impurity region (a). The region where the impurity regions 435 to 441 are formed contains phosphorus or boron already added in the previous step, but phosphorus is added at a sufficiently high concentration. You do not need to consider the effects of phosphorus or boron. Therefore, in this specification, the impurity regions 435 to 441 may be referred to as n-type impurity regions (a).

Next, the resist masks 432 to 434 are removed, and a cap film 442 made of an insulating film containing silicon is formed. The film thickness is 25-100 nm (preferably 30-50
nm). In this embodiment, a silicon nitride film having a thickness of 25 nm is used. The cap film 442 also functions as a protective film for preventing oxidation of the gate wiring in the subsequent activation step. However, if the cap film 442 is formed too thick, the stress is increased and a problem such as film peeling occurs. Is preferred.

Next, an n-type impurity element (phosphorus in this embodiment) is added in a self-aligned manner using the gate wirings 425 to 428 as a mask. The impurity region 443 thus formed
446 to １ ／ of the n-type impurity region (b).
10 (typically 1/3 to 1/4) (however, 5% higher than the boron concentration added in the channel doping step described above).
〜１０10-fold higher concentration, typically 1 × 10 ¹⁶ -5 × 10 ¹⁸
atoms / cm ³ , typically 3 × 10 ^{17 to} 3 × 10 ¹⁸ atoms / c
Adjust so that phosphorus is added in m ³ ). Note that, in this specification, an impurity region containing an n-type impurity element (excluding the p-type impurity region (a)) in the above concentration range is defined as an n-type impurity region (c). (FIG. 6 (C))

In this step, an insulating film having a thickness of 105 nm (a laminated film of the cap film 442 and the gate insulating film 415).
Phosphorus is added through the gate wiring 43.
Cap films formed on the side walls of 4a and 434b also function as masks. That is, an offset region having a length corresponding to the thickness of the cap film 442 is formed. Note that the offset region refers to a high-resistance region which is formed in contact with the channel formation region and is formed of a semiconductor film having the same composition as the channel formation region, but does not form an inversion layer (channel region) because no gate voltage is applied. . In order to reduce the off-state current value, it is important to minimize the overlap between the LDD region and the gate wiring. In that sense, providing an offset region is effective.

When the channel forming region also contains the p-type impurity element at a concentration of 1 × 10 ¹⁵ to 1 × 10 ¹⁸ atoms / cm ³ as in this embodiment, the same concentration is naturally applied to the offset region. Contains a p-type impurity element.

The length of the offset region depends on the thickness of the cap film actually formed on the side wall of the gate wiring and the sneak phenomenon when the impurity element is added (the phenomenon in which the impurity is added so as to enter under the mask). ), But L
From the viewpoint of suppressing the overlap between the DD region and the gate wiring, it is very effective to form a cap film in advance when forming the n-type impurity region (c) as in the present invention.

In this step, 1 × 10 ^{16 to} 5 × 1 is applied to all the impurity regions except for the portion hidden by the gate wiring.
Although phosphorus is added at a concentration of 0 ¹⁸ atoms / cm ³ , the function is extremely low and does not affect the function of each impurity region. The n-type impurity regions (b) 443 to 446 are already 1 × 10 ¹⁵ to 1 × 10 ¹⁸ atoms in the channel doping process.
Although boron is added at a concentration of s / cm ³ , phosphorus is added at a concentration of 5 to 10 times that of boron contained in the p-type impurity region (b) in this step.
It may be considered that the function of the type impurity region (b) is not affected.

However, strictly speaking, the n-type impurity region (b) 44
7 and 448, the phosphorus concentration of the portion overlapping the gate wiring remains at 2 × 10 ^{16 to} 5 × 10 ¹⁹ atoms / cm ³ , whereas the portion not overlapping the gate wiring is 1 × 10 ¹⁶
Phosphorus at a concentration of ~ 5 × 10 ¹⁸ atoms / cm ³ is added,
It will contain phosphorus at a slightly higher concentration.

Next, a first interlayer insulating film 449 is formed.
The first interlayer insulating film 449 may be formed using an insulating film containing silicon, specifically, a silicon nitride film, a silicon oxide film, a silicon nitride oxide film, or a stacked film including a combination thereof. Further, the film thickness may be 100 to 400 nm. In the present embodiment, SiH ₄ , N
_A silicon nitride oxide film having a thickness of 200 nm (nitrogen concentration: 25 to 50 atomic%) is used with ₂ O and NH ₃ as source gases.

Thereafter, a heat treatment step was performed to activate the n-type or p-type impurity element added at each concentration. This step can be performed by furnace annealing, laser annealing, lamp annealing, or a combination thereof. When performing the furnace annealing method,
The heat treatment may be performed at 500 to 800C, preferably 550 to 600C in an inert atmosphere. In this embodiment, 600
A heat treatment is performed at 4 ° C. for 4 hours to activate the impurity element.
(FIG. 6 (D))

In this embodiment, the silicon nitride film 442
The gate wiring is covered in a state where the silicon nitride oxide film 449 and the silicon nitride oxide film 449 are stacked, and an activation step is performed in that state. In this embodiment, tungsten is used as a wiring material.
It is known that a tungsten film is very susceptible to oxidation. That is, even if it is covered with the protective film and oxidized, if the pinhole exists in the protective film, it is immediately oxidized. However,
In this embodiment, a very effective silicon nitride film is used as an antioxidant film, and a silicon nitride oxide film is laminated on the silicon nitride film. The activation step can be performed at a very high temperature.

Next, after the activation step, heat treatment is performed in an atmosphere containing 3 to 100% hydrogen at 300 to 450 ° C. for 1 to 4 hours to hydrogenate the active layer. In this step, dangling bonds in the semiconductor layer are terminated by thermally excited hydrogen. Plasma hydrogenation (using hydrogen excited by plasma) as another means of hydrogenation
May be performed.

After completing the activation step, the first interlayer insulating film 4
A second interlayer insulating film 450 having a thickness of 500 nm to 1.5 μm is formed on the insulating film 49. In this embodiment, the second interlayer insulating film 450 is used.
800nm thick silicon oxide film as plasma CVD
It is formed by a method. Thus, a 1 μm-thick interlayer insulating film composed of a stacked film of the first interlayer insulating film (silicon oxynitride film) 449 and the second interlayer insulating film (silicon oxide film) 450 is formed.

If heat resistance is allowed in a later step, an organic resin film such as polyimide, acrylic, polyamide, polyimide amide, or BCB (benzocyclobutene) can be used as the second interlayer insulating film 450. .

Thereafter, contact holes reaching the source region or the drain region of each TFT are formed, and the source wirings 451 to 454 and the drain wiring 455 are formed.
To 457 are formed. Note that the drain wiring 455 is shared between the p-channel TFT and the n-channel TFT in order to form a CMOS circuit. Although not shown, in the present embodiment, this wiring is
nm, Ti-containing aluminum film 500 nm, Ti film 1
A three-layer laminated film having a thickness of 00 nm formed continuously by a sputtering method.

Next, as a passivation film 458,
A silicon nitride film, a silicon oxide film, or a silicon nitride oxide film having a thickness of 50 to 500 nm (typically, 200 to 300 nm);
(nm). (FIG. 7A) At this time, in this embodiment, a plasma treatment is performed using a gas containing hydrogen such as H ₂ and NH ₃ before the film is formed, and a heat treatment is performed after the film is formed. Hydrogen excited by this pretreatment is supplied into the first and second interlayer insulating films. By performing the heat treatment in this state, the film quality of the passivation film 458 is improved, and the hydrogen added to the first and second interlayer insulating films diffuses to the lower layer side, so that the active layer is effectively hydrogenated. be able to.

After the passivation film 458 is formed, a hydrogenation step may be further performed. For example, 3
300 to 450 ° C. in an atmosphere containing １００100% hydrogen
The heat treatment is preferably performed for 1 to 12 hours, or the same effect can be obtained by using a plasma hydrogenation method. Note that an opening (not shown) may be formed in the passivation film 458 at a position where a contact hole for connecting the pixel electrode and the drain wiring is formed after the hydrogenation step.

Thereafter, a third interlayer insulating film 459 made of an organic resin is formed to a thickness of about 1 μm. As the organic resin, polyimide, acrylic, polyamide, polyimide amide, BCB (benzocyclobutene), or the like can be used. The advantages of using an organic resin film include that the film formation method is simple, the parasitic capacitance can be reduced because the relative dielectric constant is low, and the flatness is excellent. Note that an organic resin film or an organic SiO compound other than those described above can also be used. Here, it is formed by baking at 300 ° C. using a type of polyimide which is thermally polymerized after being applied to the substrate.

Next, a common electrode 460 is formed on the third interlayer insulating film 459 in a region to be a pixel portion. In addition,
The common electrode 460 may also have a function of a shielding film for shielding light and electromagnetic waves. The common electrode 460 is made of an anodizable material, for example, aluminum (Al), titanium (Ti),
A film made of an element selected from tantalum (Ta) or a film containing any of the elements as a main component is formed to a thickness of 100 to 300 nm. In this embodiment, an aluminum film containing 1 wt% of titanium is formed to a thickness of 125 nm.

If an insulating film such as a silicon oxide film is formed to a thickness of 5 to 50 nm on the third interlayer insulating film 459, the adhesion of the common electrode formed thereon can be improved.
Further, when plasma treatment using CF ₄ gas is performed on the surface of the third interlayer insulating film 459 formed of an organic resin, the adhesion of a common electrode formed on the film can be improved by surface modification.

Further, using the aluminum film containing titanium, not only a common electrode but also other connection wirings can be formed. For example, it is possible to form a connection wiring that connects circuits in a drive circuit. However, in this case, it is necessary to form a contact hole in the third interlayer insulating film before forming a material for forming the common electrode or the connection wiring.

Next, an oxide 461 having a thickness of 20 to 100 nm (preferably 30 to 50 nm) is formed on the surface of the common electrode 460 by anodization or plasma oxidation (in this embodiment, anodization). At this time, the common electrode is patterned in such a manner that all the common electrodes are connected for anodizing. The common electrodes are arranged with a certain margin so that the ends of the common electrodes do not short-circuit with each other.
In this embodiment, since a film containing aluminum as a main component is used as the common electrode 460, an aluminum oxide film (alumina film) is formed as the anodic oxide 461.

In this anodizing treatment, an ethylene glycol tartrate solution having a sufficiently low alkali ion concentration is first prepared. This is a solution obtained by mixing a 15% aqueous solution of ammonium tartrate and ethylene glycol at a ratio of 2: 8, and ammonia water is added thereto to adjust the pH to 7 ± 0.5. Then, a platinum electrode serving as a cathode is provided in the solution, and the substrate on which the common electrode 460 is formed is immersed in the solution.
A to several tens mA).

The voltage between the cathode and the anode in the solution changes with time according to the growth of the anodic oxide. However, the voltage is increased at a constant current of 100 V / min at a step-up rate to reach the ultimate voltage of 45 V. By the way, the anodizing treatment is terminated. In this manner, an anodic oxide 461 having a thickness of about 50 nm can be formed on the surface of the common electrode 460 on the organic resin film. The anodic oxide film 461 formed by the anodic oxidation method has less rounding at the electrode end portions and is less likely to be peeled off than the anodic oxide film formed by the conventional anodic oxidation method.
As a result, the thickness of the common electrode 460 becomes 90 nm. It is to be noted that the numerical values relating to the anodic oxidation method shown here are merely examples, and the optimum values can naturally vary depending on the size of the element to be manufactured.

When the common electrode 460 also has the function of a shielding film, the starting film thickness of the aluminum film is set under three conditions (65 n
(m, 95 nm, 125 nm) and anodizing conditions were all the same, and an anodized film having a thickness of 50 nm was formed. As a result, the thickness of the non-anodized electrode is 30 nm and 60 nm.
nm and 90 nm.

FIG. 17 shows the result of measurement using a Hitachi spectrophotometer U-4000. Electrode thickness at 550 nm:
It can be read from FIG. 17 that the absorbance at 30 nm is 2.6, the absorbance at an electrode film thickness: 60 nm is 4, and the absorbance at an electrode film thickness: 90 nm is 4.6. The absorbance (at 550 nm) required when the electrode is used as a shielding film may be 3 or more. Therefore, if it is 60 nm or more, it functions as a shielding film without any problem. In consideration of light leakage due to steps, it is preferable that the shielding film be thin.

Thereafter, the common electrodes connected at the time of anodic oxidation were cut off to obtain the shape of the common electrode shown in FIG. Next, a contact hole reaching the drain wiring 457 is formed in the third interlayer insulating film 459 and the passivation film 458, and a pixel electrode 462 is formed. Pixel electrode 4
62 may be formed by patterning a conductive metal film having a thickness of 100 to 300 nm. In this embodiment, an aluminum film is used.

At this time, the region where the pixel electrode 462 and the common electrode 460 overlap with each other via the anodic oxide 461 is
A storage capacity (capacity striation) 464 is formed. In this case, it is desirable that the common electrode 460 be set to a floating state (an electrically isolated state) or a fixed potential, preferably a common potential (an intermediate potential of an image signal transmitted as data).

Thus, an element substrate having a driving circuit and a pixel portion on the same substrate was completed. Note that in FIG. 7B, a p-channel TFT 601 and n-channel TFTs 602 and 603 are formed in a driver circuit, and a pixel TFT 604 including an n-channel TFT is formed in a pixel portion.

In the p-channel TFT 601 of the driving circuit, a channel formation region 501, a source region 502, and a drain region 503 are each formed of a p-type impurity region (a). However, strictly speaking, the source 502 region and the drain region 503 contain phosphorus at a concentration of 1 × 10 ^{16 to} 5 × 10 ¹⁸ atoms / cm ³ .

In the n-channel type TFT 602, the channel formation region 504, the source region 505, the drain region 506, and the region between the channel formation region and the drain region which overlaps with the gate wiring via the gate insulating film ( In the present specification, such a region is referred to as a Lov region, where ov is assigned to overlap.) 507 is formed. At this time, the Lov area 507 is 2 × 10 ^{16 to} 5 × 10 ¹⁹
It is formed so as to contain phosphorus at a concentration of atoms / cm ³ and to completely overlap with the gate wiring.

In the n-channel TFT 603, the L-type TFT is formed so as to sandwich the channel formation region 508, the source region 509, the drain region 510, and the channel formation region.
DD regions 511 and 512 are formed. That is, an LDD region is formed between the source region and the channel formation region and between the drain region and the channel formation region.

In this structure, the LDD regions 511,
12 are arranged so as to overlap with the gate wiring, a region (Lov region) that overlaps with the gate wiring via the gate insulating film and a region that does not overlap with the gate wiring (such a region is referred to as Loff region, where off is
Affixed in the meaning of offset. ) Has been realized.

The LDD region 511 further includes a Lov region and a Lof region.
f region can be distinguished. In the Lov area, 2 × 1
Phosphorus is contained at a concentration of 0 ^{16 to} 5 × 10 ¹⁹ atoms / cm ³ , but the Loff region is 1 to 2 times as large (typically 1.2 to
1.5 times).

The pixel TFT 604 includes channel forming regions 513 and 514, a source region 515, a drain region 516, Loff regions 517 to 520, and an Loff region 51.
N-type impurity regions (a) 521 in contact with 8, 519 are formed. At this time, the source region 515 and the drain region 51
6 are each formed of an n-type impurity region (a),
Regions 517 to 520 are formed of n-type impurity regions (c).

In the present embodiment, the structure of the TFT forming each circuit can be optimized according to the circuit specifications required by the pixel portion and the driving circuit, and the operation performance and reliability of the semiconductor device can be improved. Specifically, an n-channel TFT
Changes the arrangement of the LDD regions according to the circuit specifications, and Lov
By properly using the region or the Loff region, a TFT structure emphasizing high-speed operation or hot carrier measures and a TFT structure emphasizing low off-current operation can be realized on the same substrate.

For example, in the case of an active matrix type liquid crystal display device, the n-channel type TFT 602 is suitable for a driving circuit such as a shift register circuit, a frequency dividing circuit, a signal dividing circuit, a level shifter circuit, and a buffer circuit which emphasizes high-speed operation. That is, the Lov region is formed only between the channel formation region and the drain region, so that the resistance component is reduced as much as possible and the hot carrier measures are emphasized. This is because, in the case of the above-described circuit group, the functions of the source region and the drain region do not change and the direction in which carriers (electrons) move is constant.

However, the Lov region can be formed with the channel forming region interposed therebetween, if necessary. That is, it can be formed between the source region and the channel formation region and between the drain region and the channel formation region.

Further, the n-channel type TFT 603 is suitable for a sampling circuit (sample-and-hold circuit) that emphasizes both hot carrier measures and low off-current operation. That is, the hot carrier is prevented by forming the Lov region, and a low off-current operation is realized by forming the Loff region. In the sampling circuit, the functions of the source region and the drain region are reversed, and the carrier moving direction is 18
Since the angle is changed by 0 °, the structure must be line-symmetric with respect to the gate wiring. In some cases, L
There may be only the ov region.

Further, the n-channel TFT 604 is suitable for a pixel portion and a sampling circuit (a sample-and-hold circuit) which place importance on low off-current operation. That is, a low off-current operation is realized by arranging the Loff region and the offset region without arranging the Lov region, which can be a factor of increasing the off-current value. Further, by using an LDD region having a lower concentration than the LDD region of the drive circuit as the Loff region, a measure is taken to thoroughly reduce the off-current value even if the on-current value is slightly reduced. Further, an n-type impurity region (a) 5
It has been confirmed that 21 is very effective in reducing the off-current value.

Further, if the length (width) of the Lov region 507 of the n-channel TFT 602 is 0.3 to 3.0 μm, typically 0.5 to 1.5 μm for a channel length of 3 to 7 μm. good. The length (width) of the Lov regions 511a and 512a of the n-channel TFT 603 is 0.3 to 3.0 μm.
m, typically 0.5 to 1.5 μm, Loff region 511
b, 512b may have a length (width) of 1.0 to 3.5 μm, typically 1.5 to 2.0 μm. The pixel TF
The length (width) of Loff regions 517 to 520 provided in T604 is 0.5 to 3.5 μm, typically 2.0 to 2.0 μm.
The thickness may be set to 5 μm.

Further, in this embodiment, an alumina film having a relative dielectric constant as high as 7 to 9 is used as the dielectric of the storage capacitor.
The area occupied by the storage capacitor required to form the required capacitance can be reduced. Further, by using the common electrode formed on the pixel TFT as one electrode of the storage capacitor as in this embodiment, the aperture ratio of the pixel portion of the liquid crystal display device can be improved.

Here, a process of manufacturing an active matrix type liquid crystal display device from an active matrix substrate will be described. As shown in FIG. 8, an alignment film 801 is formed on the substrate in the state shown in FIG. In this embodiment, a polyimide film is used as an alignment film. Further, an alignment film 803 is formed over the counter substrate 802. Note that a color filter and a shielding film may be formed on the counter substrate as needed.

Next, after forming the alignment film, a rubbing treatment is performed to adjust the liquid crystal molecules so as to be aligned with a certain pretilt angle. Then, the pixel portion, the substrate on which the driver circuit is formed, and the counter substrate are attached to each other via a spacer 805 or the like by a known cell assembling process. However, in order to prevent a short circuit from occurring when pressure is applied between the substrates, it is preferable that the spacer 805 be arranged so as to avoid the region where the storage capacitor is formed. In addition, in order to keep the distance between the substrates uniform, the liquid crystal layer may be surrounded by a sealant 806, and a spacer may be formed in a region where the sealant 806 is formed. Further, in the driver circuit, the spacer 805 may be provided in a region where no element of the driver circuit exists, and the spacer may be formed in a region between the pixel portion provided with the pixel electrode and the driver circuit. In addition, when the spacer 805 is formed over the contact portion of the pixel electrode 462 which becomes a concave portion, occurrence of disclination can be reduced.

Thereafter, a liquid crystal 804 is injected between the two substrates, and is completely sealed with a sealant 806. Liquid crystal 80
4 is a well-known n-type liquid crystal or p-type liquid crystal used in the IPS system.
A type liquid crystal may be used. Thus, the liquid crystal display device shown in FIG. 8 is completed.

Next, the structure of the liquid crystal display device will be described with reference to the perspective view of FIG. A pixel portion 901 and a scanning (gate) line driving circuit 902 formed on a quartz substrate 401
And a signal (source) line driving circuit 903. The pixel TFT in the pixel portion is an n-channel TFT, and a peripheral driving circuit is configured based on a CMOS circuit. The scanning line driver circuit and the signal line driver circuit are connected to the pixel portion 901 by a gate wiring and a source wiring, respectively. Also, a connection wiring 90 from the external input / output terminal 905 to which the FPC 904 is connected to the input / output terminal of the driving circuit.
6, 907 are provided.

Next, FIG. 10 shows an example of a circuit configuration of the liquid crystal display device shown in FIG. The liquid crystal display device of this embodiment is
Signal line driving circuit 1001, scanning line driving circuit (A) 100
7, a scan line driver circuit (B) 1011, a precharge circuit 1012, and a pixel portion 1006. Note that in this specification, a driving circuit is a signal line driving circuit 100
1, a scanning line driving circuit (A) 1007 and a scanning line driving circuit (B) 1011 are included.

The signal line driving circuit 1001 includes a shift register circuit 1002, a level shifter circuit 1003, a buffer circuit 1004, and a sampling circuit 1005. The scan line driver circuit (A) 1007 includes a shift register circuit 1008, a level shifter circuit 1009, and a buffer circuit 1010. Scan line drive circuit (B)
1011 has a similar configuration.

The structure of this embodiment can be easily realized by fabricating a TFT according to the steps shown in FIGS. In this embodiment, only the configuration of the pixel portion and the driving circuit is shown. However, according to the manufacturing process of this embodiment, other components such as a signal dividing circuit, a frequency dividing circuit, a D / A converter circuit, an operational amplifier circuit, and γ A correction circuit and a signal processing circuit (also referred to as a logic circuit) such as a microprocessor circuit can be formed over the same substrate.

As described above, the present invention provides a semiconductor device including at least a pixel portion and a driving circuit for driving the pixel portion on the same substrate, for example, a signal processing circuit, a driving circuit, a pixel portion, and a holding circuit on the same substrate. And a semiconductor device having a capacitor.

When the steps up to FIG. 5B of this embodiment are performed, a crystalline silicon film having a unique crystal structure having continuity in the crystal lattice is formed. Hereinafter, the features of the crystal structure experimentally examined by the present applicant will be briefly described. In addition,
This feature coincides with the feature of the semiconductor layer forming the active layer of the TFT completed by this embodiment.

The crystalline silicon film has a crystal structure in which a plurality of needle-like or rod-like crystals (hereinafter, abbreviated as rod-like crystals) are gathered and lined up microscopically. This is T
It can be easily confirmed by observation by EM (transmission electron microscopy).

Further, electron diffraction and X-ray (X-ray)
When diffraction is used, it can be confirmed that the surface of the crystalline silicon film (portion where a channel is formed) has a {110} plane as a main orientation plane, although the crystal axis has some deviation. At this time, if analysis is performed by electron beam diffraction,
It can be confirmed that diffraction spots corresponding to the 0 ° plane clearly appear. It can also be confirmed that each spot has a distribution on a concentric circle.

The crystal grain boundaries formed by the contact of the individual rod-shaped crystals are formed by HR-TEM (high-resolution transmission electron microscopy).
By observing the results, it can be confirmed that the crystal lattice has continuity at the crystal grain boundaries. This can be easily confirmed from the fact that the observed lattice fringes are continuously connected at the crystal grain boundaries.

Note that the continuity of the crystal lattice at the crystal grain boundaries is caused by the fact that the crystal grain boundaries are grain boundaries called “planar grain boundaries”. The definition of the planar grain boundary in this specification is `` Characterization of High-Efficiency Cast-Si
Solar Cell Wafers by MBICMeasurement; Ryuichi Shi
mokawa and Yutaka Hayashi, Japanese Journal of Appl
ied Physics vol.27, No.5, pp.751-758, 1988 ".

According to the above paper, the planar grain boundaries include twin grain boundaries, special stacking faults, special twist grain boundaries, and the like. This planar grain boundary is characterized by being electrically inactive. In other words, since it is a crystal grain boundary but does not function as a trap that hinders the movement of carriers, it can be considered that it does not substantially exist.

In particular, the crystal axis (the axis perpendicular to the crystal plane) is <11
In the case of the <0> axis, the {211} twin grain boundaries are also called corresponding grain boundaries of {3}. The Σ value is a parameter serving as a guideline indicating the degree of consistency of the corresponding grain boundaries, and it is known that the smaller the Σ value, the better the grain boundaries of consistency.

When the crystalline silicon film of this embodiment is actually observed in detail using a TEM, almost all of the crystal grain boundaries (90%
It can be seen that (typically 95% or more) is the corresponding grain boundary of {3, typically {211} twin grain boundary.

In a grain boundary formed between two crystal grains, when the plane orientation of both crystals is {110},
Assuming that the angle formed by the lattice fringes corresponding to the {111} plane is θ,
It is known that when θ = 70.5 °, the corresponding grain boundary becomes Σ3. In the crystalline silicon film of this embodiment, the lattice fringes of adjacent crystal grains at the crystal grain boundary are continuous at exactly an angle of about 70.5 °, which means that this crystal grain boundary is a corresponding grain boundary of Σ3. I can say.

When θ = 38.9 °, the corresponding grain boundary becomes の 9, but there is another such corresponding grain boundary. In any case, it is still inert.

Such corresponding grain boundaries are formed only between crystal grains having the same plane orientation. That is, the crystalline silicon film of this embodiment can form such a corresponding grain boundary over a wide range only because the plane orientation is substantially {110}.

Such a crystal structure (accurately, a structure of a crystal grain boundary) indicates that two different crystal grains are bonded to each other with extremely high consistency at the crystal grain boundary. That is, the crystal lattice is continuously connected at the crystal grain boundary, and it is very difficult to form a trap level due to a crystal defect or the like. Therefore, it can be considered that the semiconductor thin film having such a crystal structure has substantially no crystal grain boundary.

Further, it was confirmed by TEM observation that defects existing in the crystal grains were almost completely eliminated by a heat treatment step (corresponding to the thermal oxidation step in Example 1) at a high temperature of 800 to 1150 ° C. I have. This is apparent from the fact that the number of defects is significantly reduced before and after this heat treatment step.

The difference in the number of defects was determined by electron spin resonance analysis (El
ectron Spin Resonance (ESR) appears as a difference in spin density. At present, it has been found that the spin density of the crystalline silicon film of this embodiment is at least 5 × 10 ¹⁷ spins / cm ³ or less (preferably 3 × 10 ¹⁷ spins / cm ³ or less). However, since this measured value is close to the detection limit of existing measuring devices, the actual spin density is expected to be lower.

From the above, it can be considered that the crystalline silicon film of this embodiment has extremely few defects in crystal grains and can be regarded as having substantially no crystal grain boundary. It can be considered a silicon film.

[Embodiment 2] In this embodiment, a case where the configuration of the pixel portion is different from that of Embodiment 1 is shown in FIG.
This will be described with reference to FIG. Note that the basic structure is the same as that of the pixel circuit shown in FIG. 1B, and thus only different points will be described. Therefore, the same reference numerals are used for the same parts.

FIG. 11A is a sectional view of a pixel portion of this embodiment, in which a buffer layer 1101 is formed between an interlayer insulating film (organic resin film) and a common electrode. Buffer layer 1
As 101, 10 to 100 nm (preferably 30 to 100 nm)
An insulating film containing silicon with a thickness of 50 nm) is used. However,
Since the film is formed over the organic resin film, degassing from the resin film becomes a problem when exposed to a vacuum, it is preferable to use an insulating film which can be formed by a sputtering method.

In this embodiment, a 50-nm-thick silicon oxide film is used as the buffer layer 1101. By forming this buffer layer, the adhesion between the organic resin film and the common electrode is improved. When the oxide is formed by the anodic oxidation method as in the first embodiment, if the adhesion is poor, there occurs a problem that the anodic oxide is formed so as to enter the interface between the organic resin film and the common electrode. However, with the structure in FIG. 11A, such a problem can be prevented.

The structure of FIG. 11B is an example in which the buffer layer 1102 is formed in a self-alignment manner under the common electrode, although the basic structure is similar to that of FIG. 11A. In this case, the structure of FIG. 11B can be realized by etching the buffer layer in a self-aligned manner using the common electrode as a mask.

The etching step may be performed immediately after forming the common electrode, or may be performed after forming the oxide film. However, in the case where the material of the buffer layer 1102 and the material of the oxide film are etched with the same etchant, it is desirable to perform an etching step before forming the oxide film.

The structure shown in FIG. 11B is advantageous when a contact hole is formed in the third interlayer insulating film. If a silicon oxide film or the like exists on the organic resin film, the silicon oxide film may remain in an eaves shape when the organic resin film is etched. Therefore, FIG.
It is preferable to remove the buffer layer at a position where a contact hole is to be formed in advance as in the structure of FIG.

In the structure of FIG. 11C, after the common electrode and the oxide film are formed, the spacer 110 formed of an insulating film is used.
An example is shown in which 3a to 1103c are formed and then the pixel electrode 104 is formed. Spacers 1103a to 1103c
As a material of the above, an organic resin film is preferable, and particularly, polyimide or acrylic having photosensitivity is preferably used.

With the structure shown in FIG. 11C,
Since the end portion (edge portion) of the common electrode is hidden by the spacer, it is possible to prevent the common electrode and the pixel electrode from being short-circuited at the end portion of the common electrode.

The structure of this embodiment is the same as that of the first embodiment except that the steps from the formation of the third interlayer insulating film to the formation of the pixel electrode are changed in the manufacturing process of the first embodiment. Is good. Therefore, the present invention can be applied to the liquid crystal display device described in the first embodiment.

[Embodiment 3] In this embodiment, a case where the shape of the common electrode in the pixel portion is different from that in Embodiment 1 will be described with reference to FIGS. Note that the basic structure is the same as that of the pixel portion shown in FIG. 1A, and only different points will be described. Therefore, the same reference numerals are used for the same parts.

In this embodiment, in order to set the common electrode to a common potential (an intermediate potential of an image signal transmitted as data), the common electrode 1 having a shape connected to each common electrode is set.
201 is formed. Then, by electrically connecting the common electrode 1201 and a power supply line for supplying a common potential outside the pixel portion, the common electrode 1201 can be held at the common potential. Note that when the common electrode 1201 is used, a dividing step after anodic oxidation can be omitted, so that the step can be simplified.

Further, the common electrode 1301 having the shape as shown in FIG. 13 may be formed so as to completely cover the TFT and block light and electromagnetic waves. Also in this case, the dividing step after anodic oxidation can be omitted, so that the step can be simplified.

The structure of this embodiment can be realized only by partially changing the manufacturing steps (such as the common electrode pattern) of the first embodiment, and other steps may be the same as those of the first embodiment. Therefore, the present invention can be applied to the liquid crystal display device described in the first embodiment. Further, it is possible to freely combine with the configuration shown in the second embodiment.

[Embodiment 4] In this embodiment, the case where the shapes of the pixel electrode and the common electrode in the pixel portion are different from those in Embodiment 1 will be described with reference to FIGS. 14 (A) and 14 (B). I do. Note that the basic structure is the same as that of the pixel portion shown in FIG. 1A, and only different points will be described.
Therefore, the same reference numerals are used for the same parts.

As shown in FIG. 14A, a zigzag pixel electrode 1401 and a zigzag common electrode 141 are formed.
02 was formed. By doing so, two kinds of directions of the electric field applied to the liquid crystal were formed, and the display characteristics could be improved.

Further, as shown in FIG. 14B, the shape of the source line was changed in accordance with the zigzag common electrode 1404 to obtain a source line 1403. By doing so, the aperture ratio could be improved. However, it is preferable to change the shape in consideration of the parasitic capacitance formed between the source line and the common electrode.

The configuration of the present embodiment can be realized by only partially changing the manufacturing steps of the first embodiment, and other steps may be the same as those of the first embodiment. Therefore, the present invention can be applied to the liquid crystal display device described in the first embodiment. Further, it is possible to freely combine with the configuration shown in the second embodiment.

[Embodiment 5] In this embodiment, the case where the shapes of the pixel electrode and the common electrode in the pixel portion are different from those in Embodiment 1 will be described with reference to FIGS. 15 (A) and 15 (B). I do. Note that the basic structure is the same as that of the pixel portion shown in FIG. 1A, and only different points will be described.
Therefore, the same reference numerals are used for the same parts.

As shown in FIG. 15A, a pixel electrode 1501 having a "-" shape and a common electrode 15 having a "-" shape are formed.
02 was formed. By doing so, two kinds of directions of the electric field applied to the liquid crystal were formed, and the display characteristics could be improved.

Further, as shown in FIG.
The shape of the source line was changed according to the common electrode 1504 in the shape of a square, and a source line 1503 was obtained. By doing so, the aperture ratio could be improved. However, it is preferable to change the shape in consideration of the parasitic capacitance formed between the source line and the common electrode.

The structure of this embodiment can be realized by only partially changing the manufacturing process of the first embodiment, and the other steps may be the same as those of the first embodiment. Therefore, the present invention can be applied to the liquid crystal display device described in the first embodiment. Further, it is possible to freely combine with the configuration shown in the second embodiment.

[Embodiment 6] In this embodiment, a case where the shapes of the pixel electrode and the common electrode in the pixel portion are different from those in Embodiment 1 will be described with reference to FIG. Note that the basic structure is the same as that of the pixel portion shown in FIG. 1A, and only different points will be described. Therefore, the same reference numerals are used for the same parts.

A pixel electrode 1601 having a shape as shown in FIG. 16A and a common electrode 1602 were formed. By doing so, three directions of the electric field applied to the liquid crystal were formed, and the display characteristics could be improved.

The shape of the source line was changed according to the shape of the common electrode 1604 as shown in FIG. By doing so, the aperture ratio could be improved. However, it is preferable to change the shape in consideration of the parasitic capacitance formed between the source line and the common electrode.

The structure of this embodiment can be realized only by partially changing the manufacturing process of the first embodiment, and other steps may be the same as those of the first embodiment. Therefore, the present invention can be applied to the liquid crystal display device described in the first embodiment. Further, it is possible to freely combine with the configuration shown in the second embodiment.

[Embodiment 7] In this embodiment, another configuration in the pixel portion will be described.

In the present embodiment, description will be made by focusing only on the differences from the first embodiment.

This embodiment has a configuration in which a color filter colored with three primary colors of RGB is provided between a pixel TFT and a pixel electrode. The color arrangement of R, G, and B may be stripe or mosaic.

First, after forming the passivation film 458 according to the first embodiment, a color filter is formed thereon. The color filter 1601 also has a function of a flattening film. Then, at the same time as patterning the color filter or after forming the color filter,
An ITO contact opening is made in advance. After that, a second interlayer insulating film is formed, and a light shielding layer is formed thereon. In the subsequent steps, a third interlayer insulating film made of an anodic oxide film and an organic resin film is formed by using the same manufacturing method as in the first embodiment. Thereafter, the third interlayer insulating film, the second interlayer insulating film, and the passivation film 458 are etched to form a contact hole, and a pixel electrode is formed using the same material as in the first embodiment.
The storage capacitor includes a shielding layer, an anodic oxide film, and a pixel electrode.

The structure of this embodiment can be freely combined with any of the structures of the first to sixth embodiments.

[Embodiment 8] In this embodiment, a case where the present invention is applied to a bottom gate type TFT will be described. Specifically, FIG. 18 shows a case where the present invention is used for an inverted stagger type TFT. In the case of the inverted stagger type TFT of the present invention, there is no particular difference from the top gate type TFT of Example 1 except that the positional relationship between the gate wiring and the active layer is different. Therefore, in the present embodiment, description will be made while paying attention to a point that is significantly different from the structure shown in FIG. 7B, and the other parts are the same as those in FIG. In the same manner as in Example 1,
A shielding film, its anodic oxide film, and a storage capacitor composed of a pixel electrode are formed. This anodic oxide film is formed by the method described in the embodiment of the present invention.

In FIG. 18, reference numerals 11 and 12 denote a p-channel TFT and an n-channel TFT of a CMOS circuit forming a shift register circuit and the like, respectively, 13 an n-channel TFT forming a sampling circuit and the like, and 14 a pixel portion. This is an n-channel TFT to be formed. These are formed on a substrate provided with a base film.

Further, reference numeral 15 denotes a gate wiring of the p-channel TFT 11, 16 denotes a gate wiring of the n-channel TFT 12, 17 denotes a gate wiring of the n-channel TFT 13, 18
Denotes a gate wiring of the n-channel TFT 14, which can be formed using the same material as the gate wiring described in the first embodiment. Reference numeral 19 denotes a gate insulating film, which can also be made of the same material as in the first embodiment.

An active layer (active layer) of each of the TFTs 11 to 14 is formed thereon. In the active layer of the p-channel TFT 11, a source region 20, a drain region 21, and a channel forming region 22 are formed.

In the active layer of the n-channel type TFT 12, a source region 23, a drain region 24, an LDD region (Lov region 25 in this case), and a channel forming region 26 are formed.

The active layer of the n-channel TFT 13 includes a source region 27, a drain region 28, and an LDD region (in this case, Lov regions 29a, 30a and Loff region 29).
b, 30b), a channel forming region 31 is formed.

In the active layer of the n-channel type TFT 14, a source region 32, a drain region 33, an LDD region (in this case, Loff regions 34 to 37), channel forming regions 38 and 39, and an n-type impurity region 40 are formed. Is done.

The insulating films indicated by 41 to 45 are formed for the purpose of protecting the channel formation region and the purpose of forming the LDD region.

As described above, it is easy to apply the present invention to a bottom gate type TFT typified by an inverted staggered type TFT. Note that in manufacturing the inverted staggered TFT of this embodiment, the manufacturing steps described in the other embodiments described in this specification may be applied to a known inverted staggered TFT manufacturing step.

The structure of this embodiment can be freely combined with any of the structures of Embodiments 1 to 7.

[Embodiment 9] The pixel portion formed by carrying out the present invention can be used for various electro-optical devices (active matrix type liquid crystal displays). That is, the invention of the present application can be applied to all electronic devices in which these electro-optical devices are incorporated in a display unit.

Such electronic devices include a video camera, digital camera, projector (rear or front type), head mounted display (goggle type display), car navigation, car stereo,
Examples include a personal computer and a portable information terminal (a mobile computer, a mobile phone, an electronic book, or the like). Examples of these are shown in FIGS. 19, 20 and 21.

FIG. 19A shows a personal computer, which includes a main body 2001, an image input section 2002, and a display section 20.
03, a keyboard 2004 and the like. Display unit 2 of the present invention
003 can be applied.

FIG. 19B shows a video camera, which includes a main body 2101, a display portion 2102, an audio input portion 2103, an operation switch 2104, a battery 2105, and an image receiving portion 210.
6 and so on. The present invention can be applied to the display portion 2102.

FIG. 19C shows a mobile computer (mobile computer), which includes a main body 2201, a camera section 2202, an image receiving section 2203, operation switches 2204, a display section 2205, and the like. The present invention can be applied to the display portion 2205.

FIG. 19D shows a goggle type display, which includes a main body 2301, a display section 2302, and an arm section 230.
3 and so on. The present invention can be applied to the display portion 2302.

FIG. 19E shows a player that uses a recording medium (hereinafter, referred to as a recording medium) on which a program is recorded, and includes a main body 2401, a display section 2402, and a speaker section 240.
3, a recording medium 2404, an operation switch 2405, and the like. This player uses a DVD (D
digital Versatile Disc), CD
And the like, it is possible to perform music appreciation, movie appreciation, games, and the Internet. The present invention can be applied to the display portion 2402.

FIG. 19F shows a digital camera, which includes a main body 2501, a display section 2502, an eyepiece section 2503, operation switches 2504, an image receiving section (not shown), and the like. The present invention can be applied to the display portion 2502.

FIG. 20A shows a front type projector, which includes a projection device 2601, a screen 2602, and the like. The present invention can be applied to the liquid crystal display device 2808 forming a part of the projection device 2601.

FIG. 20B shows a rear type projector, which includes a main body 2701, a projection device 2702, and a mirror 270.
3, including a screen 2704 and the like. The present invention relates to a projection device 2
702 can be applied to a liquid crystal display device 2808 which forms part of the liquid crystal display device.

FIG. 20C is a diagram showing an example of the structure of the projection devices 2601 and 2702 in FIGS. 20A and 20B. Projection devices 2601, 27
02 denotes a light source optical system 2801, mirrors 2802, 280
4 to 2806, dichroic mirror 2803, prism 2807, liquid crystal display device 2808, retardation plate 280
9. The projection optical system 2810. Projection optical system 28
Reference numeral 10 denotes an optical system including a projection lens. In the present embodiment, an example of a three-plate type is shown, but there is no particular limitation, and for example, a single-plate type may be used. Further, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarizing function, a film for adjusting a phase difference, and an IR film in the optical path indicated by the arrow in FIG. Good.

FIG. 20D is a diagram showing an example of the structure of the light source optical system 2801 in FIG. 20C. In this embodiment, the light source optical system 2801 includes a reflector 2811, a light source 2812, a lens array 2813,
814, a polarization conversion element 2815, and a condenser lens 2816. Note that the light source optical system shown in FIG. 20D is an example and is not particularly limited. For example, a practitioner may appropriately provide an optical system such as an optical lens, a film having a polarizing function, a film for adjusting a phase difference, and an IR film in the light source optical system.

FIG. 21A shows a mobile phone,
01, audio output unit 2902, audio input unit 2903, display unit 2904, operation switch 2905, antenna 2906
And so on. The present invention can be applied to the display portion 2904.

FIG. 21B shows a portable book (electronic book), which includes a main body 3001, display portions 3002 and 3003, a storage medium 3004, operation switches 3005, and an antenna 3006.
And so on. The present invention can be applied to the display units 3002 and 3003.

FIG. 21C shows a display, which includes a main body 3101, a support 3102, a display portion 3103, and the like.
The present invention can be applied to the display portion 3103. The display of the present invention is particularly advantageous when the screen is enlarged, and is advantageous for a display having a diagonal of 10 inches or more (particularly 30 inches or more).

As described above, the applicable range of the present invention is extremely wide, and can be applied to electronic devices in all fields. Further, the electronic apparatus according to the present embodiment can be realized by using any combination of the embodiments 1 to 7.

[0193]

According to the present invention, an insulating film used for each circuit of an electro-optical device typified by an IPS type LCD, particularly an electrode formed on a resin film, is used as an anodized film according to the present invention. By covering with, the wraparound amount can be reduced, and a highly reliable liquid crystal display device having electrodes having excellent adhesion can be manufactured.

Further, in a pixel portion of an electro-optical device typified by an IPS LCD, a storage capacitor having a large area and a small capacity can be formed. Therefore, even in an AM-LCD having a diagonal of 1 inch or less, a sufficient storage capacity can be secured without reducing the aperture ratio. In addition, since the wraparound amount of the anodic oxide film is scarce, the coverage of the pixel electrode formed thereon can be improved, and the yield can be improved.

[Brief description of the drawings]

1A and 1B are a top view and a cross-sectional view illustrating an example of a pixel portion of the present invention.

FIG. 2 is an equivalent circuit diagram.

FIG. 3 is a diagram showing a relationship between voltage and current between electrodes in an anodization method.

FIG. 4 is a view showing a manufacturing process of an LCD.

FIG. 5 is a view showing a manufacturing process of an LCD.

FIG. 6 is a view showing a manufacturing process of an LCD.

FIG. 7 is a view showing a manufacturing process of an LCD.

FIG. 8 is a sectional structural view of a liquid crystal display device.

FIG. 9 is a diagram showing an appearance of an LCD.

FIG. 10 illustrates a circuit of a liquid crystal display device.

FIG. 11 illustrates an example of a configuration of a storage capacitor.

FIG. 12 illustrates an example of a top view of a pixel portion.

FIG. 13 illustrates an example of a top view of a pixel portion.

FIG. 14 illustrates an example of a top view of a pixel portion.

FIG. 15 illustrates an example of a top view of a pixel portion.

FIG. 16 illustrates an example of a top view of a pixel portion.

FIG. 17 is a graph showing the absorbance characteristics of an aluminum film.

FIG. 18 illustrates an example of a structure of a TFT.

FIG. 19 illustrates an example of an electronic device.

FIG. 20 illustrates an example of an electronic device.

FIG. 21 illustrates an example of an electronic device.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 29/786 H01L 29/78 612B 21/336 612Z 619A

Claims (11)

[Claims] And a liquid crystal layer sandwiched between the pair of substrates. A pixel electrode is formed on one of the substrates, and the pixel electrode and a common electrode are provided. And a capacitor formed by a common electrode, an oxide film on at least a part of the common electrode, and a pixel electrode provided on the oxide film. A semiconductor device comprising: 2. The semiconductor device according to claim 1, wherein said common electrode is made of an anodizable material. 3. A liquid crystal display device comprising: a pair of substrates; and a liquid crystal layer sandwiched between the pair of substrates. A pixel electrode is formed on one of the pair of substrates. A common electrode, an anodic oxide film on at least a part of the common electrode, and a pixel electrode provided on the anodic oxide film. The liquid crystal layer is surrounded by a sealing material,
A semiconductor device, wherein a spacer is formed in a region where the sealing material is formed. 4. A liquid crystal display device comprising: a pair of substrates; and a liquid crystal layer sandwiched between the pair of substrates. A pixel electrode is formed on one of the pair of substrates, and the pixel electrode and a common electrode are provided. A common electrode, an anodic oxide film on at least a part of the common electrode, and a pixel electrode provided on the anodic oxide film. A semiconductor device, comprising: a capacitor having a capacitance; and a spacer formed in a region between a pixel portion provided with the pixel electrode and a driver circuit and a region where an element of the driver circuit does not exist. 5. A semiconductor device comprising: a pair of substrates; and a liquid crystal layer sandwiched between the pair of substrates. A pixel electrode is formed on one of the pair of substrates, and the pixel electrode and a common electrode are provided. A common electrode, an anodic oxide film on at least a part of the common electrode, and a pixel electrode provided on the anodic oxide film. A semiconductor device having a capacitor having a capacitance and a spacer on a contact portion of the pixel electrode. 6. The semiconductor device according to claim 1, wherein the oxide film is formed through an anodic oxidation step in which an applied voltage / power supply time is 11 V / min or more. 7. A video camera, a digital camera, a projector, a goggle type display, a car navigation, a personal computer, or a portable information terminal using the semiconductor device according to claim 1. . 8. A step of forming a resin film above the TFT, a step of forming a common electrode on the resin film, a step of forming an oxide film of the common electrode, and forming at least a part of the oxide film. Forming a pixel electrode covering the common electrode, a capacitor is formed by the common electrode, an oxide film of the common electrode, and the pixel electrode. 9. A step of forming a resin film above the TFT,
A step of forming an inorganic film on the resin film, a step of forming a common electrode on the inorganic film, a step of forming an oxide film of the common electrode, and a pixel electrode covering at least a part of the oxide film Forming a capacitor, wherein a capacitor is formed by the common electrode, an oxide film of the common electrode, and the pixel electrode. 10. The method for manufacturing a semiconductor device according to claim 9, wherein the step of forming the inorganic film on the resin film is performed by a sputtering method. 11. The method according to claim 8, wherein the step of forming the oxide film of the common electrode is an anodic oxidation step in which an applied voltage / power supply time is 11 V / min or more. A method for manufacturing a semiconductor device.