JP4197574B2 - Liquid crystal display - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device having a circuit formed of a thin film transistor (hereinafter referred to as TFT) and a method for manufacturing the semiconductor device. For example, the present invention relates to an electro-optical device typified by a liquid crystal display panel and an electronic apparatus in which such an electro-optical device is mounted as a component.
[0002]
Note that in this specification, a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics, and an electro-optical device, a semiconductor circuit, and an electronic device are all semiconductor devices.
[0003]
[Prior art]
In recent years, a technique for forming a thin film transistor (TFT) using a semiconductor thin film (having a thickness of about several to several hundred nm) formed on a substrate having an insulating surface has attracted attention. Thin film transistors are widely applied to electronic devices such as ICs and electro-optical devices, and development of switching devices for image display devices is urgently required.
[0004]
For example, in a liquid crystal display device, a TFT is arranged in each of millions of pixels arranged in a matrix, and the charge applied to each pixel electrode is controlled by the switching function of the TFT, whereby the electro-optical characteristics of the liquid crystal The image is displayed by controlling the light transmitted through the liquid crystal panel.
[0005]
In such a method for driving a liquid crystal display device, an IPS system (described in Japanese Patent Laid-Open No. 6-160878) is known in which a liquid crystal display device is driven by controlling a horizontal electric field with respect to a substrate by a parallel electrode structure. Yes.
[0006]
A liquid crystal display device driven by the IPS method can be driven at a low voltage, and has a higher viewing angle characteristic than other driving methods (TN method, STN method, etc.).
[0007]
The IPS liquid crystal display device includes a TFT, a gate line, a source line, a pixel electrode, a common line, and a common electrode extending from the common line in a pixel region on the same substrate. Further, in order to prevent the electric field applied to the pixel electrode from affecting other pixels, each pixel electrode is sandwiched between common electrodes arranged in parallel with the pixel electrode. Therefore, the IPS liquid crystal display device requires an electrode area of these electrodes, and the aperture ratio is reduced.
[0008]
In general, in a liquid crystal display device, it is necessary to form a storage capacitor in order to ensure a charge holding time. Also in the IPS liquid crystal display device, a sufficient electrode area is required to form a storage capacitor, so that the aperture ratio is low.
[0009]
Further, when the wiring and electrodes are miniaturized to improve the aperture ratio, it is difficult to ensure a sufficient storage capacity.
[0010]
[Problems to be solved by the invention]
The invention disclosed in this specification provides a technique for solving the above-described conventional problems. That is, an object of the present invention is to propose a method for forming a storage capacitor in an IPS liquid crystal display device and to provide a technique for forming a pixel region with a high aperture ratio.
[0011]
[Means for Solving the Problems]
The configuration of the invention disclosed in this specification is as follows.
A pair of substrates and a liquid crystal layer sandwiched between the pair of substrates
In the semiconductor device in which a pixel electrode is formed on one of the pair of substrates and an electric field parallel to the substrate surface is applied between the pixel electrode and the common electrode.
A semiconductor device including a capacitor formed by a common electrode, an oxide film on at least a part of the common electrode, and a pixel electrode provided on the oxide film.
[0012]
In the above structure, the common electrode is made of an anodizable material.
[0013]
In addition, the configuration of other inventions is as follows:
A pair of substrates and a liquid crystal layer sandwiched between the pair of substrates,
In the semiconductor device in which a pixel electrode is formed on one of the pair of substrates and an electric field parallel to the substrate surface is applied between the pixel electrode and the common electrode.
A capacitor formed by a common electrode, an anodized film on at least a part of the common electrode, and a pixel electrode provided on the anodized film;
The liquid crystal layer is surrounded by a sealing material, and a spacer is formed in a region where the sealing material is formed.
[0014]
In addition, the configuration of other inventions is as follows:
A pair of substrates and a liquid crystal layer sandwiched between the pair of substrates,
In the semiconductor device in which a pixel electrode is formed on one of the pair of substrates and an electric field parallel to the substrate surface is applied between the pixel electrode and the common electrode.
A capacitor formed by a common electrode, an anodized film on at least a part of the common electrode, and a pixel electrode provided on the anodized film;
In the semiconductor device, a spacer is formed in a region between a pixel portion provided with the pixel electrode and a driver circuit and a region where no element of the driver circuit exists.
[0015]
In addition, the configuration of other inventions is as follows:
A pair of substrates and a liquid crystal layer sandwiched between the pair of substrates,
In the semiconductor device in which a pixel electrode is formed on one of the pair of substrates and an electric field parallel to the substrate surface is applied between the pixel electrode and the common electrode.
A capacitor formed by a common electrode, an anodized film on at least a part of the common electrode, and a pixel electrode provided on the anodized film;
In the semiconductor device, a spacer is present on a contact portion of the pixel electrode.
[0016]
In each of the above structures, the oxide film is formed through an anodic oxidation process in which an applied voltage / power feeding time is 11 V / min or more.
[0017]
The configuration of the invention for realizing the above structure is as follows.
Forming a resin film above the TFT;
Forming a common electrode on the resin film;
Forming an oxide film of the common electrode;
Forming a pixel electrode covering at least a part of the oxide film,
In the method for manufacturing a semiconductor device, a capacitor is formed by the common electrode, the oxide film of the common electrode, and the pixel electrode.
[0018]
In addition, the configuration of other inventions is as follows:
Forming a resin film above the TFT;
Forming an inorganic film on the resin film;
Forming a common electrode on the inorganic film;
Forming an oxide film of the common electrode;
Forming a pixel electrode covering at least a part of the oxide film,
In the method for manufacturing a semiconductor device, a capacitor is formed by the common electrode, the oxide film of the common electrode, and the pixel electrode.
[0019]
In each of the above structures, the step of forming the inorganic film on the resin film is formed by a sputtering method.
[0020]
In each of the above structures, the step of forming the oxide film of the common electrode is an anodic oxidation step in which an applied voltage / power feeding time is 11 V / min or more.
[0021]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below.
[0022]
In the present invention, as shown in FIGS. 1A and 1B, a first electrode (common electrode 103) made of an anodizable material is provided, and an oxide film 105 is provided on the surface of the electrode. Further, a second electrode (pixel electrode 104) is provided over the oxide film, and the storage capacitor 106 using the oxide film formed by an anodic oxidation method as a dielectric is formed. In FIGS. 1A and 1B, 101 is a gate line, 101a and 101b are gate electrodes extending from the gate line, and 102 is a source line.
[0023]
In the present invention, the liquid crystal display device is driven by controlling the electric field in the horizontal direction (direction parallel to the substrate) formed by the first electrode (common electrode 103) and the second electrode (pixel electrode 104). Use the method. 2 is an equivalent circuit diagram corresponding to FIGS. 1 (A) and 1 (B).
[0024]
As anodizable materials used in the present invention, valve metal films (for example, aluminum, tantalum film, niobium film, hafnium film, zirconium film, chromium film, titanium film, etc.) and conductive silicon films (for example, phosphorus doped) A silicon film, a boron-doped silicon film, or the like), or a material mainly composed of a silicide film obtained by siliciding the valve metal film or a nitrided valve metal film (tantalum nitride film, tungsten nitride film, titanium nitride film, etc.). Can be used. Alternatively, an alloy (eg, a molybdenum tantalum alloy) that is a eutectic with another metal element (such as a tungsten film or a molybdenum film) can be used. Moreover, you may laminate | stack combining these freely.
[0025]
The valve metal refers to a metal in which a barrier type anodic oxide film produced in an anodic manner passes a cathode current but does not pass an anode current, that is, exhibits a valve action. (Electrochemical Handbook 4th Edition; edited by Electrochemical Society, p370, Maruzen, 1985)
[0026]
Further, the structure of the first electrode (common electrode 103) made of the anodizable material may be an electrode made of a single layer film or an electrode made of a multilayer film. In FIG. 1A, the first electrode (common electrode 103) can be operated in a floating state (electrically isolated state), but the pixel electrode shape shown in FIG. May be set to a level at which no flicker occurs near the common potential (intermediate potential of the image signal sent as data). Moreover, you may make it serve as the function of the shielding film which shields light and electromagnetic waves like the electrode shape shown in FIG. 1A illustrates an example in which the shape of the second electrode (the pixel electrode 104) is a T shape, but there is no particular limitation. For example, the shape of the pixel electrode may be a zigzag shape as shown in FIG. 14, a “<” shape as shown in FIG. 15, or a shape as shown in FIG.
[0027]
Note that in this specification, an “electrode” is a part of “wiring” and refers to a portion where electrical connection with another wiring is made or a portion intersecting with a semiconductor layer. Therefore, for convenience of explanation, “wiring” and “electrode” are used properly, but “wiring” is always included in the term “electrode”.
[0028]
Further, the anodic oxidation method of the present invention uses a method different from the conventional method (a method in which the current and voltage flowing between the anode and the cathode immersed in the anodic oxidation solution are shifted from the constant current state to the constant voltage state). In the conventional method, when a material film having poor adhesion to an anodizable material, for example, an organic resin film, is provided with an electrode thereon, and the electrode is anodized, it is inevitably non-uniform anodization at the electrode end. The film was peeled off due to the anodic oxide film.
[0029]
Therefore, in the present invention, compared with the conventional case, the current value per unit area of the electrode to be anodized in the anodizing step of the present invention and the applied voltage value per unit time are set to a large value, and the target voltage is reached. When completed in stages, the amount of wraparound could be reduced. In addition, in order to shorten the time required for the anodic oxidation step, the anodic oxide film is formed by setting the constant voltage state time to several seconds to several minutes, or setting the constant voltage state time to zero.
[0030]
An example of the forming method of the present invention will be described below with reference to FIG. Of course, the voltage becomes zero at the stage where the anodizing step is completed, but it is not shown in FIG.
[0031]
Specifically, the current density (current amount per unit area) of the electrode to be anodized is 1 to 20 mA / cm.²It is preferable that In addition, the conventional current density (about 0.3 mA / cm²Current density is greater than
[0032]
Further, the voltage increase rate (voltage value increased per unit time) was set to 11 V / min or more, preferably 100 V / min or more. Similarly, it is larger than the conventional voltage increase rate (about 10 V / min).
[0033]
FIG. 8 shows a cross-sectional view of an LCD using an anodic oxide film using the present invention as a dielectric of a storage capacitor arranged in the pixel portion. Here, a CMOS circuit is shown as a basic circuit constituting a driver circuit, and a TFT having a double gate structure is shown as a TFT in a pixel portion. Of course, not only the double gate structure but also a triple gate structure or a single gate structure may be used. The structure of the TFT is not limited to the top gate type TFT, but can be applied to other structures such as a bottom gate type TFT.
[0034]
The present invention having the above-described configuration will be described in more detail with the following examples.
[0035]
【Example】
[Embodiment 1] An embodiment of the present invention will be described with reference to FIGS. Here, a method for simultaneously manufacturing a pixel portion and a driver circuit for driving the pixel portion over the same substrate will be described. However, in order to simplify the description, a CMOS circuit that is a basic circuit such as a shift register circuit and a buffer circuit in the driver circuit and an n-channel TFT that forms a sampling circuit are illustrated.
[0036]
In FIG. 4A, it is desirable to use a quartz substrate or a silicon substrate for the substrate 401. In this example, a quartz substrate was used. In addition, a substrate in which an insulating film is formed on the surface of a metal substrate or stainless steel substrate may be used. In the case of the present embodiment, heat resistance that can withstand a temperature of 800 ° C. or higher is required, so any substrate that satisfies this requirement may be used.
[0037]
Then, a semiconductor film 402 having an amorphous structure with a thickness of 20 to 100 nm (preferably 40 to 80 nm) is formed on the surface of the substrate 401 on which the TFT is formed by low pressure CVD, plasma CVD, or sputtering. Form. In this embodiment, an amorphous silicon film having a thickness of 60 nm is formed. However, since there is a thermal oxidation process later, this film thickness does not necessarily become the film thickness of the active layer of the TFT.
[0038]
The semiconductor film including an amorphous structure includes an amorphous semiconductor film and a microcrystalline semiconductor film, and further includes a compound semiconductor film including an amorphous structure such as an amorphous silicon germanium film. Further, it is also effective to continuously form the base film and the amorphous silicon film on the substrate without releasing to the atmosphere. By doing so, it becomes possible to prevent the contamination of the substrate surface from affecting the amorphous silicon film and to reduce the characteristic variation of the manufactured TFT.
[0039]
Next, a mask film 403 made of an insulating film containing silicon (silicon) is formed on the amorphous silicon film 402, and openings 404a and 404b are formed by patterning. This opening becomes an addition region for adding a catalytic element that promotes crystallization in the next crystallization step. (Fig. 4 (A))
[0040]
Note that as the insulating film containing silicon, a silicon oxide film, a silicon nitride film, or a silicon nitride oxide film can be used. The silicon nitride oxide film is an insulating film containing silicon, nitrogen, and oxygen in predetermined amounts, and is an insulating film represented by SiOxNy. Silicon nitride oxide film is SiH_Four, N₂O and NH_ThreeCan be produced as a raw material gas, and the concentration of nitrogen contained is preferably 25 atomic% or more and less than 50 atomic%.
[0041]
At the same time that the mask film 403 is patterned, a marker pattern that serves as a reference for a subsequent patterning process is formed. When the mask film 403 is etched, the amorphous silicon film 402 is also slightly etched, but this step can be used as a marker pattern later when the mask is aligned.
[0042]
Next, a semiconductor film including a crystal structure is formed according to the technique described in Japanese Patent Application Laid-Open No. 10-247735 (corresponding to US Application No. 09 / 034,041). The technology described in this publication is a catalyst element (one or more selected from nickel, cobalt, germanium, tin, lead, palladium, iron, copper) that promotes crystallization when a semiconductor film including an amorphous structure is crystallized. Crystallization means using seed elements).
[0043]
Specifically, heat treatment is performed with the catalytic element held on the surface of a semiconductor film including an amorphous structure, and the semiconductor film including the amorphous structure is changed to a semiconductor film including a crystalline structure. is there. In addition, as a crystallization means, you may use the technique described in Example 1 of Unexamined-Japanese-Patent No. 7-130652. In addition, a semiconductor film including a crystalline structure includes a so-called single crystal semiconductor film and a polycrystalline semiconductor film, but the semiconductor film including a crystal structure formed in this publication has a crystal grain boundary.
[0044]
In this publication, the spin coating method is used when forming the layer containing the catalytic element on the mask film, but means for forming the thin film containing the catalytic element using a vapor phase method such as sputtering or vapor deposition. You may take.
[0045]
Further, although the amorphous silicon film depends on the amount of hydrogen contained, it is preferable to perform heat treatment at 400 to 550 ° C. for about 1 hour to crystallize after sufficiently desorbing hydrogen. In that case, the hydrogen content is preferably 5 atom% or less.
[0046]
In the crystallization step, first, a heat treatment step is performed at 400 to 500 ° C. for about 1 hour to desorb hydrogen from the film, and then 500 to 650 ° C. (preferably 550 to 600 ° C.) for 6 to 16 hours (preferably For 8-14 hours).
[0047]
In this embodiment, nickel is used as a catalyst element and heat treatment is performed at 570 ° C. for 14 hours. As a result, a semiconductor film including a crystal structure in which crystallization progresses in a direction substantially parallel to the substrate (direction indicated by an arrow) starting from the openings 404a and 404b and the macroscopic crystal growth directions are aligned (this embodiment) Then, crystalline silicon films) 405a to 405d are formed. (Fig. 4 (B))
[0048]
Next, a gettering step for removing nickel used in the crystallization step from the crystalline silicon film is performed. In this embodiment, an element belonging to Group 15 (phosphorus in this embodiment) is added using the mask film 403 formed earlier as a mask as it is, and 1 × 10 10 is applied to the crystalline silicon film exposed at the openings 404a and 404b.¹⁹~ 1x10²⁰atoms / cm^ThreePhosphorus-added regions containing phosphorus (hereinafter referred to as gettering regions) 406a and 406b are formed. (Fig. 4 (C))
[0049]
Next, a heat treatment step of 450 to 650 ° C. (preferably 500 to 550 ° C.) and 4 to 24 hours (preferably 6 to 12 hours) is performed in a nitrogen atmosphere. By this heat treatment process, nickel in the crystalline silicon film moves in the direction of the arrow and is captured in the gettering regions 406a and 406b by the gettering action of phosphorus. That is, since nickel is removed from the crystalline silicon film, the concentration of nickel contained in the crystalline silicon films 407a to 407d after gettering is 1 × 10¹⁷atms / cm^ThreeOr less, preferably 1 × 10¹⁶atms / cm^ThreeIt can be reduced to.
[0050]
Next, the mask film 403 is removed, and a protective film 408 is formed on the crystalline silicon films 407a to 407d for later impurity addition. As the protective film 408, a silicon nitride oxide film or a silicon oxide film with a thickness of 100 to 200 nm (preferably 130 to 170 nm) is preferably used. This protective film 408 is meaningful in order to prevent the crystalline silicon film from being directly exposed to plasma when impurities are added, and to enable fine concentration control.
[0051]
Then, a resist mask 409 is formed thereon, and an impurity element imparting p-type (hereinafter referred to as a p-type impurity element) is added through the protective film 408. As the p-type impurity element, typically, an element belonging to Group 13, typically boron or gallium can be used. This step (referred to as channel doping step) is a step for controlling the threshold voltage of the TFT. Here, diborane (B₂H₆Boron is added by ion doping that is plasma-excited without mass separation. Of course, an ion implantation method for performing mass separation may be used.
[0052]
1x10 by this process¹⁵~ 1x10¹⁸atoms / cm^Three(Typically 5 × 10¹⁶~ 5x10¹⁷atoms / cm^Three) Impurity regions 410a and 410b containing a p-type impurity element (boron in this embodiment) are formed. In the present specification, an impurity region containing a p-type impurity element in the above concentration range (however, a region not containing phosphorus) is defined as a p-type impurity region (b). (Fig. 4 (D))
[0053]
Next, the resist mask 409 is removed, and the crystalline silicon film is patterned to form island-like semiconductor layers (hereinafter referred to as active layers) 411 to 414. The active layers 411 to 414 are formed of a crystalline silicon film having very good crystallinity by selectively adding nickel and crystallizing. Specifically, it has a crystal structure in which rod-like or columnar crystals are arranged with a specific direction. Further, after crystallization, nickel is removed or reduced by the gettering action of phosphorus, and the concentration of the catalytic element remaining in the active layers 411 to 414 is 1 × 10¹⁷atms / cm^ThreeOr less, preferably 1 × 10¹⁶atms / cm^ThreeIt is. (Fig. 4 (E))
[0054]
The active layer 411 of the p-channel TFT is a region that does not contain the impurity element added intentionally, and the active layers 412 to 414 of the n-channel TFT are p-type impurity regions (b). In this specification, it is defined that all the active layers 411 to 414 in this state are intrinsic or substantially intrinsic. In other words, a region where an impurity element is intentionally added to such an extent that does not hinder the operation of the TFT may be considered as a substantially intrinsic region.
[0055]
Next, an insulating film containing silicon having a thickness of 10 to 100 nm is formed by plasma CVD or sputtering. In this embodiment, a silicon nitride oxide film having a thickness of 30 nm is formed. As the insulating film containing silicon, another insulating film containing silicon may be used as a single layer or a stacked layer.
[0056]
Next, a heat treatment step at a temperature of 800 to 1150 ° C. (preferably 900 to 1000 ° C.) for 15 minutes to 8 hours (preferably 30 minutes to 2 hours) is performed in an oxidizing atmosphere (thermal oxidation step). In this embodiment, a heat treatment step is performed at 950 ° C. for 80 minutes in an atmosphere in which 3% by volume of hydrogen chloride is added to an oxygen atmosphere. Note that boron added in the step of FIG. 4D is activated during this thermal oxidation step. (Fig. 5 (A))
[0057]
Note that the oxidizing atmosphere may be either a dry oxygen atmosphere or a wet oxygen atmosphere, but a dry oxygen atmosphere is suitable for reducing crystal defects in the semiconductor layer. In this embodiment, an atmosphere in which a halogen element is included in an oxygen atmosphere is used. However, a 100% oxygen atmosphere may be used. Moreover, you may carry out by the high pressure oxidation method.
[0058]
During this thermal oxidation process, an oxidation reaction also proceeds at the interface between the insulating film containing silicon and the active layers 411 to 414 therebelow. In the present invention, in consideration thereof, the thickness of the gate insulating film 415 to be finally formed is adjusted to be 50 to 200 nm (preferably 100 to 150 nm). In the thermal oxidation process of the present embodiment, 25 nm of the 60 nm thick active layer is oxidized, and the film thickness of the active layers 411 to 414 becomes 35 nm. Further, since a 50 nm thick thermal oxide film is added to the 30 nm thick silicon-containing insulating film, the final gate insulating film 415 has a thickness of 80 nm.
[0059]
Next, resist masks 416 to 419 are newly formed. Then, an impurity element imparting n-type (hereinafter referred to as n-type impurity element) is added to form impurity regions 420 to 422 exhibiting n-type. Note that as the n-type impurity element, an element belonging to Group 15 typically, phosphorus or arsenic can be used. (Fig. 5 (B))
[0060]
The impurity regions 420 to 422 are impurity regions for functioning as LDD regions later in the n-channel TFTs of the CMOS circuit and the sampling circuit. Note that the impurity region formed here contains 2 × 10 n-type impurity elements.¹⁶~ 5x10¹⁹atoms / cm^Three(Typically 5 × 10¹⁷~ 5x10¹⁸atoms / cm^Three) Concentration. In this specification, an impurity region containing an n-type impurity element in the above concentration range is defined as an n-type impurity region (b).
[0061]
Here, phosphine (PH_Three) By mass-separated plasma-excited ion doping method with 1 × 10 phosphorus¹⁸atoms / cm^ThreeAdd at a concentration of Of course, an ion implantation method for performing mass separation may be used. In this step, phosphorus is added to the crystalline silicon film through the gate film 415.
[0062]
Next, heat treatment is performed in an inert atmosphere at 600 to 1000 ° C. (preferably 700 to 800 ° C.) to activate phosphorus added in the step of FIG. In this embodiment, heat treatment at 800 ° C. for 1 hour is performed in a nitrogen atmosphere. (Fig. 5 (C))
[0063]
At the same time, it is possible to repair the active layer damaged during the addition of phosphorus and the interface between the active layer and the gate insulating film. This activation step is preferably furnace annealing using an electric furnace, but light annealing such as lamp annealing or laser annealing may be used in combination.
[0064]
By this step, the boundary portion of the n-type impurity region (b) 420 to 422, that is, the intrinsic or substantially intrinsic region existing around the n-type impurity region (b) (of course, the p-type impurity region (b) is also included). The joint part becomes clear. This means that when the TFT is later completed, the LDD region and the channel formation region can form a very good junction.
[0065]
Next, a conductive film to be a gate wiring is formed. Note that although the gate wiring may be formed using a single-layer conductive film, it is preferable to form a stacked film such as two layers or three layers as necessary. In this embodiment, a stacked film including a first conductive film 423 and a second conductive film 424 is formed. (Fig. 5 (D))
[0066]
Here, as the first conductive film 423 and the second conductive film 424, an element selected from tantalum (Ta), titanium (Ti), molybdenum (Mo), tungsten (W), chromium (Cr), and silicon (Si). Or a conductive film containing the element as a main component (typically a tantalum nitride film, a tungsten nitride film, a titanium nitride film), or an alloy film (typically a Mo—W alloy film, Mo— Ta alloy film, tungsten silicide film, etc.) can be used.
[0067]
Note that the first conductive film 423 may be 10 to 50 nm (preferably 20 to 30 nm), and the second conductive film 424 may be 200 to 400 nm (preferably 250 to 350 nm). In this embodiment, a 50 nm-thick tungsten nitride (WN) film is used as the first conductive film 423, and a 350 nm-thick tungsten film is used as the second conductive film 424. Although not shown, it is effective to form a silicon film with a thickness of about 2 to 20 nm below the first conductive film 423. Thereby, the improvement of the adhesiveness of the electrically conductive film formed on it and prevention of oxidation can be aimed at.
[0068]
It is also effective to use a tantalum nitride film as the first conductive film 423 and a tantalum film as the second conductive film.
[0069]
Next, the first conductive film 423 and the second conductive film 424 are collectively etched to form gate wirings 425 to 428 having a thickness of 400 nm. At this time, the gate wirings 426 and 427 formed in the driver circuit are formed so as to overlap a part of the n-type impurity regions (b) 420 to 422 with the gate insulating film 415 interposed therebetween. This overlapped portion later becomes the Lov region. Note that although the gate wirings 428a and 428b appear to be two in the cross section, they are actually formed from a single continuous pattern. (Fig. 5 (E))
[0070]
Next, a resist mask 429 is formed, and a p-type impurity element (boron in this embodiment) is added to form impurity regions 430 and 431 containing boron at a high concentration. In this example, diborane (B₂H₆3 × 10 by an ion doping method (which may of course be an ion implantation method).²⁰~ 3x10^{twenty one}atoms / cm^Three(Typically 5 × 10²⁰~ 1x10^{twenty one}atoms / cm^Three) Add boron at a concentration. In this specification, an impurity region containing a p-type impurity element in the above concentration range is defined as a p-type impurity region (a). (Fig. 6 (A))
[0071]
Next, the resist mask 429 is removed, and resist masks 432 to 434 are formed so as to cover a region to be a gate wiring and a p-channel TFT. Then, an n-type impurity element (phosphorus in this embodiment) is added to form impurity regions 435 to 441 containing phosphorus at a high concentration. Again, phosphine (PH_Three) Using an ion doping method (of course, an ion implantation method may be used), and the phosphorus concentration in this region is 1 × 10²⁰~ 1x10^{twenty two}atoms / cm^Three(Typically 2 × 10²⁰~ 5x10^{2 1}atoms / cm^Three). (Fig. 6 (B))
[0072]
In this specification, an impurity region containing an n-type impurity element in the above concentration range is defined as an n-type impurity region (a). The region where the impurity regions 435 to 441 are formed already contains phosphorus or boron added in the previous step. However, since phosphorus is added at a sufficiently high concentration, it is added in the previous step. There is no need to consider the effects of phosphorus or boron. Therefore, in this specification, the impurity regions 435 to 441 may be referred to as n-type impurity regions (a).
[0073]
Next, the resist masks 432 to 434 are removed, and a cap film 442 made of an insulating film containing silicon is formed. The film thickness may be 25 to 100 nm (preferably 30 to 50 nm). In this embodiment, a silicon nitride film having a thickness of 25 nm is used. The cap film 442 also functions as a protective film for preventing the oxidation of the gate wiring in a later activation process. However, if it is formed too thick, the stress increases and problems such as film peeling occur. Is preferred.
[0074]
Next, an n-type impurity element (phosphorus in this embodiment) is added in a self-aligning manner using the gate wirings 425 to 428 as masks. The impurity regions 443 to 446 thus formed have a concentration of 1/2 to 1/10 (typically 1/3 to 1/4) of the n-type impurity region (b) (however, the channel doping step described above) Concentration 5-10 times higher than the boron concentration added, typically 1 × 10¹⁶~ 5x10¹⁸atoms / cm^Three, Typically 3x10¹⁷~ 3x10¹⁸atoms / cm^Three)) So that phosphorus is added. Note that in this specification, an impurity region containing an n-type impurity element in the above concentration range (excluding the p-type impurity region (a)) is defined as an n-type impurity region (c). (Fig. 6 (C))
[0075]
In this step, phosphorus is added through an insulating film having a thickness of 105 nm (a stacked film of a cap film 442 and a gate insulating film 415). The cap film formed on the side walls of the gate wirings 434a and 434b is also used as a mask. Function. That is, an offset region having a length corresponding to the film thickness of the cap film 442 is formed. Note that an offset region is a high-resistance region which is formed in contact with a channel formation region and is formed using a semiconductor film having the same composition as the channel formation region but does not form an inversion layer (channel region) because no gate voltage is applied. . In order to reduce the off-current value, it is important to suppress the overlap between the LDD region and the gate wiring as much as possible, and it can be said that it is effective to provide an offset region in that sense.
[0076]
As in this embodiment, the channel formation region is also 1 × 10¹⁵~ 1x10¹⁸atoms / cm^ThreeWhen the p-type impurity element is included at the concentration of, the p-type impurity element is naturally included in the offset region at the same concentration.
[0077]
The length of this offset region is determined by the film thickness of the cap film actually formed on the side wall of the gate wiring and the wraparound phenomenon (a phenomenon in which the impurity is added so as to go under the mask) when the impurity element is added. However, from the viewpoint of suppressing the overlap between the LDD region and the gate wiring, it is very effective to form a cap film in advance when forming the n-type impurity region (c) as in the present invention. is there.
[0078]
In this step, all impurity regions except for the portion hidden by the gate wiring are also 1 × 10 6.¹⁶~ 5x10¹⁸atoms / cm^ThreeHowever, since the concentration is very low, the function of each impurity region is not affected. In addition, the n-type impurity regions (b) 443 to 446 have already been channeled by 1 × 10¹⁵~ 1x10¹⁸atoms / cm^ThreeIn this step, phosphorus is added at a concentration 5 to 10 times that of boron contained in the p-type impurity region (b). In this case as well, boron is added to the n-type impurity region ( It may be considered that the function of b) is not affected.
[0079]
Strictly speaking, however, the phosphorus concentration of the portion of the n-type impurity regions (b) 447 and 448 overlapping the gate wiring is 2 × 10.¹⁶~ 5x10¹⁹atoms / cm^ThreeWhereas the portion that does not overlap the gate wiring is 1 × 10¹⁶~ 5x10¹⁸atoms / cm^ThreeThe concentration of phosphorus is added, and phosphorus is contained at a slightly higher concentration.
[0080]
Next, a first interlayer insulating film 449 is formed. The first interlayer insulating film 449 may be formed using an insulating film containing silicon, specifically, a silicon nitride film, a silicon oxide film, a silicon nitride oxide film, or a stacked film including a combination thereof. The film thickness may be 100 to 400 nm. In this example, SiH is used by plasma CVD._Four, N₂O, NH_ThreeAs a source gas, a 200 nm thick silicon nitride oxide film (however, the nitrogen concentration is 25 to 50 atomic%) is used.
[0081]
Thereafter, a heat treatment process was performed to activate the n-type or p-type impurity element added at each concentration. This step can be performed by furnace annealing, laser annealing, lamp annealing, or a combination thereof. In the case of performing the furnace annealing method, it may be performed at 500 to 800 ° C., preferably 550 to 600 ° C. in an inert atmosphere. In this embodiment, a heat treatment is performed at 600 ° C. for 4 hours to activate the impurity element. (Fig. 6 (D))
[0082]
In this embodiment, the gate wiring is covered in a state where the silicon nitride film 442 and the silicon nitride oxide film 449 are stacked, and the activation process is performed in that state. In this embodiment, tungsten is used as a wiring material, but it is known that the tungsten film is very vulnerable to oxidation. That is, even if it covers and oxidizes with a protective film, if a pinhole exists in a protective film, it will be oxidized immediately. However, in this embodiment, a very effective silicon nitride film is used as the anti-oxidation film, and the silicon nitride oxide film is laminated on the silicon nitride film. It is possible to carry out the activation process at a high temperature without using it.
[0083]
Next, after the activation step, heat treatment is performed at 300 to 450 ° C. for 1 to 4 hours in an atmosphere containing 3 to 100% hydrogen to hydrogenate the active layer. This step is a step of terminating dangling bonds in the semiconductor layer with thermally excited hydrogen. As another means of hydrogenation, plasma hydrogenation (using hydrogen excited by plasma) may be performed.
[0084]
When the activation process is completed, a second interlayer insulating film 450 having a thickness of 500 nm to 1.5 μm is formed on the first interlayer insulating film 449. In this embodiment, a silicon oxide film having a thickness of 800 nm is formed as the second interlayer insulating film 450 by a plasma CVD method. In this way, an interlayer insulating film having a thickness of 1 μm formed of a laminated film of the first interlayer insulating film (silicon nitride oxide film) 449 and the second interlayer insulating film (silicon oxide film) 450 is formed.
[0085]
Note that an organic resin film such as polyimide, acrylic, polyamide, polyimide amide, or BCB (benzocyclobutene) can be used as the second interlayer insulating film 450 if heat resistance is allowed in a later step.
[0086]
Thereafter, contact holes reaching the source region or the drain region of each TFT are formed, and source wirings 451 to 454 and drain wirings 455 to 457 are formed. In order to form a CMOS circuit, the drain wiring 455 is shared between the p-channel TFT and the n-channel TFT. Although not shown, in this embodiment, this wiring is a laminated film having a three-layer structure in which a Ti film is 200 nm, an aluminum film 500 nm containing Ti, and a Ti film 100 nm are continuously formed by sputtering.
[0087]
Next, the passivation film 458 is formed using a silicon nitride film, a silicon oxide film, or a silicon nitride oxide film with a thickness of 50 to 500 nm (typically 200 to 300 nm). (FIG. 7A) At this time, in this embodiment, H is formed prior to film formation.₂, NH_ThreePlasma treatment is performed using a gas containing hydrogen, and heat treatment is performed after film formation. Hydrogen excited by this pretreatment is supplied into the first and second interlayer insulating films. By performing heat treatment in this state, the film quality of the passivation film 458 is improved and hydrogen added to the first and second interlayer insulating films diffuses to the lower layer side, so that the active layer is effectively hydrogenated. be able to.
[0088]
Further, a hydrogenation step may be further performed after the passivation film 458 is formed. For example, heat treatment may be performed at 300 to 450 ° C. for 1 to 12 hours in an atmosphere containing 3 to 100% hydrogen, or the same effect can be obtained by using a plasma hydrogenation method. Note that an opening (not shown) may be formed in the passivation film 458 at a position where a contact hole for connecting the pixel electrode and the drain wiring is formed after the hydrogenation step.
[0089]
Thereafter, a third interlayer insulating film 459 made of an organic resin is formed to a thickness of about 1 μm. As the organic resin, polyimide, acrylic, polyamide, polyimide amide, BCB (benzocyclobutene), or the like can be used. Advantages of using the organic resin film are that the film forming method is simple, the relative dielectric constant is low, the parasitic capacitance can be reduced, and the flatness is excellent. Note that organic resin films other than those described above, organic SiO compounds, and the like can also be used. Here, after applying to the substrate, a thermal polymerization type polyimide is used and baked at 300 ° C.
[0090]
Next, the common electrode 460 is formed over the third interlayer insulating film 459 in the region to be the pixel portion. Note that the common electrode 460 may also function as a shielding film that blocks light and electromagnetic waves. The common electrode 460 is an anodizable material, for example, a film made of an element selected from aluminum (Al), titanium (Ti), and tantalum (Ta) or a film containing any element as a main component and having a thickness of 100 to 300 nm. Form to thickness. In this embodiment, an aluminum film containing 1 wt% titanium is formed to a thickness of 125 nm.
[0091]
Note that if an insulating film such as a silicon oxide film is formed to a thickness of 5 to 50 nm on the third interlayer insulating film 459, the adhesion of the common electrode formed thereon can be improved. Further, CF is formed on the surface of the third interlayer insulating film 459 formed of an organic resin._FourWhen plasma treatment using a gas is performed, the adhesion of the common electrode formed on the film can be improved by surface modification.
[0092]
In addition, it is possible to form not only the common electrode but also other connection wiring by using the aluminum film containing titanium. For example, it is possible to form a connection wiring that connects circuits in the drive circuit. However, in that case, it is necessary to form a contact hole in the third interlayer insulating film in advance before forming a material for forming the common electrode or the connection wiring.
[0093]
Next, an oxide 461 having a thickness of 20 to 100 nm (preferably 30 to 50 nm) is formed on the surface of the common electrode 460 by an anodic oxidation method or a plasma oxidation method (an anodic oxidation method in this embodiment). At this time, in order to anodize, the common electrode is patterned into a connected shape. The common electrodes are arranged with a certain margin so that the ends of the common electrodes do not short-circuit each other. In this embodiment, since a film containing aluminum as a main component is used as the common electrode 460, an aluminum oxide film (alumina film) is formed as the anodic oxide 461.
[0094]
In this anodizing treatment, first, an ethylene glycol tartrate solution having a sufficiently low alkali ion concentration is prepared. This is a solution of 15% ammonium tartrate aqueous solution and ethylene glycol mixed at 2: 8, and ammonia water is added to this to adjust the pH to 7 ± 0.5. Then, a platinum electrode serving as a cathode is provided in the solution, the substrate on which the common electrode 460 is formed is immersed in the solution, and a constant (several mA to several tens mA) direct current is passed using the common electrode 460 as an anode.
[0095]
The voltage between the cathode and the anode in the solution changes with time according to the growth of the anodic oxide, but the voltage is increased at a step-up rate of 100 V / min with a constant current, and when the voltage reaches 45 V, anodization is performed. End the process. In this manner, an anodic oxide 461 having a thickness of about 50 nm can be formed on the surface of the common electrode 460 on the organic resin film. Note that the anodic oxide film 461 formed by the anodic oxidation method has less wraparound at the electrode end portion and is less likely to be peeled off as compared with the conventional anodic oxidation film formed by the anodic oxidation method. As a result, the common electrode 460 has a film thickness of 90 nm. The numerical values related to the anodic oxidation method shown here are only examples, and the optimum values can naturally vary depending on the size of the element to be manufactured.
[0096]
In the case where the common electrode 460 also functions as a shielding film, the starting film thickness of the aluminum film was changed in three conditions (65 nm, 95 nm, and 125 nm), and the anodic oxidation conditions were all the same, and an anodic oxide film having a film thickness of 50 nm was formed. . Then, the electrode film thickness which was not anodized became 30 nm, 60 nm, and 90 nm.
[0097]
FIG. 17 shows the results of measurement with a Hitachi spectrophotometer U-4000. It can be seen from FIG. 17 that the electrode film thickness at 550 nm: the absorbance at 30 nm is 2.6, the electrode film thickness: the absorbance at 60 nm is 4, and the electrode film thickness: the absorbance at 90 nm is 4.6. The absorbance (at 550 nm) required when the electrode is used as a shielding film may be 3 or more. Therefore, if it is 60 nm or more, it functions as a shielding film without any problem. If light leakage due to a step is taken into consideration, the shielding film is preferably thin.
[0098]
Thereafter, the common electrodes connected at the time of anodic oxidation were divided to form the common electrode shown in FIG. Next, a contact hole reaching the drain wiring 457 is formed in the third interlayer insulating film 459 and the passivation film 458, and a pixel electrode 462 is formed. The pixel electrode 462 may be formed by patterning a conductive metal film having a thickness of 100 to 300 nm. In this embodiment, an aluminum film is used.
[0099]
At this time, a region where the pixel electrode 462 and the common electrode 460 overlap with each other through the anodic oxide 461 forms a storage capacitor (capacitance storage) 464. In this case, the common electrode 460 is desirably set to a floating state (electrically isolated state) or a fixed potential, preferably a common potential (an intermediate potential of an image signal transmitted as data).
[0100]
Thus, an element substrate having a drive circuit and a pixel portion on the same substrate was completed. Note that in FIG. 7B, a p-channel TFT 601 and n-channel TFTs 602 and 603 are formed in the driver circuit, and a pixel TFT 604 including an n-channel TFT is formed in the pixel portion.
[0101]
In the p-channel TFT 601 of the driver circuit, a channel formation region 501, a source region 502, and a drain region 503 are each formed with a p-type impurity region (a). However, strictly speaking, the source 502 region and the drain region 503 are 1 × 10¹⁶~ 5x10¹⁸atoms / cm^ThreeContains phosphorus at a concentration of.
[0102]
The n-channel TFT 602 includes a channel formation region 504, a source region 505, a drain region 506, and a region overlapping with a gate wiring through a gate insulating film between the channel formation region and the drain region (this specification In this case, such a region is referred to as a Lov region, where ov is attached in the meaning of overlap.) 507 is formed. At this time, the Lov region 507 is 2 × 10.¹⁶~ 5x10¹⁹atoms / cm^ThreeIt is formed so as to contain phosphorus at a concentration of 5 and overlap with the gate wiring.
[0103]
In the n-channel TFT 603, a channel formation region 508, a source region 509, a drain region 510, and LDD regions 511 and 512 are formed so as to sandwich the channel formation region. That is, an LDD region is formed between the source region and the channel formation region and between the drain region and the channel formation region.
[0104]
In this structure, the LDD regions 511 and 512 are arranged so that part of the LDD regions 511 and 512 overlap with the gate wiring. Therefore, the region overlapping the gate wiring (Lov region) through the gate insulating film and the region not overlapping with the gate wiring (this In the specification, such an area is referred to as an Loff area, where “off” is an offset meaning).
[0105]
The LDD region 511 can be further divided into a Lov region and a Loff region. In addition, the above Lov region has 2 × 10.¹⁶~ 5x10¹⁹atoms / cm^ThreeThe Loff region contains phosphorus at a concentration of 1 to 2 times (typically 1.2 to 1.5 times).
[0106]
In the pixel TFT 604, n-type impurity regions (a) 521 in contact with the channel formation regions 513 and 514, the source region 515, the drain region 516, the Loff regions 517 to 520, and the Loff regions 518 and 519 are formed. At this time, the source region 515 and the drain region 516 are each formed of an n-type impurity region (a), and the Loff regions 517 to 520 are formed of an n-type impurity region (c).
[0107]
In this embodiment, the structure of the TFT forming each circuit can be optimized according to the circuit specifications required by the pixel portion and the drive circuit, and the operation performance and reliability of the semiconductor device can be improved. Specifically, an n-channel TFT has a TFT structure in which high-speed operation or hot carrier countermeasures are emphasized on the same substrate by changing the arrangement of the LDD region according to circuit specifications and using the Lov region or Loff region separately. A TFT structure emphasizing low off-current operation can be realized.
[0108]
For example, in the case of an active matrix liquid crystal display device, the n-channel TFT 602 is suitable for a drive circuit such as a shift register circuit, a frequency divider circuit, a signal dividing circuit, a level shifter circuit, or a buffer circuit that places importance on high-speed operation. In other words, by forming the Lov region only between the channel formation region and the drain region, the resistance component is reduced as much as possible, and the structure with an emphasis on measures against hot carriers is provided. This is because in the case of the above circuit group, the functions of the source region and the drain region are not changed, and the direction in which carriers (electrons) move is constant.
[0109]
However, if necessary, the Lov region can be formed with the channel formation region interposed therebetween. In other words, it can be formed between the source region and the channel formation region and between the drain region and the channel formation region.
[0110]
Further, the n-channel TFT 603 is suitable for a sampling circuit (sample hold circuit) that places importance on both hot carrier countermeasures and low off-current operation. That is, by forming the Lov region, a countermeasure against hot carriers is taken, and by forming the Loff region, a low off-current operation is realized. In addition, since the functions of the source region and the drain region are inverted and the carrier moving direction is changed by 180 °, the sampling circuit must be structured so as to be symmetric with respect to the gate wiring. In some cases, only the Lov region may be used.
[0111]
The n-channel TFT 604 is suitable for a pixel portion and a sampling circuit (sample hold circuit) that place importance on low off-current operation. That is, the low off-current operation is realized by arranging the Loff region and the offset region without arranging the Lov region that may increase the off-current value. Further, by using an LDD region having a lower concentration than the LDD region of the drive circuit as the Loff region, a measure is taken to thoroughly reduce the off-current value even if the on-current value is somewhat lowered. Furthermore, it has been confirmed that the n-type impurity region (a) 521 is very effective in reducing the off-current value.
[0112]
The length (width) of the Lov region 507 of the n-channel TFT 602 may be 0.3 to 3.0 μm, typically 0.5 to 1.5 μm, with respect to the channel length of 3 to 7 μm. The length (width) of the Lov regions 511a and 512a of the n-channel TFT 603 is 0.3 to 3.0 μm, typically 0.5 to 1.5 μm, and the length (width) of the Loff regions 511b and 512b. May be 1.0 to 3.5 μm, typically 1.5 to 2.0 μm. The length (width) of the Loff regions 517 to 520 provided in the pixel TFT 604 may be 0.5 to 3.5 μm, typically 2.0 to 2.5 μm.
[0113]
Further, in this embodiment, an alumina film having a high relative dielectric constant of 7 to 9 is used as the dielectric of the storage capacitor, so that the area occupied by the storage capacitor necessary for forming the necessary capacitance can be reduced. . Furthermore, by using the common electrode formed on the pixel TFT as one electrode of the storage capacitor as in this embodiment, the aperture ratio of the pixel portion of the liquid crystal display device can be improved.
[0114]
Here, a process of manufacturing an active matrix liquid crystal display device from an active matrix substrate will be described. As shown in FIG. 8, an alignment film 801 is formed on the substrate in the state of FIG. In this embodiment, a polyimide film is used as the alignment film. In addition, an alignment film 803 is formed over the counter substrate 802. Note that a color filter or a shielding film may be formed on the counter substrate as necessary.
[0115]
Next, after forming an alignment film, a rubbing process is performed to adjust the liquid crystal molecules so that they are aligned with a certain pretilt angle. Then, the pixel portion, the substrate on which the driver circuit is formed, and the counter substrate are attached to each other through a spacer 805 or the like by a known cell assembling process. However, the spacer 805 is preferably arranged so as to avoid a region where a storage capacitor is formed in order to prevent a short circuit from occurring when pressure is applied between the substrates. In addition, in order to keep the distance between the substrates uniform, the liquid crystal layer may be surrounded by a sealant 806 and a spacer may be formed in a region where the sealant 806 is formed. In the driver circuit, a spacer 805 is preferably provided in a region where no element of the driver circuit exists, and the spacer is formed in a region between the pixel portion where the pixel electrode is provided and the driver circuit. In addition, when the spacer 805 is formed over the contact portion of the pixel electrode 462 serving as a recess, the occurrence of disclination can be reduced.
[0116]
After that, liquid crystal 804 is injected between both substrates and completely sealed with a sealant 806. As the liquid crystal 804, a known n-type liquid crystal or p-type liquid crystal used in the IPS mode may be used. In this way, the liquid crystal display device shown in FIG. 8 is completed.
[0117]
Next, the configuration of the liquid crystal display device will be described with reference to the perspective view of FIG. The pixel portion 901, the scanning (gate) line driving circuit 902, and the signal (source) line driving circuit 903 are formed on the quartz substrate 401. The pixel TFT in the pixel portion is an n-channel TFT, and a driving circuit provided in the periphery is configured based on a CMOS circuit. The scan line driver circuit and the signal line driver circuit are connected to the pixel portion 901 through a gate wiring and a source wiring, respectively. In addition, connection wirings 906 and 907 from the external input / output terminal 905 to which the FPC 904 is connected to the input / output terminal of the driving circuit are provided.
[0118]
Next, an example of a circuit configuration of the liquid crystal display device illustrated in FIG. 9 is illustrated in FIG. The liquid crystal display device of this embodiment includes a signal line driver circuit 1001, a scan line driver circuit (A) 1007, a scan line driver circuit (B) 1011, a precharge circuit 1012, and a pixel portion 1006. Note that in this specification, a driver circuit includes a signal line driver circuit 1001, a scan line driver circuit (A) 1007, and a scan line driver circuit (B) 1011.
[0119]
The signal line driver circuit 1001 includes a shift register circuit 1002, a level shifter circuit 1003, a buffer circuit 1004, and a sampling circuit 1005. The scan line driver circuit (A) 1007 includes a shift register circuit 1008, a level shifter circuit 1009, and a buffer circuit 1010. The scanning line driver circuit (B) 1011 has a similar structure.
[0120]
Note that the configuration of this example can be easily realized by manufacturing a TFT in accordance with the steps shown in FIGS. In addition, in this embodiment, only the configuration of the pixel portion and the drive circuit is shown. However, according to the manufacturing process of this embodiment, a signal dividing circuit, a frequency divider circuit, a D / A converter circuit, an operational amplifier circuit, γ A signal processing circuit (also referred to as a logic circuit) such as a correction circuit or a microprocessor circuit can be formed over the same substrate.
[0121]
As described above, the present invention provides a semiconductor device including at least a pixel portion and a driving circuit for driving the pixel portion on the same substrate, for example, a signal processing circuit, a driving circuit, a pixel portion, and a storage capacitor on the same substrate. The provided semiconductor device can be realized.
[0122]
Further, when the steps up to FIG. 5B of this embodiment are performed, a crystalline silicon film having a unique crystal structure having continuity in the crystal lattice is formed. Hereinafter, an outline of the characteristics of the crystal structure experimentally investigated by the applicant will be described. This feature coincides with the feature of the semiconductor layer forming the active layer of the TFT completed by this embodiment.
[0123]
When viewed microscopically, the crystalline silicon film has a crystal structure in which a plurality of needle-like or rod-like crystals (hereinafter abbreviated as rod-like crystals) are gathered and arranged. This can be easily confirmed by observation with TEM (transmission electron microscopy).
[0124]
Further, when electron diffraction and X-ray (X-ray) diffraction are used, the surface of the crystalline silicon film (portion forming portion) has a {110} plane as the main orientation plane although the crystal axis includes some deviation. Can be confirmed. At this time, if analysis is performed by electron beam diffraction, it can be confirmed that diffraction spots corresponding to the {110} plane appear clearly. It can also be confirmed that each spot has a distribution on a concentric circle.
[0125]
Further, when a crystal grain boundary formed by contact of individual rod-like crystals is observed by HR-TEM (high resolution transmission electron microscopy), it can be confirmed that the crystal lattice has continuity at the crystal grain boundary. This can be easily confirmed because the observed lattice fringes are continuously connected at the grain boundaries.
[0126]
Note that the continuity of the crystal lattice at the crystal grain boundary results from the fact that the crystal grain boundary is a grain boundary called a “planar grain boundary”. The definition of the planar grain boundary in this specification is “Characterization of High-Efficiency Cast-Si Solar Cell Wafers by MBIC Measurement; Ryuichi Shimokawa and Yutaka Hayashi, Japanese Journal of Applied Physics vol.27, No.5, pp.751”. -758, 1988 ”is the“ Planar boundary ”.
[0127]
According to the above paper, planar grain boundaries include twin grain boundaries, special stacking faults, and special twist grain boundaries. This planar grain boundary is characterized by being electrically inactive. That is, although it is a crystal grain boundary, it does not function as a trap that inhibits the movement of carriers, and thus can be regarded as substantially nonexistent.
[0128]
In particular, when the crystal axis (axis perpendicular to the crystal plane) is the <110> axis, the {211} twin grain boundary is also referred to as the corresponding grain boundary of Σ3. The Σ value is a parameter that serves as a guideline indicating the degree of consistency of the corresponding grain boundary. It is known that the smaller the Σ value is, the better the grain boundary is.
[0129]
Actually, when the crystalline silicon film of this example is observed in detail using TEM, most of the crystal grain boundaries (90% or more, typically 95% or more) are the corresponding grain boundaries of Σ3, typically It turns out that it is a {211} twin grain boundary.
[0130]
In the crystal grain boundary formed between two crystal grains, when the plane orientation of both crystals is {110}, assuming that the angle formed by the lattice stripes corresponding to the {111} plane is θ, θ = 70.5 ° It is known that sometimes it becomes the corresponding grain boundary of Σ3. In the crystalline silicon film of the present example, each lattice fringe of adjacent crystal grains in the crystal grain boundary is continuous at an angle of about 70.5 °. Therefore, this crystal grain boundary is a corresponding grain boundary of Σ3. I can say that.
[0131]
In addition, when θ = 38.9 °, the corresponding grain boundary of Σ9 is obtained, but such other corresponding grain boundary also exists. In any case, it is still inactive.
[0132]
Such a corresponding grain boundary is formed only between crystal grains having the same plane orientation. That is, since the crystalline silicon film of this embodiment has a plane orientation of approximately {110}, such a corresponding grain boundary can be formed over a wide range.
[0133]
Such a crystal structure (exactly, the structure of the crystal grain boundary) indicates that two different crystal grains are joined with extremely good consistency at the crystal grain boundary. That is, the crystal lattice is continuously connected at the crystal grain boundary, and the trap level caused by crystal defects or the like is very difficult to create. Therefore, it can be considered that the semiconductor thin film having such a crystal structure is substantially free of crystal grain boundaries.
[0134]
Furthermore, it has been confirmed by TEM observation that defects present in the crystal grains have almost disappeared by a heat treatment step (corresponding to the thermal oxidation step in Example 1) at a high temperature of 800 to 1150 ° C. This is also clear from the fact that the number of defects is greatly reduced before and after this heat treatment step.
[0135]
The difference in the number of defects appears as a difference in spin density by electron spin resonance analysis (Electron Spin Resonance: ESR). At present, the spin density of the crystalline silicon film of this example is at least 5 × 10¹⁷spins / cm^ThreeBelow (preferably 3 × 10¹⁷spins / cm^ThreeThe following): However, since this measured value is close to the detection limit of existing measuring devices, the actual spin density is expected to be even lower.
[0136]
From the above, since the crystalline silicon film of this example has extremely few defects in crystal grains and it can be considered that there is substantially no crystal grain boundary, a single crystal silicon film or a substantially single crystal silicon film You can think about it.
[0137]
[Embodiment 2] In this embodiment, a case where the structure of a pixel portion is different from that in Embodiment 1 will be described with reference to FIG. Since the basic structure is the same as that of the pixel circuit shown in FIG. 1B, only the differences will be described. Accordingly, the same reference numerals are used for the same parts.
[0138]
FIG. 11A is a cross-sectional view of the pixel portion of this embodiment, which is an example in which a buffer layer 1101 is formed between an interlayer insulating film (organic resin film) and a common electrode. As the buffer layer 1101, an insulating film containing silicon with a thickness of 10 to 100 nm (preferably 30 to 50 nm) is used. However, since it is formed on the organic resin film, degassing from the resin film becomes a problem when exposed to vacuum. Therefore, it is preferable to use an insulating film that can be formed by sputtering.
[0139]
In this embodiment, a 50 nm thick silicon oxide film is used as the buffer layer 1101. By forming this buffer layer, the adhesion between the organic resin film and the common electrode is improved. When the oxide is formed by the anodic oxidation method as in Example 1, if the adhesion is poor, there is a problem that the anodic oxide is formed so as to sink into the interface between the organic resin film and the common electrode. However, such a problem can be prevented by adopting the structure of FIG.
[0140]
The structure of FIG. 11B is an example in which the basic structure is the same as that of FIG. 11A, but the buffer layer 1102 is formed in a self-aligned manner under the common electrode. In this case, the structure of FIG. 11B can be realized by etching the buffer layer in a self-aligning manner using the common electrode as a mask.
[0141]
The etching process may be performed immediately after the common electrode is formed or may be performed after the oxide film is formed. However, in the case where the material of the buffer layer 1102 and the material of the oxide film are etched with the same etchant, it is desirable to perform an etching process before forming the oxide film.
[0142]
Further, the structure of FIG. 11B is advantageous when a contact hole is opened in the third interlayer insulating film. If a silicon oxide film or the like is present on the organic resin film, the silicon oxide film may remain in an eaves shape when the organic resin film is etched. Therefore, it is preferable to remove the buffer layer in advance at the position where the contact hole is formed as in the structure of FIG.
[0143]
11C illustrates an example in which the spacers 1103a to 1103c made of insulating films are formed after the common electrode and the oxide film are formed, and then the pixel electrode 104 is formed. As a material for the spacers 1103a to 1103c, an organic resin film is preferable, and it is particularly preferable to use photosensitive polyimide or acrylic.
[0144]
With the structure as shown in FIG. 11C, the end (edge portion) of the common electrode is hidden by the spacer, so that the common electrode and the pixel electrode are short-circuited at the end of the common electrode. Can be prevented.
[0145]
The configuration of this example is the same as that of Example 1 except that the steps from the formation of the third interlayer insulating film to the formation of the pixel electrode are changed in the manufacturing process of Example 1. Therefore, the present invention can be applied to the liquid crystal display device shown in Embodiment 1.
[0146]
[Embodiment 3] In this embodiment, the case where the shape of the common electrode of the pixel portion is different from that of Embodiment 1 will be described with reference to FIGS. Since the basic structure is the same as that of the pixel portion shown in FIG. 1A, only the differences will be described. Accordingly, the same reference numerals are used for the same parts.
[0147]
In this embodiment, in order to set the common electrode to the common potential (intermediate potential of the image signal sent as data), the common electrode 1201 having a shape to which the common electrodes are connected is formed. Then, the common electrode 1201 can be held at the common potential by electrically connecting the common electrode 1201 and the power supply line for applying the common potential outside the pixel portion. Note that in the case where the common electrode 1201 is used, the separation process after anodization can be omitted, and thus the process can be simplified.
[0148]
Alternatively, the common electrode 1301 having a shape as illustrated in FIG. 13 may have a shape that completely covers the TFT and shields it from light and electromagnetic waves. Even in this case, since the dividing step after the anodic oxidation can be omitted, the step can be simplified.
[0149]
Note that the configuration of this example can be realized by only partially changing the manufacturing process (such as the common electrode pattern) of Example 1, and the other processes may be similar to those of Example 1. Therefore, the present invention can be applied to the liquid crystal display device shown in Embodiment 1. Further, it can be freely combined with the structure shown in the second embodiment.
[0150]
[Embodiment 4] In this embodiment, the case where the shape of the pixel electrode and the common electrode in the pixel portion is different from that in Embodiment 1 will be described with reference to FIGS. 14A and 14B. Since the basic structure is the same as that of the pixel portion shown in FIG. 1A, only the differences will be described. Accordingly, the same reference numerals are used for the same parts.
[0151]
As shown in FIG. 14A, a zigzag pixel electrode 1401 and a zigzag common electrode 1402 were formed. By doing so, two types of directions of the electric field applied to the liquid crystal were formed, and the display characteristics could be improved.
[0152]
Further, as shown in FIG. 14B, the shape of the source line is changed in accordance with the zigzag common electrode 1404 to obtain a source line 1403. By doing so, the aperture ratio could be improved. However, it is preferable to change the shape in consideration of the parasitic capacitance formed between the source line and the common electrode.
[0153]
Note that the configuration of this example can be realized by only partially changing the manufacturing process of Example 1, and the other processes may be similar to those of Example 1. Therefore, the present invention can be applied to the liquid crystal display device shown in Embodiment 1. Further, it can be freely combined with the structure shown in the second embodiment.
[0154]
[Embodiment 5] In this embodiment, the case where the shape of the pixel electrode and the common electrode in the pixel portion is different from that in Embodiment 1 will be described with reference to FIGS. Since the basic structure is the same as that of the pixel portion shown in FIG. 1A, only the differences will be described. Accordingly, the same reference numerals are used for the same parts.
[0155]
As shown in FIG. 15A, a “<”-shaped pixel electrode 1501 and a “<”-shaped common electrode 1502 were formed. By doing so, two types of directions of the electric field applied to the liquid crystal were formed, and the display characteristics could be improved.
[0156]
In addition, as illustrated in FIG. 15B, the shape of the source line was changed in accordance with the “-”-shaped common electrode 1504 to obtain a source line 1503. By doing so, the aperture ratio could be improved. However, it is preferable to change the shape in consideration of the parasitic capacitance formed between the source line and the common electrode.
[0157]
Note that the configuration of this example can be realized by only partially changing the manufacturing process of Example 1, and the other processes may be similar to those of Example 1. Therefore, the present invention can be applied to the liquid crystal display device shown in Embodiment 1. Further, it can be freely combined with the structure shown in the second embodiment.
[0158]
[Embodiment 6] In this embodiment, the case where the shape of the pixel electrode and the common electrode in the pixel portion is different from that in Embodiment 1 will be described with reference to FIG. Since the basic structure is the same as that of the pixel portion shown in FIG. 1A, only the differences will be described. Accordingly, the same reference numerals are used for the same parts.
[0159]
A pixel electrode 1601 having a shape as shown in FIG. 16A and a common electrode 1602 were formed. By doing so, three types of directions of the electric field applied to the liquid crystal were formed, and the display characteristics could be improved.
[0160]
In addition, the shape of the source line was changed in accordance with the common electrode 1604 having a shape as illustrated in FIG. By doing so, the aperture ratio could be improved. However, it is preferable to change the shape in consideration of the parasitic capacitance formed between the source line and the common electrode.
[0161]
Note that the configuration of this example can be realized by only partially changing the manufacturing process of Example 1, and the other processes may be similar to those of Example 1. Therefore, the present invention can be applied to the liquid crystal display device shown in Embodiment 1. Further, it can be freely combined with the structure shown in the second embodiment.
[0162]
[Example 7]
In this embodiment, another structure in the pixel portion will be described.
[0163]
In the present embodiment, the description will be given focusing only on the differences from the first embodiment.
[0164]
In this embodiment, a color filter colored with three primary colors of RGB is provided between a pixel TFT and a pixel electrode. The color arrangement of R, G, and B may be striped or mosaic.
[0165]
First, after forming the passivation film 458 according to the first embodiment, a color filter is formed thereon. The color filter 1601 also has a planarizing film function. Thereafter, at the same time as patterning the color filter, or after forming the color filter, an ITO contact opening is made in advance. Thereafter, a second interlayer insulating film is formed, and a light shielding layer is formed thereon. In the subsequent steps, a third interlayer insulating film made of an anodic oxide film and an organic resin film is formed using the same manufacturing method as in Example 1. Thereafter, the third interlayer insulating film, the second interlayer insulating film, and the passivation film 458 are etched to form a contact hole, and a pixel electrode is formed using the same material as in the first embodiment. The storage capacitor includes a shielding layer, an anodic oxide film, and a pixel electrode.
[0166]
Moreover, the structure of a present Example can be freely combined with any structure of Examples 1-6.
[0167]
[Example 8]
In this embodiment, the case where the present invention is used for a bottom gate type TFT will be described. Specifically, FIG. 18 shows a case where it is used for an inverted stagger type TFT. In the case of the inverted stagger type TFT of the present invention, the top gate type TFT of Example 1 is not particularly different except for the positional relationship between the gate wiring and the active layer. Therefore, in this embodiment, description will be made by paying attention to the point that is greatly different from the structure shown in FIG. 7B, and the other parts are the same as those in FIG. In the same manner as in the first embodiment, a storage capacitor including a shielding film, an anodic oxide film thereof, and a pixel electrode is formed. This anodic oxide film is formed by the method shown in the embodiment of the invention.
[0168]
In FIG. 18, 11 and 12 are p-channel TFTs and n-channel TFTs of CMOS circuits that form shift register circuits, respectively, 13 is an n-channel TFT that forms sampling circuits, and 14 is an n-channel TFT that forms a pixel portion. It is a channel type TFT. These are formed on a substrate provided with a base film.
[0169]
Further, 15 is a gate wiring of the p-channel TFT 11, 16 is a gate wiring of the n-channel TFT 12, 17 is a gate wiring of the n-channel TFT 13, and 18 is a gate wiring of the n-channel TFT 14, which is described in the first embodiment. It can be formed using the same material as the gate wiring. Reference numeral 19 denotes a gate insulating film, which can also use the same material as in the first embodiment.
[0170]
An active layer (active layer) of each of the TFTs 11 to 14 is formed thereon. A source region 20, a drain region 21, and a channel formation region 22 are formed in the active layer of the p-channel TFT 11.
[0171]
In the active layer of the n-channel TFT 12, a source region 23, a drain region 24, an LDD region (in this case, a Lov region 25), and a channel formation region 26 are formed.
[0172]
In the active layer of the n-channel TFT 13, a source region 27, a drain region 28, an LDD region (in this case, Lov regions 29a and 30a and Loff regions 29b and 30b), and a channel formation region 31 are formed.
[0173]
In the active layer of the n-channel TFT 14, a source region 32, a drain region 33, an LDD region (in this case, Loff regions 34 to 37), channel forming regions 38 and 39, and an n-type impurity region 40 are formed.
[0174]
The insulating films 41 to 45 are formed for the purpose of protecting the channel formation region and the purpose of forming the LDD region.
[0175]
As described above, it is easy to apply the present invention to a bottom gate type TFT represented by an inverted stagger type TFT. Note that in manufacturing the inverted staggered TFT of this embodiment, the manufacturing process shown in another embodiment described in this specification may be applied to a manufacturing process of a known inverted staggered TFT.
[0176]
Moreover, the structure of a present Example can be freely combined with any structure of Examples 1-7.
[0177]
[Example 9]
The pixel portion formed by implementing the present invention can be used in various electro-optical devices (active matrix liquid crystal displays). That is, the present invention can be implemented in all electronic devices in which these electro-optical devices are incorporated in the display unit.
[0178]
Such electronic devices include video cameras, digital cameras, projectors (rear or front type), head mounted displays (goggles type displays), car navigation systems, car stereos, personal computers, personal digital assistants (mobile computers, mobile phones) Or an electronic book). Examples of these are shown in FIGS. 19, 20 and 21. FIG.
[0179]
FIG. 19A illustrates a personal computer, which includes a main body 2001, an image input portion 2002, a display portion 2003, a keyboard 2004, and the like. The present invention can be applied to the display portion 2003.
[0180]
FIG. 19B illustrates a video camera, which includes a main body 2101, a display portion 2102, an audio input portion 2103, operation switches 2104, a battery 2105, an image receiving portion 2106, and the like. The present invention can be applied to the display portion 2102.
[0181]
FIG. 19C illustrates a mobile computer, which includes a main body 2201, a camera unit 2202, an image receiving unit 2203, operation switches 2204, a display unit 2205, and the like. The present invention can be applied to the display portion 2205.
[0182]
FIG. 19D shows a goggle type display, which includes a main body 2301, a display portion 2302, an arm portion 2303, and the like. The present invention can be applied to the display portion 2302.
[0183]
FIG. 19E shows a player using a recording medium (hereinafter referred to as a recording medium) on which a program is recorded, and includes a main body 2401, a display portion 2402, a speaker portion 2403, a recording medium 2404, an operation switch 2405, and the like. This player uses a DVD (Digital Versatile Disc), CD, or the like as a recording medium, and can perform music appreciation, movie appreciation, games, and the Internet. The present invention can be applied to the display portion 2402.
[0184]
FIG. 19F illustrates a digital camera, which includes a main body 2501, a display portion 2502, an eyepiece portion 2503, operation switches 2504, an image receiving portion (not shown), and the like. The present invention can be applied to the display portion 2502.
[0185]
FIG. 20A illustrates a front projector, which includes a projection device 2601, a screen 2602, and the like. The present invention can be applied to a liquid crystal display device 2808 that constitutes a part of the projection device 2601.
[0186]
FIG. 20B illustrates a rear projector, which includes a main body 2701, a projection device 2702, a mirror 2703, a screen 2704, and the like. The present invention can be applied to a liquid crystal display device 2808 that constitutes a part of the projection device 2702.
[0187]
20C is a diagram showing an example of the structure of the projection devices 2601 and 2702 in FIGS. 20A and 20B. The projection devices 2601 and 2702 include a light source optical system 2801, mirrors 2802 and 2804 to 2806, a dichroic mirror 2803, a prism 2807, a liquid crystal display device 2808, a phase difference plate 2809, and a projection optical system 2810. The projection optical system 2810 includes an optical system that includes a projection lens. Although the present embodiment shows an example of a three-plate type, it is not particularly limited, and for example, a single-plate type may be used. Further, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarization function, a film for adjusting a phase difference, or an IR film in the optical path indicated by an arrow in FIG. Good.
[0188]
FIG. 20D is a diagram illustrating an example of the structure of the light source optical system 2801 in FIG. In this embodiment, the light source optical system 2801 includes a reflector 2811, a light source 2812, lens arrays 2813 and 2814, a polarization conversion element 2815, and a condenser lens 2816. Note that the light source optical system illustrated in FIG. 20D is an example and is not particularly limited. For example, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarization function, a film for adjusting a phase difference, or an IR film in the light source optical system.
[0189]
FIG. 21A illustrates a mobile phone, which includes a main body 2901, an audio output portion 2902, an audio input portion 2903, a display portion 2904, operation switches 2905, an antenna 2906, and the like. The present invention can be applied to the display portion 2904.
[0190]
FIG. 21B illustrates a portable book (electronic book), which includes a main body 3001, display portions 3002 and 3003, a storage medium 3004, operation switches 3005, an antenna 3006, and the like. The present invention can be applied to the display portions 3002 and 3003.
[0191]
FIG. 21C illustrates a display which includes a main body 3101, a support base 3102, a display portion 3103, and the like. The present invention can be applied to the display portion 3103. The display of the present invention is particularly advantageous when the screen is enlarged, and is advantageous for displays having a diagonal of 10 inches or more (particularly 30 inches or more).
[0192]
As described above, the application range of the present invention is extremely wide and can be applied to electronic devices in various fields. Moreover, the electronic apparatus of a present Example is realizable even if it uses the structure which consists of what combination of Examples 1-7.
[0193]
【The invention's effect】
By using the invention of the present application, the surface of an electrode formed on an insulating film, particularly a resin film, used in each circuit of an electro-optical device typified by an IPS LCD is covered with the anodized film of the present invention. The amount of wraparound can be reduced, and a highly reliable liquid crystal display device having an electrode with excellent adhesion can be produced.
[0194]
In addition, a storage capacitor having a small area and a large capacity can be formed in a pixel portion of an electro-optical device typified by an IPS LCD. Therefore, even in an AM-LCD having a diagonal of 1 inch or less, a sufficient storage capacity can be secured without reducing the aperture ratio. In addition, since there is almost no amount of anodic oxide film, the coverage of the pixel electrode formed thereon can be improved and the yield can be improved.
[Brief description of the drawings]
FIG. 1 is a diagram illustrating an example of a top view and a cross-sectional view of a pixel portion according to the present invention.
FIG. 2 is an equivalent circuit diagram.
FIG. 3 is a diagram showing the relationship between voltage and current between electrodes in an anodic oxidation method.
FIG. 4 is a diagram showing a manufacturing process of an LCD.
FIGS. 5A and 5B are diagrams showing a manufacturing process of an LCD. FIGS.
6A and 6B are diagrams showing a manufacturing process of an LCD.
FIGS. 7A and 7B are diagrams illustrating a manufacturing process of an LCD. FIGS.
FIG. 8 is a cross-sectional structure diagram of a liquid crystal display device.
FIG. 9 is a diagram showing the appearance of an LCD.
FIG. 10 is a diagram showing a circuit of a liquid crystal display device.
FIG. 11 is a diagram illustrating an example of a configuration of a storage capacitor.
FIG. 12 illustrates an example of a top view of a pixel portion.
FIG. 13 is a diagram illustrating an example of a top view of a pixel portion.
FIG 14 illustrates an example of a top view of a pixel portion.
FIG 15 illustrates an example of a top view of a pixel portion.
FIG 16 illustrates an example of a top view of a pixel portion.
FIG. 17 is a graph showing absorbance characteristics of an aluminum film.
FIG. 18 illustrates an example of a structure of a TFT.
FIG 19 illustrates an example of an electronic device.
FIG. 20 illustrates an example of an electronic device.
FIG. 21 illustrates an example of an electronic device.

Claims (11)

A thin film transistor formed on a substrate;
An interlayer insulating film having a contact hole formed on the thin film transistor;
A pixel electrode electrically connected to the electrode of the thin film transistor through the contact hole;
A common electrode formed on and in contact with the interlayer insulating film;
An oxide film of the common electrode formed pinched in overlap between a portion of a part and the common electrode of the pixel electrode,
A liquid crystal layer formed on the thin film transistor, interlayer insulating film, pixel electrode, common electrode, and oxide film;
Consisting of at least
A liquid crystal display device, wherein a voltage is applied between the pixel electrode and the common electrode to change the orientation of the liquid crystal layer. A thin film transistor formed on a substrate;
An interlayer insulating film having a contact hole formed on the thin film transistor;
A pixel electrode electrically connected to the electrode of the thin film transistor through the contact hole;
A common electrode formed on and in contact with the interlayer insulating film;
An oxide film of the common electrode formed pinched in overlap between a portion of a part and the common electrode of the pixel electrode,
A liquid crystal layer formed on the thin film transistor, interlayer insulating film, pixel electrode, common electrode, and oxide film;
Consisting of at least
The pixel electrode and the common electrode have a zigzag shape,
A liquid crystal display device, wherein a voltage is applied between the pixel electrode and the common electrode to change the orientation of the liquid crystal layer. A thin film transistor formed on a substrate;
An interlayer insulating film having a contact hole formed on the thin film transistor;
A pixel electrode electrically connected to the electrode of the thin film transistor through the contact hole;
A common electrode formed on and in contact with the interlayer insulating film so as to surround the contact hole;
An oxide film of the common electrode formed pinched in overlap between a portion of a part and the common electrode of the pixel electrode,
A liquid crystal layer formed on the thin film transistor, interlayer insulating film, pixel electrode, common electrode, and oxide film;
Consisting of at least
A liquid crystal display device, wherein a voltage is applied between the pixel electrode and the common electrode to change the orientation of the liquid crystal layer. A thin film transistor formed on a substrate;
An interlayer insulating film having a contact hole formed on the thin film transistor;
A pixel electrode electrically connected to the electrode of the thin film transistor through the contact hole;
A common electrode formed on and in contact with the interlayer insulating film so as to surround the contact hole;
An oxide film of the common electrode formed pinched in overlap between a portion of a part and the common electrode of the pixel electrode,
A liquid crystal layer formed on the thin film transistor, interlayer insulating film, pixel electrode, common electrode, and oxide film;
Consisting of at least
The pixel electrode and the common electrode have a zigzag shape,
A liquid crystal display device, wherein a voltage is applied between the pixel electrode and the common electrode to change the orientation of the liquid crystal layer.   The liquid crystal display device according to claim 1, wherein the interlayer insulating film is a resin film. The thin film transistor includes a semiconductor film, a gate wiring, and a gate insulating film provided between the semiconductor film and the gate wiring,
The liquid crystal display device according to claim 1, wherein the gate wiring is formed by stacking a first conductive film and a second conductive film. The thin film transistor includes a semiconductor layer having at least one channel formation region, a gate insulating film formed on the semiconductor layer, and a gate electrode formed on the gate insulating film,
The liquid crystal display device according to claim 1, wherein the channel formation region of the thin film transistor and a part of the common electrode overlap each other.   8. The liquid crystal display device according to claim 1, wherein a spacer is disposed so as to avoid a region sandwiched between a part of the pixel electrode and a part of the common electrode. 9. . The common electrode is formed of aluminum, the liquid crystal display device according to any one of claims 1 to 8, wherein the oxide film is alumina film. The oxide film, a liquid crystal display device according to any one of claims 1 to 9, characterized in that at 20nm or more 100nm or less. An electronic apparatus, characterized in that a liquid crystal display device according to any one of claims 1 to 1 0.

Images