JP2000332249A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To efficiently make a crystal growth by a method wherein an active layer of thin film transistors is formed by use of a region where a crystal grows from a region where a catalytic element is introduced by heating. SOLUTION: On a surface forming thin film transistors of a substrate 1001, a semiconductor film 1002 containing an amorphous structure of a thickness 20 to 100 nm is formed by a low pressure thermal CVD method, etc. Next, a mask film 1003 composed of an insulation film containing silicon is formed on the amorphous silicon film 1002, and opening parts 1004a, 1004b are formed by patterning. A margin of 10 μm is taken from a region as an active layer, and a band-like first catalytic element introduced region is disposed. A second catalyst element introduced region is disposed so as to interpose a region to be the active layer. An embodiment appropriately determines an interval distance between the first catalytic element introduced region and the second catalytic element introduced region and a width of a catalytic element introduced region.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a circuit constituted by thin film transistors (hereinafter, referred to as TFTs) and a method for manufacturing the same. For example, the present invention relates to an electro-optical device typified by a liquid crystal display panel and an electronic device equipped with such an electro-optical device as a component.

[0002] In this specification, a semiconductor device generally refers to a device that can function by utilizing semiconductor characteristics, and an electro-optical device, a semiconductor circuit, and an electronic device are all semiconductor devices.

[0003]

2. Description of the Related Art In recent years, a technique of forming a thin film transistor (TFT) using a semiconductor thin film (having a thickness of several to several hundred nm) formed on a substrate having an insulating surface has attracted attention. Thin film transistors are widely applied to electronic devices such as ICs and electro-optical devices, and are particularly rapidly developed as switching elements for image display devices.

[0004] As a semiconductor thin film for forming an active layer of a TFT, an amorphous silicon film (typically, an amorphous silicon film) has been widely used so far. Films (typically polysilicon films) are becoming mainstream. As a technique for obtaining the crystalline silicon film, a method of forming an amorphous silicon film and then crystallizing the film by heat treatment or laser light irradiation is often used.

After the amorphous silicon film is formed, a catalytic element (eg, nickel) for promoting crystallization of the amorphous silicon film is introduced, and heat treatment is performed to obtain a crystalline silicon film. Techniques (JP-A-6-232059 and JP-A-7-321339) are disclosed. According to this technique, a uniform crystalline silicon film can be obtained in a short time.

However, a catalyst element for promoting crystallization of the amorphous silicon film often deteriorates the characteristics of the TFT. Therefore, after crystallization, the region where the catalyst element exists at a high concentration is removed by etching or the like.

Hereinafter, a crystallization technique using a catalyst element for promoting crystallization of an amorphous silicon film and a technique for removing a region where the catalyst element exists at a high concentration will be specifically described.

In FIG. 1, 101 is a silicon film, 10
Reference numeral 2 denotes a belt-like region on the silicon film surface (hereinafter, referred to as a catalyst element introduction region). Reference numeral 103 denotes a silicon oxide mask that covers the silicon film surface other than the catalytic element introduction region.
Note that the catalyst element is selectively introduced into the catalyst element introduction region 102 by using the silicon oxide mask 103.

First, the catalyst element is introduced into the catalyst element introduction region 102.
And a heat treatment is performed to grow a crystal from the catalyst element introduction region 102 in a direction parallel to the insulating surface and in a direction substantially perpendicular to the long side of the catalyst element introduction region 102. Note that reference numeral 104 indicates the direction of crystal growth.

The leading end of the crystal growth thus obtained is set at 10
5 is assumed. It is known that the catalyst element exists at a high concentration at the tip 105 of crystal growth. When a certain crystal growth distance is exceeded, a region in the silicon film 101 where the active layer of the TFT can be arranged is formed between the belt-shaped catalyst element introduction region 102 and the crystal growth tip 105 where the catalyst element exists at a high concentration. Is done.

Next, the TF is formed using a region sandwiched between the crystal growth tip 105 and the belt-like catalyst element introduction region 102.
When forming the active layer of T, other regions (including at least the crystal growth tip 105) where the catalytic element exists at a high concentration are removed by etching.

Conventionally, a catalyst element introduction region is formed such that a region to be an active layer of a TFT in a later step exists in a region sandwiched between a crystal growth front end portion 105 and a belt-like catalyst element introduction region 102. The arrangement of 102 was determined, and the heat treatment conditions for crystallization were determined.

[0013]

SUMMARY OF THE INVENTION An object of the invention disclosed in the present invention is to further shorten the heat treatment time required for crystal growth and simplify the process as compared with the prior art.

Another object of the present invention is to efficiently arrange a catalyst element introduction region in a small space with miniaturization and integration of circuits in recent years.

Conventionally, the catalyst element introduction region is arranged so that a region to be an active layer of a TFT in a later step is present in a region sandwiched between the tip of crystal growth and a belt-like catalyst element introduction region. Had to be determined. Further, even if the catalyst element is removed in a step after crystallization, it is difficult to completely remove the catalyst element, so it has been said that a minimum necessary amount may be introduced.

Therefore, one catalyst element introduction region is provided on one side with respect to a region to be an active layer of a TFT in a later step. The crystal growth rate at 570 ° C. when only one catalytic element introduction region (width w = 10 μm) was arranged was about 3 μm / hr.

The present inventors have paid attention to the fact that the crystal growth conditions largely depend on the width and the arrangement interval of the catalytic element introduction region, and have found a method for performing crystal growth more efficiently than in the prior art.

[0018]

According to the structure of the invention disclosed in this specification, a step of forming an amorphous silicon film and a step of selectively introducing a catalyst element for promoting crystallization into the amorphous silicon film are provided. Performing a crystal growth from a region in which the catalyst element is introduced by heat treatment, and forming an active layer of a TFT using the crystal-grown region. It is a manufacturing method.

In another aspect of the present invention, a step of forming an amorphous silicon film, a step of selectively introducing a catalytic element for promoting crystallization to the amorphous silicon film, and a heat treatment Crystal growing from the region where the catalytic element is introduced, removing or reducing the catalytic element present in the region where the crystal is grown, and using the region where the catalytic element is removed or reduced to activate the TFT. And a step of forming a layer.

In each of the above structures, the step of selectively introducing the catalyst element is performed using a mask having an opening exposing a part of the amorphous silicon film,
The method for manufacturing a semiconductor device, wherein the mask has a plurality of openings with the region where the crystal growth is performed interposed therebetween.

Further, in the above configuration, the opening portion may include:
An active layer of a TFT is formed between the crystal growth region and an end of the region where the crystal growth is performed.

In each of the above structures, the catalyst element for promoting crystallization is one or more selected from Ni, Fe, Co, Cu, Ge, and Pd.

In the present specification, a technique for efficiently growing a crystal by determining the arrangement of the catalytic element introduction region will be described below.

As shown in FIG. 2, the inventors of the present application have two catalytic element introduction regions 20 with one active layer 204 interposed therebetween.
An experiment was conducted in which crystallization was performed by arranging 1, 202.

If crystallization is performed in a state where a region 204 to be an active layer of the TFT is sandwiched between two catalytic element introduction regions 201 and 202 in a later step, the region from one catalyst element introduction region to the other catalyst element introduction region is changed. The crystals grow toward each other. Note that the region 204 to be the active layer of the TFT is
It is assumed that the catalyst element introduction region 201 is arranged such that there exists a region between the catalyst element introduction region 201 and the tip portion 205 of the crystal grown therefrom.

First, an amorphous silicon film having a thickness of 65 nm and a silicon oxide film having a thickness of 150 nm were stacked. Next, an opening reaching the amorphous silicon film was formed in the silicon oxide film in order to introduce the catalyst element into the catalyst element introduction regions 201 and 202. The strip-shaped region on the silicon film surface exposed by the opening is a catalyst element introduction region.

Next, nickel was introduced into the catalyst element introduction region using nickel as a catalyst element for promoting crystal growth and using a nickel acetate ethanol solution containing 10 ppm by weight of nickel element. Finally, 57
Heat treatment was performed at 0 ° C. to grow crystals.

In FIG. 2, the crystal growth speed in the crystal growth direction 203 (the direction from one catalyst element introduction region 201 to the other catalyst element introduction region 202) is v, 2
The distance between the two catalytic element introduction regions 201 and 202 is d. Further, the width of the catalyst element introduction regions 201 and 202 is set to w.
And Here, w = 10 μm and w = 3
Heat treatment for crystallization was performed for each of the cases where the thickness was set to 0 μm.

Under the above conditions, the crystal growth rate v is calculated from the value of the distance d between the regions sandwiched between the two catalytic element introduction regions.
3 is shown in FIG. As is clear from FIG. 3, the crystal growth rate v depends on the distance d, and the distance d
In the range of <400 μm, the crystal growth rate v decreases as the distance d increases. However, when the distance d exceeds 400 μm, the crystal growth rate v tends to be saturated. The value of the saturated crystal growth rate v is substantially equal to the crystal growth rate when only one catalytic element introduction region is arranged and crystallized.

As described above, the present inventors have found that the crystal growth conditions largely depend on the distance d between the two catalytic element introduction regions. Further, the catalyst element introduction region 2
The crystal growth rate in the direction from 02 to the catalyst element introduction region 201 also depends on the distance d.

Therefore, by arranging the two catalytic element introduction regions with the desired region interposed therebetween and reducing the distance d between the regions, the desired region can be efficiently crystallized in a short time. However, the spacing distance d is twice or more the crystal growth distance. In addition, the distance d is 400 μm>
d ≧ 2 × (the distance between the catalytic element introduction region 201 and the region 204 to be the active layer + the width of the region 204 to be the active layer in the crystal growth direction 203).

The crystal growth rate v increases as the width w of the catalytic element introduction region increases. Therefore, if the width w of the catalyst element introduction region is increased, crystallization can be performed efficiently and in a short time.

It should be noted that the relationship established between the crystal growth rate v and the spacing distance d did not change even when parameters such as heat treatment conditions were changed.

By using the relationship shown in FIG. 3 to determine the width w and the spacing d of the catalytic element introduction region necessary for crystallization of the region to be crystallized, the crystal growth speed v can be increased to shorten the region. Crystallization can be performed in a short time. Reducing the time required for crystal growth is very important for simplifying the process.

An example of a procedure for determining the width w and the distance d of the catalytic element introduction region will be described below.

For example, the same conditions as those described above for obtaining the relationship shown in FIG. 3 (the thickness of the amorphous silicon film is 65 nm, and the initial thickness of the silicon oxide film used as the catalyst element introduction mask is 150 n
m, a solution of nickel acetate ethanol containing 10 ppm by weight of nickel element is added and heat treatment is performed at 570 ° C.) to crystallize the amorphous silicon film.

It is also assumed that a desired region (here, a region to be an active layer of a TFT) is arranged as shown in FIG. In FIG. 4, regions 401 and 4 to be active layers
02 are arranged at intervals of 200 μm. The width of each of the regions 401 and 402 to be the active layers was set to 20 μm.

Here, the regions 401 and 40 to be active layers
The margin between 2 and the catalyst element introduction region is 10 μm. The margin from the tip of the crystal grown from one of the catalytic element introduction regions is set to 10 μm, and regions 401 and 402 to be active layers are arranged in a region sandwiched between the tips of the crystal. Therefore, the crystal growth distance for crystallizing the regions 401 and 402 to be active layers is 40 μm (10 μm + 20).
μm + 10 μm) or more.

When three catalytic element introduction regions 503, 504, and 505 having a width w of 10 μm are arranged as shown in FIG. 5, the distance d is 190 μm (200 μm).
−10 μm). Therefore, according to FIG.
It can be seen that the crystal growth rate at 90 μm is about 7 μm / hr, so the heat treatment time required for crystallization is 5.
It can be calculated as 7 hours.

As another example, consider a case where a desired region (here, a region to be an active layer of a TFT) is arranged as shown in FIG. In FIG. 6, regions 601 and 602 to be active layers are arranged at intervals of 500 μm. The widths of the regions 601 and 602 to be active layers are each 60 μm.

In this case, similarly, the width w is 10 μm.
When the calculation is performed assuming that m catalyst element introduction regions are arranged (d = 490 μm), the time required for crystallization is 27.8.
Time. It can be seen that the time required for crystallization is longer in the arrangement of FIG. 6 than in the arrangement of FIG. Therefore, in the case of FIG. 6, the width w of the catalytic element introduction region is set to 30 μm. The interval distance d = 470 μm, and FIG.
The time required for crystallization can be calculated as 11.4 hours. Further, when the width w is 30 μm or more, the heat treatment time can be further reduced.

It should be noted that the width w of the catalytic element introduction region is particularly 1 if the relationship between the crystal growth rate v and the distance d is obtained.
It is not limited to 0 μm or 30 μm. However, it is desirable that the width w of the catalytic element introduction region is determined according to the heat treatment conditions and the necessary crystal growth distance.

As described above, if FIG. 3 is used, it is possible to determine the arrangement of the catalytic element introduction region for obtaining a required crystal growth distance in a certain heat treatment time.

The present invention having the above configuration will be described in more detail with reference to the embodiments of the present invention described below.

[0045]

FIG. 8 shows an embodiment of the present invention.
This will be described with reference to FIGS. Here, a method for simultaneously manufacturing a pixel portion and a driver circuit for driving the pixel portion over the same substrate will be described. However, for the sake of simplicity, a part of the buffer circuit portion of the driving circuit is illustrated.

FIG. 8 is a diagram showing an end portion of the entire buffer circuit section, and two inverter circuits 801 and 80 are shown.
2 is arranged at the extreme end, and although not shown, similar circuits are periodically arranged at the bottom of the figure. Also, 805
Is a pattern of a crystalline silicon film, 806 is a gate line, 8
07, 808 and 809 are source lines.

First, an amorphous silicon film having a thickness of 65 nm and a silicon oxide film having a thickness of 150 nm were stacked. Next, an opening reaching the amorphous silicon film was formed in the silicon oxide film in order to introduce the catalyst element into the catalyst element introduction region. The strip-shaped region on the silicon film surface exposed by the opening is a catalyst element introduction region.

Next, nickel was used as a catalyst element to promote crystal growth, and nickel element was introduced into the catalyst element introduction region using a nickel acetate ethanol solution containing 10 ppm by weight of nickel element.

The width of each active layer is 60 μm. If the tip of the crystal growth is arranged on the active layer of the TFT, the characteristics are deteriorated. Therefore, in the present invention, a certain margin is provided between the tip of crystal growth and the active layer of the TFT. However, considering that the tip has a variation of about 1 μm in the deviation σ, preferably, the margin may be set to 2 μm or more. here,
The margin was set to 10 μm.

The crystal growth distance required to crystallize the region to be the active layer is 80 μm (10 μm + 60 μm + 1
0 μm) or more. Spacing distance d of catalyst element introduction region
Is (500-w) μm. From FIG. 3, when the width w of the catalytic element introduction region is w = 10 μm and d = 490 μm, the time required for crystallization is 27.8 hours. When the width w of the catalytic element introduction region is set to 10 μm, the crystallization time becomes long. Therefore, the width w of the catalyst element introduction region is set to 30.
μm. From FIG. 3, w = 30 μm and d = 470 μm
In this case, the time required for crystallization can be calculated as 12.4 hours. Therefore, a region in which a margin of 10 μm is added to a region to be an active layer in a heat treatment at 570 ° C. for 11.4 hours can be crystallized.

Therefore, as shown in FIG. 9, the catalyst element introduction regions 910 and 911 having a width of 30 μm are arranged. Note that FIG.
Used the same reference numerals used in FIG.

As described above, the arrangement of the catalytic element introduction region suitable for each element can be determined using the relationship shown in FIG.

In this way, the crystal growth rate is increased by adjusting the distance d between the two catalytic element introduction regions, and the crystalline silicon film crystallized in a short time is used for a TFT or a semiconductor part of another element. Complete the semiconductor device.

[0054]

[Embodiment 1] In this embodiment, an active matrix substrate in which a CMOS circuit which is a basic form of a driver circuit provided in the pixel portion and its periphery is formed simultaneously with reference to FIGS. The method for fabricating will be described.

In FIG. 10A, a glass substrate, a quartz substrate, or a silicon substrate is desirably used as the substrate 1001. In this embodiment, a quartz substrate was used. Alternatively, a substrate obtained by forming an insulating film on the surface of a metal substrate or a stainless steel substrate may be used as the substrate. In the case of the present embodiment, 80
Since heat resistance that can withstand a temperature of 0 ° C. or higher is required, any substrate may be used as long as it satisfies the heat resistance.

The surface of the substrate 1001 where the TFT is to be formed is 20 to 100 nm (preferably 40 to 80 nm).
A semiconductor film 1002 including an amorphous structure with a thickness of (nm) is formed by a low-pressure thermal CVD method, a plasma CVD method, or a sputtering method. In this embodiment, an amorphous silicon film having a thickness of 60 nm is formed. However, since a thermal oxidation step is performed later, this film thickness does not necessarily become the final film thickness of the active layer of the TFT.

The semiconductor film having an amorphous structure includes an amorphous semiconductor film and a microcrystalline semiconductor film, and further includes a compound semiconductor film having an amorphous structure such as an amorphous silicon germanium film. . Further, it is also effective to continuously form a base film and an amorphous silicon film on a substrate without exposing them to the atmosphere. By doing so, it becomes possible to prevent contamination of the substrate surface from affecting the amorphous silicon film, and it is possible to reduce the variation in characteristics of the TFT to be manufactured.

Next, a mask film 1003 made of an insulating film containing silicon (silicon) is formed on the amorphous silicon film 1002, and the openings 1004a and 1004a are formed by patterning.
4b is formed. The strip-shaped region on the amorphous silicon film surface exposed by the opening serves as a catalyst element introduction region for introducing a catalyst element that promotes crystallization in the next crystallization step. (FIG. 10A)

The position of the catalytic element introduction region becomes important in the subsequent crystallization step. Although not shown in this embodiment,
With a margin of 10 μm from the region to be the active layer, a belt-shaped first catalytic element introduction region (width w = 10 μm) was arranged. Then, the second catalytic element introduction region was arranged so as to sandwich the region to be the active layer. The practitioner may appropriately determine the distance d between the first catalyst element introduction region and the second catalyst element introduction region and the width w of the catalyst element introduction region using FIG. In this embodiment, d = 190 μm, w = 10 μm
And However, it is not necessary that the spacing distance d and the width w be the same, and the practitioner may appropriately determine the distance in consideration of the circuit arrangement.

Note that as the insulating film containing silicon, a silicon oxide film, a silicon nitride film, or a silicon nitride oxide film can be used. The silicon nitride oxide film is an insulating film containing silicon, nitrogen, and oxygen in predetermined amounts, and is an insulating film represented by SiOxNy. The silicon nitride oxide film is SiH ₄
, N ₂ O, and NH ₃ as source gases, and the nitrogen concentration contained is at least 25 atomic% and at least 50 atomic%.
It is better to be less than.

At the same time as the patterning of the mask film 1003, a marker pattern serving as a reference for a subsequent patterning step is formed. When the mask film 1003 is etched, the amorphous silicon film 1002 is also slightly etched, and this step can be used as a marker pattern later when the mask is aligned.

Next, a semiconductor film having a crystal structure is formed according to the technique described in Japanese Patent Application Laid-Open No. Hei 10-247735 (corresponding to US Application No. 09 / 034,041). The technology described in the publication discloses a catalyst element (nickel, cobalt, germanium, tin, lead, palladium, etc.) that promotes crystallization during crystallization of a semiconductor film having an amorphous structure.
Crystallization means using one or more elements selected from iron and copper).

Specifically, heat treatment is performed with the catalyst element held on the surface of the semiconductor film including the amorphous structure, and the semiconductor film including the amorphous structure is changed to a semiconductor film including the crystalline structure. It is to let. As the crystallization means, the technique described in Example 1 of JP-A-7-130652 may be used. In addition, a semiconductor film including a crystalline structure includes a so-called single crystal semiconductor film and a polycrystalline semiconductor film, and a semiconductor film including a crystal structure formed in the publication has a crystal grain boundary.

In this publication, a spin coat method is used to form a layer containing a catalytic element on a mask film.
Means for forming a thin film containing a catalytic element by a gas phase method such as a sputtering method or an evaporation method may be employed.

Although it depends on the amount of hydrogen contained, the amorphous silicon film is preferably subjected to a heat treatment at 400 to 550 ° C. for about one hour to crystallize after sufficient desorption of hydrogen. . In this case, the hydrogen content is preferably set to 5 atom% or less.

The crystallization step is first performed at 400 to 500 ° C. for 1 hour.
After performing a heat treatment process for about an hour to desorb hydrogen from the film, the heat treatment is performed at 500 to 650 ° C. (preferably 550 to 600
C.) for 6 to 16 hours (preferably 8 to 14 hours).

In the present embodiment, nickel was used as the catalyst element, and the width and position of the catalyst element introduction region were devised as described above. Thus, crystallization could be performed by heat treatment at 570 ° C. for 5.7 hours. As a result, the openings 1004a,
Crystallization progresses in a direction parallel to the substrate (direction indicated by an arrow) starting from the substrate 04b, and a semiconductor film (a crystalline silicon film in this embodiment) 1005a having a crystal structure in which macroscopic crystal growth directions are aligned. -1005d was formed. (FIG. 10
(B)) The boundary between 1005b and 1005c is a region where crystal growth collides, and nickel is present at a relatively high concentration.

Next, a gettering step of removing nickel used in the crystallization step from the crystalline silicon film is performed.
In this embodiment, a step of adding an element belonging to Group 15 (phosphorus in this embodiment) using the mask film 1003 formed earlier as a mask is performed, and the openings 1004a and 1004a are formed.
1 × 10 ¹⁹ to 1 × 1 on the crystalline silicon film exposed at 4b
Phosphorus-added regions (hereinafter, referred to as gettering regions) 1006a and 1006b containing phosphorus at a concentration of 0 ²⁰ atoms / cm ³ are formed. (FIG. 10 (C))

Next, at 450 to 650 ° C. in a nitrogen atmosphere.
(Preferably 500 to 550 ° C.) and a heat treatment step for 4 to 24 hours (preferably 6 to 12 hours) are performed. By this heat treatment step, nickel in the crystalline silicon film moves in the direction of the arrow, and is captured in the gettering regions 1006a and 1006b by the gettering action of phosphorus. That is, since nickel is removed from the crystalline silicon film, the concentration of nickel contained in the crystalline silicon films 1007a to 1007d after gettering is 1 × 10 ¹⁷ atms / cm ³ or less, preferably 1 × 10 ¹⁶ atms. / cm ³ .

Next, the mask film 1003 is removed, and a protective film 1008 is formed on the crystalline silicon films 1007a to 1007d in order to add impurities later. The protective film 1008 has a thickness of 100 to 200 nm (preferably 130 to 170 nm).
It is preferable to use a silicon nitride oxide film or a silicon oxide film with a thickness of This protective film 1008 has a meaning to prevent the crystalline silicon film from being directly exposed to plasma at the time of adding an impurity and to enable fine concentration control.

Then, a resist mask 1009 is formed thereon.
Is formed, and an impurity element imparting p-type conductivity (hereinafter referred to as a p-type impurity element) is added via the protective film 1008. p
As the type impurity element, an element belonging to Group 13 typically, typically, boron or gallium can be used. This step (called channel doping step)
This is a step for controlling the threshold voltage. Here, boron is added by an ion doping method in which diborane (B ₂ H ₆ ) is plasma-excited without mass separation. Of course, an ion implantation method for performing mass separation may be used.

By this step, 1 × 10 ¹⁵ to 1 × 10 ¹⁸ at
oms / cm ³ (typically 5 × 10 ^{16 to} 5 × 10 ¹⁷ atoms / c
Impurity regions 1010a and 1010b containing a p-type impurity element (boron in this embodiment) at a concentration of m ³ ) are formed. Note that in this specification, an impurity region containing a p-type impurity element (a region not containing phosphorus) within the above concentration range is defined as p
It is defined as a type impurity region (b). (FIG. 10 (D))

Next, the resist mask 1009 is removed,
The crystalline silicon film is patterned to form island-shaped semiconductor layers (hereinafter, referred to as active layers) 1011 to 1014. Although not shown, when the crystalline silicon film is etched, the substrate or a base film provided on the substrate is also slightly etched. Therefore, a trace of the arrangement of the catalyst element introduction region remains slightly.

The active layers 1011 to 1014 are formed of a crystalline silicon film having very good crystallinity by selectively introducing nickel and crystallizing the same. Specifically, it has a crystal structure in which rod-shaped or columnar crystals are arranged with a specific direction. Further, after crystallization, nickel is removed or reduced by the gettering action of phosphorus, and the concentration of the catalytic element remaining in the active layers 1011 to 1014 is 1 × 10 ¹⁷ atms / cm ³ or less, preferably 1 × 10 ¹⁷ atms / cm ³ or less.
It is 10 ¹⁶ atms / cm ³ . (FIG. 10E)

Further, the active layer 101 of the p-channel TFT
Reference numeral 1 denotes a region not containing an impurity element intentionally introduced, and active layers 1012 to 1014 of an n-channel TFT are p-type impurity regions (b). In this specification,
The active layers 1011 to 1014 in this state are all defined as being intrinsic or substantially intrinsic. That is, a region into which an impurity element is intentionally introduced to such an extent that the operation of the TFT is not hindered may be considered as a substantially intrinsic region.

Next, an insulating film containing silicon having a thickness of 10 to 100 nm is formed by a plasma CVD method or a sputtering method. In this embodiment, a 30-nm-thick silicon nitride oxide film is formed. As the insulating film containing silicon, another insulating film containing silicon may be used as a single layer or a stacked layer.

Next, at 800-1150 ° C. (preferably 9 ° C.)
A heat treatment step at a temperature of (00 to 1000 ° C.) for 15 minutes to 8 hours (preferably 30 minutes to 2 hours) is performed in an oxidizing atmosphere (thermal oxidation step). In this embodiment, a heat treatment process is performed at 950 ° C. for 80 minutes in an atmosphere in which 3% by volume of hydrogen chloride is added to an oxygen atmosphere. Note that boron added in the step of FIG. 10D is activated during this thermal oxidation step.
(FIG. 11A)

The oxidizing atmosphere may be a dry oxygen atmosphere or a wet oxygen atmosphere, but a dry oxygen atmosphere is suitable for reducing crystal defects in the semiconductor layer.
Further, in this embodiment, an atmosphere in which a halogen element is included in an oxygen atmosphere is used, but the atmosphere may be performed in a 100% oxygen atmosphere.

During this thermal oxidation step, an oxidation reaction also proceeds at the interface between the insulating film containing silicon and the active layers 1011 to 1014 thereunder. In consideration of this, the thickness of the gate insulating film 1015 finally formed is set to 50 to 2 in the present invention.
It is adjusted so as to be 00 nm (preferably 100 to 150 nm). In the thermal oxidation step of this embodiment, 25 nm of the 60 nm-thick active layer is oxidized to
The film thickness of 014 is 45 nm. Further, since a 50-nm-thick thermal oxide film is added to the 30-nm-thick silicon-containing insulating film, the final gate insulating film 1015 has a thickness of 110 n.
m.

Next, new resist masks 1016-1 are added.
019 is formed. Then, an impurity element imparting n-type (hereinafter, referred to as an n-type impurity element) is added to form impurity regions 1020 to 1022 exhibiting n-type. Note that n
As the type impurity element, an element belonging to Group 15 typically, typically, phosphorus or arsenic can be used.
(FIG. 11B)

The impurity regions 1020 to 1022 will be
N-channel type CMOS circuit and sampling circuit
In TFTs, there is no need to function as an LDD region.
It is a pure area. Note that the impurity region formed here
Is 2 × 10 n-type impurity elements ¹⁶~ 5 × 10¹⁹atoms / cm^Three
(Typically 5 × 10¹⁷~ 5 × 10¹⁸atoms / cm^Three) No
Included in degrees. In this specification, n-type is used in the above concentration range.
The impurity region containing the impurity element is referred to as an n-type impurity region (b).
Define.

Here, phosphorus is added at a concentration of 1 × 10 ¹⁸ atoms / cm ³ by an ion doping method in which phosphine (PH ₃ ) is plasma-excited without mass separation. Of course, an ion implantation method for performing mass separation may be used. In this step, phosphorus is added to the crystalline silicon film via the gate film 1015.

Next, at 600 to 1000 ° C. (preferably at 7 ° C.)
Heat treatment is performed in an inert atmosphere (at 00 to 800 ° C.) to activate the phosphorus added in the step of FIG. In this embodiment, heat treatment at 800 ° C. for one hour is performed in a nitrogen atmosphere. (FIG. 11 (C))

At this time, it is possible to repair the active layer and the interface between the active layer and the gate insulating film that have been damaged by the addition of phosphorus at the same time. In this activation step, furnace annealing using an electric heating furnace is preferable, but optical annealing such as lamp annealing or laser annealing may be used together.

By this step, n-type impurity region (b) 10
The boundary between 20 and 1022, that is, the n-type impurity region (b)
Around the intrinsic or substantially intrinsic region (of course,
The junction with the p-type impurity region (b) is clarified. This means that when the TFT is completed later,
This means that the LDD region and the channel forming region can form a very good junction.

Next, a conductive film to be a gate wiring is formed. Note that the gate wiring may be formed using a single-layer conductive film, but is preferably a stacked film such as two layers or three layers as necessary. In this embodiment, the first conductive film 1023 and the second
A stacked film including the conductive film 1024 is formed. (FIG. 11
(D))

Here, the first conductive film 1023 and the second conductive film 1
024, tantalum (Ta), titanium (Ti),
Molybdenum (Mo), tungsten (W), chromium (C
r), an element selected from silicon (Si), or a conductive film containing the above element as a main component (typically, a tantalum nitride film, a tungsten nitride film, a titanium nitride film), or an alloy film combining the above elements ( Typically, a Mo-W alloy film, a Mo-Ta alloy film, a tungsten silicide film, etc.)
Can be used.

The first conductive film 1023 has a thickness of 10 to 50 n.
m (preferably 20 to 30 nm).
24 is 200 to 400 nm (preferably 250 to 350 nm)
nm). In this embodiment, the first conductive film 102
3, a 50-nm-thick tungsten nitride (WN) film is used, and as the second conductive film 1024, a 350-nm-thick tungsten film is used. Although not shown, the first conductive film 1
It is effective to form a silicon film below 023 with a thickness of about 2 to 20 nm. This can improve the adhesion of the conductive film formed thereon and prevent oxidation.

It is also effective to use a tantalum nitride film as the first conductive film 1023 and a tantalum film as the second conductive film.

Next, the first conductive film 1023 and the second conductive film 1
024 are collectively etched to form gate wirings 1025 to 1028 having a thickness of 400 nm. At this time, the gate wirings 1026 and 1027 formed in the driver circuit are n
It is formed so as to overlap with part of the type impurity regions (b) 1020 to 1022 with the gate insulating film 1015 interposed therebetween. This overlapping portion will later become a Lov region. The gate wiring 1
Although 028a and 1028b appear to be two in cross section, they are actually formed from one continuous pattern.
(FIG. 11E)

Next, a resist mask 1029 is formed,
By adding a p-type impurity element (boron in this embodiment), impurity regions 1030 and 1031 containing boron at a high concentration are formed. In this embodiment, 3 × 10 ^{20 to} 3 × 10 ²¹ atoms / cm ³ (typically 5 × 10 ²⁰ ) by an ion doping method using diborane (B ₂ H ₆ ) (of course, an ion implantation method may be used). Boron is added at a concentration of about 1 × 10 ²¹ atoms / cm ³ ). In this specification, an impurity region containing a p-type impurity element in the above concentration range is defined as a p-type impurity region (a). (FIG. 12 (A))

Next, the resist mask 1029 is removed,
Resist masks 1032 to 1034 are formed so as to cover a region to be a gate wiring and a p-channel TFT. Then, an n-type impurity element (phosphorus in this embodiment) is added to form impurity regions 1035 to 1041 containing phosphorus at a high concentration. Also in this case, the ion doping method using phosphine (PH ₃ ) (of course, the ion implantation method may be used), and the phosphorus concentration in this region is 1 × 10 ²⁰ to 1
× 10 ²¹ atoms / cm ³ (typically 2 × 10 ^{20 to} 5 × 10
²¹ atoms / cm ³ ). (FIG. 12 (B))

In this specification, an impurity region containing an n-type impurity element in the above concentration range is defined as an n-type impurity region (a). The region where the impurity regions 1035 to 1041 are formed contains phosphorus or boron already added in the previous step, but phosphorus is added at a sufficiently high concentration. You do not need to consider the effect of phosphorus or boron. Therefore, in this specification, the impurity regions 1035 to 1041 may be referred to as n-type impurity regions (a).

Next, resist masks 1032 to 1034
Is removed, and a cap film 1042 made of an insulating film containing silicon is removed.
To form The film thickness is 25-100 nm (preferably 30
５０50 nm). In this embodiment, a silicon nitride film having a thickness of 25 nm is used. The cap film 1042 also functions as a protective film for preventing oxidation of the gate wiring in a later activation step. However, if the thickness is too large, stress is increased and problems such as film peeling occur.
It is preferable to set the following.

Next, an n-type impurity element (phosphorus in this embodiment) is added in a self-aligned manner using the gate wirings 1025 to 1028 as a mask. The impurity region 10 thus formed
43 to 1046 are １ ／ of the n-type impurity region (b).
Concentration of about 1/10 (typically 1/3 to 1/4) (provided that the concentration is 5 to 10 times higher than the boron concentration added in the channel doping step described above, typically 1 × 10 ^16). ~ 5
× 10 ¹⁸ atoms / cm ³ , typically 3 × 10 ^{17 to} 3 × 10
Adjust so that phosphorus is added at ¹⁸ atoms / cm ³ ).
In this specification, an impurity region containing an n-type impurity element in the above concentration range (excluding a p-type impurity region (a))
Is defined as an n-type impurity region (c). (FIG. 12 (C))

In this step, phosphorus is added through an insulating film having a thickness of 105 nm (a laminated film of the cap film 1042 and the gate insulating film 1015), but the cap film formed on the side walls of the gate wirings 1034a and 1034b is added. Also function as a mask. That is, an offset region having a length corresponding to the thickness of the cap film 1042 is formed. Note that the offset region refers to a high-resistance region which is formed in contact with the channel formation region and is formed of a semiconductor film having the same composition as the channel formation region, but does not form an inversion layer (channel region) because no gate voltage is applied. . In order to reduce the off-state current value, it is important to minimize the overlap between the LDD region and the gate wiring. In that sense, providing an offset region is effective.

When the p-type impurity element is also contained at a concentration of 1 × 10 ¹⁵ to 1 × 10 ¹⁸ atoms / cm ³ in the channel formation region as in this embodiment, the offset region also has the same concentration. Contains a p-type impurity element.

The length of the offset region depends on the thickness of the cap film actually formed on the side wall of the gate wiring and the sneak phenomenon when the impurity element is added (the phenomenon that the impurity is added so as to sunk under the mask). ), But L
From the viewpoint of suppressing the overlap between the DD region and the gate wiring, it is very effective to form a cap film in advance when forming the n-type impurity region (c) as in the present invention.

In this step, the mask was hidden by the gate wiring.
1 × 10 also in all impurity regions except the part¹⁶~ 5 × 1
0¹⁸atoms / cm^ThreePhosphorus is added at a concentration of
Low impurity concentration may affect the function of each impurity region.
Absent. Also, n-type impurity regions (b) 1043 to 1046
Already in the channel doping process¹⁵~ 1 × 10 ¹⁸
atoms / cm^ThreeConcentration of boron is added.
About 5 to 1 of boron contained in the p-type impurity region (b).
Since phosphorus is added at a concentration of 0 times, boron is also used in this case.
Does not affect the function of the n-type impurity region (b).
Good

However, strictly speaking, the n-type impurity region (b) 10
47 and 1048, the phosphorus concentration of the portion overlapping the gate wiring remains at 2 × 10 ^{16 to} 5 × 10 ¹⁹ atoms / cm ³ , while the portion not overlapping the gate wiring is 1 × 1
Phosphorus is added at a concentration of 0 ^{16 to} 5 × 10 ¹⁸ atoms / cm ³ , and contains phosphorus at a slightly higher concentration.

Next, a first interlayer insulating film 1049 is formed. The first interlayer insulating film 1049 may be formed using an insulating film containing silicon, specifically, a silicon nitride film, a silicon oxide film, a silicon nitride oxide film, or a stacked film obtained by combining them. Further, the film thickness may be 100 to 400 nm. In this embodiment, SiH ₄ ,
N ₂ O and NH ₃ are used as source gases, and a 200-nm-thick silicon nitride oxide film (nitrogen concentration is 25 to 50 atomic%) is used.

Thereafter, a heat treatment step was performed to activate the n-type or p-type impurity element added at each concentration. This step can be performed by furnace annealing, laser annealing, lamp annealing, or a combination thereof. When performing the furnace annealing method,
The heat treatment may be performed at 500 to 800C, preferably 550 to 600C in an inert atmosphere. In this embodiment, 600
A heat treatment is performed at 4 ° C. for 4 hours to activate the impurity element.
(FIG. 12 (D))

In this embodiment, the silicon nitride film 104 is used.
2 and the silicon nitride oxide film 1049 are stacked to cover the gate wiring, and the activation step is performed in that state.
In this embodiment, tungsten is used as a wiring material, but it is known that a tungsten film is very susceptible to oxidation. That is, even if it is covered with the protective film and oxidized, if the pinhole exists in the protective film, it is immediately oxidized. However, in this embodiment, a very effective silicon nitride film is used as an antioxidant film, and a silicon nitride oxide film is laminated on the silicon nitride film. It is possible to carry out the activation step at a high temperature without having to do so.

Next, after the activation step, heat treatment is performed at 300 to 450 ° C. for 1 to 4 hours in an atmosphere containing 3 to 100% hydrogen to hydrogenate the active layer. In this step, dangling bonds in the semiconductor layer are terminated by thermally excited hydrogen. Plasma hydrogenation (using hydrogen excited by plasma) as another means of hydrogenation
May be performed.

After the activation step, the first interlayer insulating film 1
A second interlayer insulating film 1050 having a thickness of 500 nm to 1.5 [mu] m is formed on 049. In this embodiment, the second interlayer insulating film 1
As 050, a silicon oxide film having a thickness of 800 nm is formed by a plasma CVD method. Thus, an interlayer insulating film having a thickness of 1 μm, which is a stacked film of the first interlayer insulating film (silicon oxynitride film) 1049 and the second interlayer insulating film (silicon oxide film) 1050, is formed.

If heat resistance is allowed in a later step, an organic resin film such as polyimide, acrylic, polyamide, polyimide amide, or BCB (benzocyclobutene) can be used as the second interlayer insulating film 1050. .

Thereafter, contact holes reaching the source region or the drain region of each TFT are formed, and the source wirings 1051 to 1054 and the drain wiring 1 are formed.
055 to 1057 are formed. In order to form a CMOS circuit, the drain wiring 1055 must be a p-channel type TF.
It is common between T and n-channel TFT. Although not shown, in this embodiment, this wiring is
200 nm film, 500n aluminum film containing Ti
A laminated film having a three-layer structure is formed by continuously forming an m and a Ti film of 100 nm by a sputtering method. (FIG. 13A)

Next, as the passivation film 1058, a silicon nitride film, a silicon oxide film, or a silicon oxynitride film is 50 to 500 nm (typically, 200 to 3 nm).
(00 nm). At this time, in this embodiment, a plasma treatment is performed using a gas containing hydrogen such as H ₂ and NH ₃ before forming the film, and a heat treatment is performed after the film is formed. Hydrogen excited by this pretreatment is supplied into the first and second interlayer insulating films. By performing the heat treatment in this state, the film quality of the passivation film 1058 is improved, and the hydrogen added to the first and second interlayer insulating films diffuses to the lower layer side, so that the active layer is effectively hydrogenated. be able to.

After the passivation film 1058 is formed, a hydrogenation step may be further performed. For example,
300 to 450 in an atmosphere containing 3 to 100% hydrogen.
The heat treatment is preferably performed at 1 ° C. for 1 to 12 hours, or the same effect can be obtained by using a plasma hydrogenation method. In addition,
An opening (not shown) may be formed in the passivation film 1058 at a position where a contact hole for connecting the pixel electrode and the drain wiring is formed after the hydrogenation step.

Thereafter, a third interlayer insulating film 1059 made of an organic resin is formed to a thickness of about 1 μm. As the organic resin, polyimide, acrylic, polyamide, polyimide amide, BCB (benzocyclobutene), or the like can be used. The advantages of using an organic resin film include that the film formation method is simple, the parasitic capacitance can be reduced because the relative dielectric constant is low, and the flatness is excellent. Note that an organic resin film or an organic SiO compound other than those described above can also be used. Here, it is formed by baking at 300 ° C. using a type of polyimide which is thermally polymerized after being applied to the substrate.

Next, a shielding film 1060 is formed on the third interlayer insulating film 1059 in a region to be a pixel portion. In this specification, the term “shielding film” is used to mean that light and electromagnetic waves are shielded. The shielding film 1060 is a film made of an element selected from aluminum (Al), titanium (Ti), and tantalum (Ta), or a film containing any one of the elements as a main component and having a thickness of 100 to 300 nm. In this embodiment, the aluminum film containing 1 wt% of titanium is 125 n
m.

If an insulating film such as a silicon oxide film is formed to a thickness of 5 to 50 nm on the third interlayer insulating film 1059, the adhesion of the shielding film formed thereon can be improved.
In addition, when plasma treatment using CF ₄ gas is performed on the surface of the third interlayer insulating film 1059 formed of an organic resin, the adhesion of a shielding film formed on the film can be improved by surface modification.

Further, it is possible to form not only a shielding film but also other connection wirings by using the aluminum film containing titanium. For example, connection wiring for connecting the circuits in the driver circuit can be formed. However, in this case, it is necessary to form a contact hole in the third interlayer insulating film before forming a material for forming the shielding film or the connection wiring.

Next, an oxide 1061 having a thickness of 20 to 100 nm (preferably 30 to 50 nm) is formed on the surface of the shielding film 1060 by an anodic oxidation method or a plasma oxidation method (in this embodiment, an anodic oxidation method). In this embodiment, the shielding film 1 is used.
Since a film mainly containing aluminum is used as 060, an aluminum oxide film (alumina film) is formed as the anodic oxide 1061.

At the time of this anodizing treatment, first, an ethylene glycol tartrate solution having a sufficiently low alkali ion concentration is prepared. This is a solution obtained by mixing a 15% aqueous solution of ammonium tartrate and ethylene glycol at a ratio of 2: 8, and ammonia water is added thereto to adjust the pH to 7 ± 0.5. Then, a platinum electrode serving as a cathode is provided in the solution, and the substrate on which the shielding film 1060 is formed is immersed in the solution.
A to several tens mA).

The voltage between the cathode and the anode in the solution changes with time as the anodic oxide grows, but the voltage is increased at a constant current of 100 V / min at a step-up rate to reach the ultimate voltage of 45 V. By the way, the anodizing treatment is terminated. In this way, the surface of the shielding film 1060 has a thickness of about 5
A 0 nm anodic oxide 1061 can be formed.
As a result, the thickness of the shielding film 1060 becomes 90 nm. It is to be noted that the numerical values relating to the anodic oxidation method shown here are merely examples, and the optimum values can naturally vary depending on the size of the element to be manufactured.

Although the insulating film is provided only on the surface of the shielding film by using the anodic oxidation method, the insulating film may be formed by a gas phase method such as a plasma CVD method, a thermal CVD method or a sputtering method. good. In this case, the film thickness is 20 to 1
It is preferably set to 00 nm (preferably 30 to 50 nm). In addition, silicon oxide film, silicon nitride film, silicon nitride oxide film, DLC (Diamond like carbon)
A film, a tantalum oxide film, or an organic resin film may be used.
Further, a stacked film combining these may be used.

Next, a contact hole reaching the drain wiring 1057 is formed in the third interlayer insulating film 1059 and the passivation film 1058, and a pixel electrode 1062 is formed. Note that the pixel electrode 1063 is a pixel electrode of another adjacent pixel. For the pixel electrodes 1062 and 1063, a transparent conductive film may be used for a transmissive liquid crystal display device, and a metal film may be used for a reflective liquid crystal display device. Here, in order to form a transmissive liquid crystal display device, an indium tin oxide (ITO) film is formed to a thickness of 110 nm by a sputtering method.

At this time, the pixel electrode 1062 and the shielding film 1060 overlap with each other via the anodic oxide 1061 to form a storage capacitance (capacitance striation) 1064. In addition,
In this case, it is desirable that the shielding film 1060 be set to a floating state (an electrically isolated state) or a fixed potential, preferably a common potential (an intermediate potential of an image signal transmitted as data).

Thus, an active matrix substrate having a driver circuit and a pixel portion on the same substrate was completed. In FIG. 13B, the driver circuit includes a p-channel TFT 1301 and an n-channel TFT 1
302 and 1303 are formed, and a pixel TFT 1304 formed of an n-channel TFT is formed in the pixel portion.

P-channel TFT 13 of Driver Circuit
01 includes a channel forming region 1201 and a source region 12
02, the drain region 1203 is formed of the p-type impurity region (a). However, strictly speaking, the source 1202 region and the drain region 1203 have 1 × 10 ^{16 to} 5 × 10 ¹⁸
Contains phosphorus at a concentration of atoms / cm ³ .

The n-channel type TFT 1302 includes:
Channel forming region 1204, source region 1205, drain
In region 1206, and channel formation region and drain
Between the gate wiring and the gate wiring through the gate insulating film.
(In this specification, such a region is referred to as a Lov region.)
Say. In addition, ov is attached with the meaning of overlap. ) 1207
Is formed. At this time, the Lov area 1207 is 2 × 10¹⁶
~ 5 × 10¹⁹atoms / cm ^ThreeContaining phosphorus at a concentration of
It is formed so as to completely overlap with the gate wiring.

The n-channel TFT 1303 includes:
LDD regions 1211 and 1212 are formed so as to sandwich the channel formation region 1208, the source region 1209, the drain region 1210, and the channel formation region. That is, an LDD region is formed between the source region and the channel formation region and between the drain region and the channel formation region.

In this structure, the LDD region 1211,
Since part of 1212 is arranged to overlap with the gate wiring, a region (Lov region) that overlaps with the gate wiring via the gate insulating film and a region that does not overlap with the gate wiring (such a region is referred to as a region in this specification). Loff area.
Is attached to the meaning of offset. ) Has been realized.

The length (width) of the Lov region 207 of the n-channel TFT 1302 for the channel length of 3 to 7 μm.
Is 0.3 to 3.0 μm, typically 0.5 to 1.5 μm
It is good. Further, the L of the n-channel TFT 1303
The length (width) of the ov region is 0.3 to 3.0 μm, typically 0.5 to 1.5 μm, and the length (width) of the Loff region is 1.0.
３3.5 μm, typically 1.5-2.0 μm. The length (width) of the Loff regions 1217 to 1220 provided in the pixel TFT 1304 is 0.5 to 3.5 μm.
m, typically 2.0 to 2.5 μm.

The present invention is not limited to the structure of the storage capacitor shown in this embodiment. For example, the present applicant has filed Japanese Patent Application No. 9-316567 and Japanese Patent Application No. 9-2732.
A storage capacitor having a structure described in Japanese Patent Application No. 44 or Japanese Patent Application No. 10-254097 can also be used.

Next, a process for manufacturing a liquid crystal display device from the above substrate will be described. As shown in FIG.
An alignment film 1401 is formed on the substrate on which the pixel portion and the driver circuit are formed in the state shown in FIG. In this embodiment, a polyimide film is used as an alignment film. In addition, the counter substrate 1
In 402, a transparent conductive film 1403 and an alignment film 1404 are formed. Note that a color filter and a shielding film may be formed on the counter substrate as needed.

Next, after forming the alignment film, a rubbing treatment is performed to adjust the liquid crystal molecules to have a certain pretilt angle. Then, the pixel portion, the substrate on which the driver circuit is formed, and the opposing substrate are bonded to each other via a sealing material, a spacer, or the like by a known cell assembly process. Thereafter, a liquid crystal 1405 is injected between the two substrates, and completely sealed with a sealant. A known liquid crystal material may be used for the liquid crystal. Thus, the liquid crystal display device shown in FIG. 14 is completed.

Next, the structure of this liquid crystal display device is shown in FIG.
This will be described with reference to a perspective view of FIG. In FIG. 15, common reference numerals are used to correspond to the cross-sectional structure diagram of FIG. A pixel portion 1501, a gate driver circuit 1502, and a source driver circuit 1503 are formed over a quartz substrate 1001. Pixel TFT 13 in the pixel section
Reference numeral 04 denotes an n-channel TFT, and a peripheral driver circuit is configured based on a CMOS circuit. The gate driver circuit 1502 and the source driver circuit 1503 are connected to the pixel portion 1501 through a gate wiring 1028 and a source wiring 1054, respectively.
The external input / output terminal 15 to which the FPC 1504 is connected
Connection wiring 1 from 05 to the input / output terminal of the driver circuit
506 and 1507 are provided.

Next, FIG. 16 shows an example of a circuit configuration of the liquid crystal display device shown in FIG. The liquid crystal display device according to this embodiment includes a source driver circuit 1601, a gate driver circuit (A) 1607, a gate driver circuit (B) 1611, a precharge circuit 1612, and a pixel unit 1.
606. Note that in this specification, a driver circuit includes an image signal processing circuit 1601 and a gate driver circuit 1607.

The source side driver circuit 1601 includes a shift register circuit 1602, a level shifter circuit 1603,
A buffer circuit 1604 and a sampling circuit 1605 are provided. Further, the gate side driver circuit (A) 160
7 includes a shift register circuit 1608, a level shifter circuit 1609, and a buffer circuit 1610. The gate side driver circuit (B) 1611 has the same configuration.

The structure of this embodiment can be easily realized by fabricating a TFT according to the steps shown in FIGS. In this embodiment, only the configuration of the pixel portion and the driver circuit is shown. However, according to the manufacturing process of the first embodiment, a signal division circuit, a frequency divider circuit, a D / A converter circuit, an operational amplifier circuit, γ A correction circuit and a signal processing circuit (also referred to as a logic circuit) such as a microprocessor circuit can be formed over the same substrate.

As described above, the present invention provides a semiconductor device including at least a pixel portion and a driver circuit for controlling the pixel portion on the same substrate, for example, a signal processing circuit, a driver circuit, and a pixel portion on the same substrate. A semiconductor device having the same can be realized.

[Embodiment 2] FIG. 11 in Embodiment 1
The crystal structure of the active layer that has undergone the steps up to the thermal oxidation step shown in FIG. The features will be described below.

The crystalline silicon film formed according to the manufacturing process of the first embodiment has a crystal structure in which a plurality of rod-shaped or column-shaped crystals are gathered and lined up microscopically. This is T
It was easily confirmed by observation by EM (transmission electron microscopy).

In addition, electron diffraction and X-ray (X-ray)
By using diffraction, it was confirmed that the surface of the active layer (portion where a channel is formed) had a {110} plane as a main orientation plane although the crystal axis contained some deviation. As a result of the applicant's detailed observation of an electron beam diffraction photograph with a spot diameter of about 1.5 μm, diffraction spots corresponding to the {110} plane clearly appear, but each spot has a distribution on a concentric circle. Was confirmed.

The applicant has observed, by HR-TEM (high resolution transmission electron microscopy), the grain boundaries formed by the contact of individual rod-shaped crystals, and found that the crystal lattices at the grain boundaries have continuity. It was confirmed. This was easily confirmed from the fact that the observed lattice fringes were continuously connected at the crystal grain boundaries.

The continuity of the crystal lattice at the crystal grain boundaries is caused by the fact that the crystal grain boundaries are grain boundaries called “planar grain boundaries”. The definition of the planar grain boundary in this specification is `` Characterization of High-Efficiency Cast-Si
Solar Cell Wafers by MBICMeasurement; Ryuichi Shi
mokawa and Yutaka Hayashi, Japanese Journal of Appl
ied Physics vol.27, No.5, pp.751-758, 1988 ".

According to the above-mentioned paper, the planar grain boundaries include twin grain boundaries, special stacking faults, special twist grain boundaries, and the like. This planar grain boundary is characterized by being electrically inactive. In other words, since it is a crystal grain boundary but does not function as a trap that hinders the movement of carriers, it can be considered that it does not substantially exist.

In particular, the crystal axis (the axis perpendicular to the crystal plane) is <11
In the case of the <0> axis, the {211} twin grain boundaries are also called corresponding grain boundaries of {3}. The Σ value is a parameter serving as a guideline indicating the degree of consistency of the corresponding grain boundaries, and it is known that the smaller the Σ value, the better the grain boundaries of consistency.

As a result of detailed observation of the crystalline silicon film obtained by carrying out the present example using a TEM, it was found that most of the crystal grain boundaries (90% or more, typically 95% or more) were observed. Σ
It was found to be the corresponding grain boundary of No. 3, ie, {211} twin grain boundary.

In a grain boundary formed between two crystal grains, when the plane orientation of both crystals is {110},
Assuming that the angle formed by the lattice fringes corresponding to the {111} plane is θ,
It is known that when θ = 70.5 °, the corresponding grain boundary becomes Σ3.

In the crystalline silicon film of this embodiment, the lattice fringes of adjacent crystal grains at the crystal grain boundaries are continuous at exactly an angle of about 70.5 °.
We arrived at the conclusion that it was a 1｝ twin grain boundary.

When θ = 38.9 °, a corresponding grain boundary of Σ9 is formed, but such other crystal grain boundaries also exist.

Such corresponding grain boundaries are formed only between crystal grains having the same plane orientation. That is, the crystalline silicon film obtained by carrying out this embodiment can form such a corresponding grain boundary over a wide range only because the plane orientation is substantially {110}.

Such a crystal structure (accurately, a structure of a crystal grain boundary) indicates that two different crystal grains are bonded to each other with extremely high consistency at the crystal grain boundary. That is, the crystal lattice is continuously connected at the crystal grain boundary, and it is very difficult to form a trap level due to a crystal defect or the like. Therefore, a crystalline silicon film having such a crystal structure can be regarded as having substantially no crystal grain boundaries.

Further, it was confirmed by TEM observation that defects existing in the crystal grains were almost completely eliminated by the heat treatment step (which corresponds to the thermal oxidation step or the gettering step in this embodiment) at a high temperature of 700 to 1150 ° C. Has been confirmed. This is apparent from the fact that the number of defects is significantly reduced before and after this heat treatment step.

The difference in the number of defects was determined by electron spin resonance analysis (El
ectron Spin Resonance (ESR) appears as a difference in spin density. At least 5 × 10 ¹⁷ spins / cm ³ or less in the present circumstances the spin density of the crystalline silicon film produced in accordance with the manufacturing steps of the present example (preferably 3 × 10 ¹⁷ spins
/ cm ³ or less). However, since this measured value is close to the detection limit of existing measuring devices, the actual spin density is expected to be lower.

As described above, since the crystalline silicon film obtained by carrying out this embodiment has substantially no inside of the crystal grain and no crystal grain boundary, the single crystal silicon film or the substantially single crystal silicon Think of it as a membrane. The present applicant has proposed a crystalline silicon film having such a crystal structure as CGS (Continuou).
s Grain Silicon).

Descriptions on CGS are described in Japanese Patent Application Nos. 10-044659 and 10-152316 by the present applicant.
No., Japanese Patent Application No. 10-152308 or Japanese Patent Application No. 10-1
No. 52305 may be referred to.

(Knowledge Regarding Electrical Characteristics of TFT) The TFT using the active layer of this example exhibited electrical characteristics comparable to those of the MOSFET. TFT prototyped by the applicant (however,
The thickness of the active layer is 30 nm, and the thickness of the gate insulating film is 100 n.
The following data is obtained from m).

(1) The sub-threshold coefficient which is an index of the switching performance (the agility of switching on / off operation) is 60 to 100 mV / decade (typically 60 to 85 mV) for both the N-channel TFT and the P-channel TFT. / decade)
And small. (2) The field effect mobility (μ _FE ) as an index of the operation speed of the TFT is 200 to 650 cm ² / Vs for the N-channel TFT.
(Typically 300-500cm ² / Vs), P-channel type TFT
In (typically ^{150~200cm 2 / Vs) 100~300cm 2 /} Vs greater the. (3) The threshold voltage (V
_th ) is as small as -0.5 to 1.5 V for an N-channel TFT and -1.5 to 0.5 V for a P-channel TFT.

As described above, it has been confirmed that extremely excellent switching characteristics and high-speed operation characteristics can be realized. Note that the configuration of this embodiment can be freely combined with the configuration of the first embodiment or the second embodiment.
However, it is important to use a catalyst element that promotes crystallization as described in Example 1 or Example 2 for crystallization of the amorphous semiconductor film.

[Embodiment 3] The present invention relates to a conventional MOSFET.
It is also possible to form an interlayer insulating film thereon and use it when forming a TFT thereon. That is, it is possible to realize a semiconductor device having a three-dimensional structure. In addition, S
An SOI substrate such as IMOX, Smart-Cut (registered trademark of SOITEC), ELTRAN (registered trademark of Canon Inc.) can also be used.

The structure of the present embodiment can be combined with the structure of the first embodiment.

[Embodiment 4] Various liquid crystal materials can be used for a liquid crystal display device manufactured according to the present invention. Such materials include TN liquid crystal, PDLC (polymer dispersed liquid crystal), FLC (ferroelectric liquid crystal), AFLC
(An anti-strongly inducing electro-liquid crystal), or a mixture of FLC and AFLC.

For example, “H. Furue et al .; Charakteristi
cs and Drivng Scheme of Polymer-Stabilized Monosta
ble FLCD Exhibiting Fast Response Time and High Co
ntrast Ratio with Gray-Scale Capability, SID, 199
8 "," T. Yoshida et al .; A Full-Color Thresholdless "
Antiferroelectric LCD Exhibiting Wide Viewing Ang
le with Fast Response Time, 841, SID97DIGEST, 199
7 ", or the materials disclosed in US Pat. No. 5,594,569.

In particular, a thresholdless (non-threshold) antiferroelectric liquid crystal (Thresholdless Antiferroelectric LCD:
TL-AFLC) can be used to reduce the operating voltage of the liquid crystal to about ± 2.5 V.
In some cases, about 8 V may be enough. That is, the driver circuit and the pixel matrix circuit can be operated at the same power supply voltage, and the power consumption of the entire liquid crystal display device can be reduced.

Further, ferroelectric liquid crystals and antiferroelectric liquid crystals are
There is an advantage that the response speed is faster than that of the N liquid crystal. Since the crystalline TFT used in the above embodiment can realize a TFT having a very high operation speed, a high image response speed utilizing the high response speed of the ferroelectric liquid crystal or the antiferroelectric liquid crystal can be realized. It is possible to realize a liquid crystal display device.

It is needless to say that it is effective to use the liquid crystal display device of this embodiment as a display for electronic equipment such as a personal computer.

The structure of this embodiment can be freely combined with any of the structures of Embodiment 1 and Embodiment 3.

Embodiment 5 A CMOS circuit and a pixel matrix circuit formed by carrying out the present invention are used for various electro-optical devices (active matrix liquid crystal display, active matrix EL display, active matrix EC display). be able to. That is, the invention of the present application can be applied to all electronic devices incorporating such electro-optical devices as display media.

Such electronic devices include a video camera, a digital camera, a projector (rear or front type), a head mounted display (goggle type display), a car navigation, a personal computer, and a portable information terminal (mobile computer, mobile phone). Or an electronic book). Examples of these are shown in FIGS.

FIG. 17A shows a personal computer, which includes a main body 2001, an image input section 2002, and a display device 2.
003 and a keyboard 2004. The present invention can be applied to the image input unit 2002, the display device 2003, and other signal control circuits.

FIG. 17B shows a video camera, which includes a main body 2101, a display device 2102, an audio input unit 2103, an operation switch 2104, a battery 2105, and an image receiving unit 21.
06. The present invention can be applied to the display device 2102, the audio input unit 2103, and other signal control circuits.

FIG. 17C shows a mobile computer (mobile computer), which comprises a main body 2201, a camera section 2202, an image receiving section 2203, operation switches 2204, and a display device 2205. The present invention relates to a display device 22.
05 and other signal control circuits.

FIG. 17D shows a goggle type display, which includes a main body 2301, a display device 2302, and an arm 23.
03. The present invention can be applied to the display device 2302 and other signal control circuits.

FIG. 17E shows a player that uses a recording medium (hereinafter, referred to as a recording medium) on which a program is recorded, and includes a main body 2401, a display device 2402, and a speaker unit 24.
03, a recording medium 2404, and operation switches 2405. This device uses a DVD (Di) as a recording medium.
It is possible to watch music, watch a movie, play a game, or use the Internet by using a CD (g. Versatile Disc) or a CD. The present invention can be applied to the display device 2402 and other signal control circuits.

FIG. 17F shows a digital camera, which comprises a main body 2501, a display device 2502, an eyepiece unit 2503, operation switches 2504, and an image receiving unit (not shown). The present invention can be applied to the display device 2502 and other signal control circuits.

FIG. 18A shows a front type projector, which comprises a display device 2601 and a screen 2602. The present invention can be applied to a display device and other signal control circuits.

FIG. 18B shows a rear type projector, which includes a main body 2701, a display device 2702, and a mirror 270.
3. It is composed of a screen 2704. The present invention can be applied to a display device and other signal control circuits.

FIG. 18C is a diagram showing an example of the structure of the display devices 2601 and 2702 in FIGS. 18A and 18B. Display devices 2601, 27
02 denotes a light source optical system 2801, mirrors 2802, 280
4 to 2806, dichroic mirror 2803, prism 2807, liquid crystal display device 2808, retardation plate 280
9. The projection optical system 2810. Projection optical system 28
Reference numeral 10 denotes an optical system including a projection lens. In the present embodiment, an example of a three-plate type is shown, but there is no particular limitation, and for example, a single-plate type may be used. In addition, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarizing function, a film for adjusting a phase difference, and an IR film in an optical path indicated by an arrow in FIG. Good.

FIG. 18D is a diagram showing an example of the structure of the light source optical system 2801 in FIG. 18C. In this embodiment, the light source optical system 2801 includes a reflector 2811, light sources 2812, 2813, 2814, a polarization conversion element 2815, and a condenser lens 2816.
Note that the light source optical system shown in FIG. 18D is an example and is not particularly limited. For example, a practitioner may appropriately provide an optical system such as an optical lens, a film having a polarizing function, a film for adjusting a phase difference, and an IR film in the light source optical system.

As described above, the applicable range of the present invention is extremely wide, and can be applied to electronic devices in all fields. Further, the electronic apparatus according to the present embodiment can be realized by using a configuration including any combination of the first to fourth embodiments.

[0175]

According to the technique presented in the present invention, it is possible to increase the crystal growth rate, shorten the heat treatment time required for the crystallization step, and manufacture a TFT having excellent electric characteristics.

Further, using the technique presented in the present invention,
By optimizing the width and arrangement of the catalyst element introduction region, it is possible to efficiently arrange the catalyst element introduction region in a small space, and achieve miniaturization and integration of a circuit.

[Brief description of the drawings]

FIG. 1 is a view showing crystal growth from a catalytic element introduction region.

FIG. 2 is a diagram showing an example of an arrangement of a catalyst element introduction region.

FIG. 3 is a diagram showing a relationship between an interval distance d and a crystal growth rate v.

FIG. 4 is a diagram showing an example of an arrangement of a region to be an active layer.

FIG. 5 is a diagram showing an example of an arrangement of a catalytic element introduction region and an arrangement of an active layer region.

FIG. 6 is a diagram showing an example of an arrangement of a region to be an active layer.

FIG. 7 is a diagram showing an example of an arrangement of a catalyst element introduction region and an arrangement of a region to be an active layer.

FIG. 8 is a top view of an element having a TFT.

FIG. 9 is a diagram showing an example of an arrangement of a device having a TFT and a catalyst element introduction region.

FIG. 10 illustrates a manufacturing process.

FIG. 11 illustrates a manufacturing process.

FIG. 12 illustrates a manufacturing process.

FIG. 13 illustrates a manufacturing process.

FIG. 14 is a sectional structural view of a liquid crystal display device.

FIG. 15 is a diagram showing an appearance of an AM-LCD.

FIG. 16 illustrates a peripheral circuit.

FIG. 17 illustrates an example of an electronic device.

FIG. 18 illustrates an example of an electronic device.

 ──────────────────────────────────────────────────続 き Continuing on the front page F term (reference) HJ01 HJ04 HJ13 HJ22 HJ23 HL03 HL04 HL06 HL12 HL23 HM14 HM15 NN02 NN03 NN04 NN22 NN23 NN24 NN35 NN36 NN44 NN46 NN47 PP23 PP34 PP35 QQ23 QQ24 QQ25 QQ28

Claims (5)

[Claims] 1. A step of forming an amorphous silicon film, a step of selectively introducing a catalytic element for promoting crystallization to the amorphous silicon film, and a region where the catalytic element is introduced by a heat treatment. And a step of forming an active layer of a TFT using the crystal-grown region. 2. A step of forming an amorphous silicon film, a step of selectively introducing a catalytic element for promoting crystallization to the amorphous silicon film, and a region where the catalytic element is introduced by heat treatment. A step of removing or reducing the catalyst element present in the region where the crystal has been grown, and a step of forming an active layer of the TFT using the region where the catalyst element has been removed or reduced. A method for manufacturing a semiconductor device, comprising: 3. The method according to claim 1, wherein the step of selectively introducing the catalyst element is performed using a mask having an opening exposing a part of the amorphous silicon film, The method for manufacturing a semiconductor device, wherein the mask has a plurality of openings with the region where the crystal growth is performed interposed therebetween. 4. The method of manufacturing a semiconductor device according to claim 3, wherein an active layer of a TFT is formed between the opening and an end of the region where the crystal growth is performed. 5. The catalyst element according to claim 1, wherein the catalyst element for promoting crystallization is Ni, Fe, Co, C
A method for manufacturing a semiconductor device, wherein the method is one or more types selected from u, Ge, and Pd.