JP2006279020A - Semiconductor device and method of manufacturing same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve driving capability and breakdown voltage of a high-breakdown-voltage MOSFET. <P>SOLUTION: A P-type second drain region 6 is formed in an N-type well region 4 formed in a P-type semiconductor substrate 2. A LOCOS oxide film 8 is formed on the second drain region 6, and a P-type third drain region 10 having a P-type impurity concentration higher than that of the P-type second drain region 6 is formed in a region underneath the LOCOS oxide film 8a. A gate oxide film 12 is formed on the surface of the N-type well region 4, extending continuously to the LOCOS oxide film 8a. A gate electrode 14 is formed on the gate oxide film 12, extending over the LOCOS oxide film 8a. A P-type first drain region 16 is formed in the surface vicinity of the P-type second drain region 6 keeping a space from the gate electrode 14. The P-type first drain region 16 has a P-type impurity concentration higher than those of the P-type second drain region 6 and the P-type third drain region 10. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device including a high voltage MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and a manufacturing method thereof.

For example, a semiconductor integrated circuit having a charge control function for a mobile phone is normally driven at a voltage of 5 to 6 V (volt), and the rating is set to about 8 V. However, a voltage exceeding the normal rating, for example, 12V to 18V may be applied to the internal circuit by being connected to a defective charging adapter. As a semiconductor integrated circuit, it is desirable that the internal circuit operates normally without causing defects such as heat generation or failure even when the above-described problems occur.
Also, display devices such as liquid crystals are required to operate at a high voltage band of about 15 V and with a large current drive capability. That is, the higher breakdown voltage and higher current of transistors support the recent development of mobile phones and digital communication devices.

  There are various means for raising the rating of the MOSFET, and one of them is a method of forming a thick oxide film under the gate oxide film on the drain side and forming a second drain region under the thick oxide film. ing. A MOSFET in which a thick oxide film is formed of a local oxidation of silicon (LOCOS) oxide film for element isolation is called a LOCOS offset transistor.

  When forming a LOCOS offset transistor, increasing the rating and increasing the driving capability are in a conflicting relationship. The reason for this is that when the concentration of the second drain region is increased, the concentration of the electric field becomes remarkable in the vicinity of the gate insulating film, and the breakdown voltage between the drain and the semiconductor substrate decreases. In addition, since the extension of the depletion layer between the second drain region and the semiconductor substrate is suppressed, the breakdown voltage between the semiconductor substrates is reduced. On the contrary, when the concentration of the second drain region is lowered, the parasitic resistance of the drain is increased and the driving capability is lowered. Therefore, the structure of the second drain region is the key to realizing both at a higher level.

  As a first conventional example, there is a MOSFET having a structure shown in FIG. 15 (see, for example, Patent Document 1). In this MOSFET, a medium concentration P + drain region 86 and a low concentration P− drain region 88 are formed between a high concentration P ++ drain region 82 and a gate oxide film 84 provided on the surface side of the N-type semiconductor substrate 80. ing. The P + drain region 86 is formed under the thick LOCOS oxide film 90, and the P− drain region 88 is disposed under the gate oxide film 84.

However, the structure shown in FIG. 15 has a problem that since the high-concentration P ++ drain region 82 is in direct contact with the N-type semiconductor substrate 80, the extension of the depletion layer is suppressed and junction breakdown occurs at a low voltage. It was. Further, Patent Document 1 discloses a structure in which a P− drain region is separately provided under the P ++ drain region 82, but even in this case, the medium concentration P + drain region 86 is in direct contact with the N-type semiconductor substrate 80. Therefore, a sufficiently high breakdown voltage cannot be achieved for the same reason.
In Patent Document 1, since the P-drain region 88 is formed at a position in contact with the gate oxide film 84 after the LOCOS oxide film 90 is formed, the P-drain region 88 and the gate oxide film 84 are in contact with each other. There is a problem that the electric field relaxation in the vicinity of the region is suppressed, the extension of the depletion layer is restricted, and gate modulation junction breakdown occurs at a low drain voltage.

  Further, as a second conventional example, there is a MOSFET having a structure shown in FIG. 16 (see, for example, Patent Document 1). In this MOSFET, a high-concentration thick LOCOS oxide film 90 is formed on the channel region side of the first drain region 92, and a high-concentration shallow second drain region 94 is formed immediately below the LOCOS oxide film 90. Further, a deep third drain region 96 having a low concentration is formed so as to surround the second drain region 94.

However, since impurities for the second drain region 94 having a high concentration and shallowness are introduced immediately below the LOCOS oxide film 90 before the LOCOS oxide film 90 is formed, ions can be sucked into the LOCOS oxide film 90, or oxidized. There is a problem in that the driving ability is easily affected by process fluctuations because the film is easily influenced by segregation of ions to the film-semiconductor substrate interface.
Further, since the high-concentration and shallow second drain region 94 is formed in the vicinity of the gate oxide film 84, the electric field between the gate and the drain is strengthened, and the breakdown voltage of the gate oxide film 84 is lowered.
Furthermore, since the first drain region 90 is in direct contact with the P-type semiconductor substrate at a high concentration, there is a problem in that the extension of the depletion layer is suppressed and junction breakdown occurs at a low drain voltage.

JP-A-6-21445 Japanese Patent No. 2668713

  An object of the present invention is to provide a semiconductor device capable of improving the driving capability and the breakdown voltage of a high breakdown voltage MOSFET and a method for manufacturing the same.

A semiconductor device according to the present invention includes a source region and a drain region of a second conductivity type that are formed in a well region of a first conductivity type with a space between each other, a channel region formed between the source region and the drain region, A gate insulating film formed on the channel region, a thick oxide film formed on the drain region adjacent to the gate insulating film and having a thickness greater than the gate insulating film, and the gate A high breakdown voltage MOSFET having a gate electrode formed over the insulating film and the thick oxide film, wherein the drain region includes a first drain region formed at a distance from the gate electrode, and the first drain A second drain region formed in a region covering at least the region under the thick oxide film and at least a lower portion covered with the second drain region. And a third drain region formed in a region including at least under the thick oxide film, wherein the first drain region has a second conductivity type impurity concentration higher than that of the third drain region, and The third drain region has a second conductivity type impurity concentration higher than that of the second drain region.
Here, the first conductivity type means P type or N type, and the second conductivity type means N type or P type opposite to the first conductivity type.

In the semiconductor device of the present invention, an example in which the third drain region is completely covered with the second drain region can be given.
The third drain region may be configured such that the side surface on the channel region side is not covered with the second drain region.
An example in which the third drain region is formed only in the region under the thick oxide film can be given. However, the formation region of the third drain region is not limited to the region under the thick oxide film, and the third drain region is a region other than the region under the thick oxide film, for example, the formation region of the second drain region. In this case, it may be formed extending in a region below the first drain region.

  The second drain region and the third drain region are preferably formed with a gap from the gate insulating film. However, the present invention is not limited to this, and the second drain region or the third drain region may be in contact with the gate insulating film.

  Further, it is preferable that the planar position of the end of the drain region on the source region side substantially coincides with the boundary position between the gate insulating film and the thick oxide film. Here, the end of the drain region on the source region side may be formed by the second drain region, or may be formed by the second drain region. However, the present invention is not limited to this, and the planar position of the end of the drain region on the source region side may not substantially coincide with the boundary position between the gate insulating film and the thick oxide film.

In the semiconductor device of the present invention, the first conductivity type may be P type and the second conductivity type may be N type, or the first conductivity type may be N type and the second conductivity type may be P type. May be.
Examples of the thick oxide film include a LOCOS oxide film and an STI film (an oxide film formed by a shallow trench isolation method).

  The semiconductor device of the present invention includes, for example, an output driver that controls output of an input voltage, a divided resistor circuit that divides the output voltage and supplies a divided voltage, a reference voltage generation circuit that supplies a reference voltage, A semiconductor device comprising a constant voltage generation circuit having a comparison circuit for comparing a divided voltage from the division resistance circuit with a reference voltage from the reference voltage generation circuit and controlling the operation of the output driver according to the comparison result The high voltage MOSFET which constitutes the present invention can be applied as an output driver.

The manufacturing method of the semiconductor device concerning this invention is a manufacturing method for forming the semiconductor device of this invention, Comprising: The following processes (A) to (G) are included.
(A) forming a first conductivity type well region in a semiconductor substrate;
(B) forming a second drain region by implanting a second conductivity type impurity into a predetermined region of the well region by an ion implantation method;
(C) forming a thick oxide film at least in a predetermined region on the surface of the second drain region;
(D) A step of implanting a second conductivity type impurity into a region including the region under the thick oxide film by an ion implantation method to form a third drain region so that at least a lower portion is covered with the second drain region. ,
(E) forming a gate insulating film adjacent to the thick oxide film on the surface of the well region;
(F) forming a gate electrode from above the gate insulating film to the thick oxide film;
(G) A second conductivity type impurity is implanted by ion implantation using the gate electrode and the thick oxide film as a mask to form a source region in the well region, and a first region in the second drain region. Forming a drain region;

  In the method for manufacturing a semiconductor device of the present invention, the planar position of the side of the second drain region resist pattern for defining the formation of the end portion on the source region side of the second drain region in the step (B), It is preferable that the planar positions of the sides of the thick oxide film resist pattern for defining the end of the thick oxide film on the source region side in the step (C) coincide. As a result, the planar position of the end of the drain region on the source region side substantially coincides with the boundary position between the gate insulating film and the thick oxide film.

Further, in the step (B), ion implantation is preferably performed with acceleration energy of 100 KeV or more.
Examples of the thick oxide film formed in the step (C) include a LOCOS oxide film and an STI film.

  In the semiconductor device of the present invention, the drain region of the high breakdown voltage MOSFET is formed in the first drain region formed at a distance from the gate electrode, and the region covering the first drain region and including at least under the thick oxide film. And a third drain region formed in a region including at least a lower portion covered with the second drain region and at least under the thick oxide film, wherein the first drain region is a third drain region. Since the second conductivity type impurity concentration is higher than that of the region and the third drain region is higher than that of the second drain region, the high concentration first drain region is changed to the low concentration first drain region. High breakdown voltage can be realized by covering with two drain regions. Further, since the third drain region having a higher concentration than the second drain region is disposed under the thick oxide film, the resistance value of the drain region can be lowered, and an increase in drain current can be achieved. Thus, the driving capability and breakdown voltage of the high breakdown voltage MOSFET can be improved.

  In the semiconductor device of the invention, if the third drain region is completely covered by the second drain region, the third drain region having the second conductivity type impurity concentration higher than that of the second drain region and the first conductivity are obtained. Since the contact surface with the mold well region can be eliminated, the drain junction breakdown voltage can be improved.

  In the semiconductor device of the invention, if the second drain region and the third drain region are formed with a gap from the gate insulating film, the electric field concentration in the vicinity of the gate insulating film can be reduced, so that the drain modulation is performed. The junction breakdown voltage can be improved.

  In addition, if the planar position of the end of the drain region on the source region side substantially coincides with the boundary position between the gate insulating film and the thick oxide film, the drain saturation current of the high breakdown voltage MOSFET constituting the present invention Can be maximized, drive capability can be maximized, and high withstand voltage can be achieved.

  In the method for manufacturing a semiconductor device of the present invention, a step (A) of forming a first conductivity type well region in a semiconductor substrate, and a step (B) of forming a second drain region in a predetermined region of the well region by ion implantation. A step (C) of forming a thick oxide film in a predetermined region on the surface of the second drain region, and a second drain region so that at least a lower part is covered with the second drain region in a region including the region under the thick oxide film by ion implantation. 3 includes a step (D) of forming a drain region, a step (E) of forming a gate insulating film, a step (F) of forming a gate electrode, and a step (G) of forming a source region and a first drain region. Since it did in this way, the high voltage | pressure-resistant MOSFET which comprises the semiconductor device of this invention can be formed.

  In the method for manufacturing a semiconductor device of the present invention, the planar position of the side of the resist pattern for the second drain region for defining the formation of the end of the second drain region on the source region side in the step (B), and the step (C If the planar positions of the sides of the thick oxide film resist pattern for defining the formation of the end of the thick oxide film on the source region in FIG. Can be formed so that the planar position of the portion substantially coincides with the boundary position between the gate insulating film and the thick oxide film, and the drain saturation current of the high voltage MOSFET is maximized to maximize the driving capability. Pull-out and high breakdown voltage can be achieved.

  Further, in the step (B), if the ion implantation is performed with acceleration energy of 100 KeV or more, the second drain region can be formed at a distance from the gate insulating film, and electric field concentration in the vicinity of the gate insulating film can be achieved. Since it can be relaxed, the drain modulation junction breakdown voltage can be improved.

  FIG. 1 is a sectional view showing a schematic configuration of an embodiment of a semiconductor device. FIG. 2 is a cross-sectional view showing the simulation result of the impurity concentration distribution of this embodiment. FIG. 3 is a diagram showing an impurity concentration profile in the depth direction at the position A-A ′ in FIG. 2. This embodiment will be described with reference to FIGS.

An N-type well region 4 is formed in the P-type semiconductor substrate 2. A P-type second drain region 6 is formed in the N-type well region 4.
LOCOS oxide films (thick film oxide films) 8 and 8a are formed on the surface of the P-type semiconductor substrate 2 near the periphery of the N-type well region 4 formation region and the periphery of the P-type second drain region 6 formation region. . A LOCOS oxide film formed in the vicinity of one end of the P-type second drain region 6 is denoted by reference numeral 8a.
A P-type third drain region 10 having a P-type impurity concentration higher than that of the P-type second drain region 6 is formed in a region under the LOCOS oxide film 8 a in the P-type second drain region 6.

A gate oxide film (gate insulating film) 12 is formed on the surface of the N-type well region 4 continuously to the LOCOS oxide film 8a. A gate electrode 14 is formed from the gate oxide film 12 to the LOCOS oxide film 8a.
Here, the P-type second drain region 6 is arranged at a distance from the gate oxide film 12. Further, the planar position of the end portion of the P-type second drain region 6 on the source region side substantially coincides with the boundary position between the gate oxide film 12 and the LOCOS oxide film 8a.

A P-type first drain region 16 is formed in the vicinity of the surface of the P-type second drain region 6 with a gap from the gate electrode 14. The P-type first drain region 16 has a higher P-type impurity concentration than the P-type second drain region 6 and the P-type third drain region 10.
In this embodiment, the drain region of the high breakdown voltage MOSFET is constituted by a P-type first drain region 16, a P-type second drain region 6, and a P-type third drain region 10.

  Near the surface of the N-type well region 4, a P-type source region 18 is formed adjacent to or overlapping with the side surface of the gate electrode 14 opposite to the P-type first drain region 16 side. The P-type source region 18 and the P-type second drain region 6 are arranged with a space therebetween, and the region near the surface of the N-type well region 4 between the regions 6 and 18 constitutes a channel region 20.

  In this embodiment, since the high-concentration P-type first drain region 16 is covered with the low-concentration P-type second drain region 6, a high breakdown voltage can be realized. Further, since the P-type third drain region 10 having a higher concentration than the P-type second drain region 6 is disposed under the LOCOS oxide film 8a, the resistance value of the drain region can be lowered and the drain current can be increased. can do.

  Further, since the P-type third drain region 10 is completely covered with the P-type second drain region 6, the P-type third drain region 10 having a higher P-type impurity concentration than the P-type second drain region 6 The contact surface with the N-type well region 4 can be eliminated, and the drain junction breakdown voltage can be improved.

  Furthermore, since the P-type second drain region 6 is disposed with a gap from the gate insulating film 12, electric field concentration in the vicinity of the gate insulating film 12 can be relaxed, and the drain junction breakdown voltage can be improved.

  4 and 5 are process cross-sectional views for explaining an embodiment of the manufacturing method. FIG. 6 is a plan view for explaining the opening region of the resist mask used in this embodiment. This embodiment will be described with reference to FIGS. 1 and 4 to 6.

(1) A resist pattern 22 is formed on the P-type semiconductor substrate 2 by a photoengraving technique in order to define an N-type well region formation region. For example, phosphorus 24, which is an N-type impurity, is ion-implanted by ion implantation under the conditions of an acceleration energy of 160 KeV and an implantation amount of 1 × 10 ¹³ cm ⁻² (FIG. 4A). And FIG. 6).

(2) After removing the resist pattern 22, for example, heat treatment is performed for 2 hours under conditions of a temperature of 1150 ° C. and a nitrogen atmosphere, and the implanted phosphorus 24 is diffused and activated to form the N-type well region 4 (FIG. 4 (b).)

(3) A second drain region resist pattern 26 is formed on the P-type semiconductor substrate 2 by a photoengraving technique in order to define the formation region of the second drain region. By ion implantation, using the second drain region resist pattern 26 as a mask, for example, boron 28 which is a P-type impurity is ion-implanted under the conditions of an acceleration energy of 160 KeV and an implantation amount of 1 × 10 ¹³ cm ⁻² ( (Refer FIG.4 (c) and FIG. 6.).

(4) After removing the resist pattern 26 for the second drain region, a silicon nitride film 30 is formed on the entire surface of the P-type semiconductor substrate 2. In order to demarcate the formation region of the LOCOS oxide film, LOCOS oxide film resist patterns 32a and 32b are formed by photolithography (see FIGS. 4D and 6). The planar position of the side of the LOCOS oxide film resist pattern 32a that defines the formation of the end portion on the source region side of the LOCOS oxide film, and the end portion on the source region side of the second drain region used in the step (3). The planar positions of the sides of the second drain region resist pattern 26 for defining the formation coincide with each other (see the position XX ′ in FIG. 6).

(5) After the silicon nitride film 30 is patterned by the etching technique using the LOCOS oxide film resist patterns 32a and 32b as a mask, the LOCOS oxide film resist patterns 32a and 32b are removed. For example, heat treatment is performed for 1 hour under conditions of a temperature of 1000 ° C. and an oxidizing atmosphere to form the LOCOS oxide films 8 and 8a. By this heat treatment, the boron 28 implanted in the step (3) is diffused and activated to form the P-type second drain region 6. (See FIG. 5 (e)).
Thereafter, the silicon nitride film 30 is removed.
Here, the boron 28 is diffused and activated simultaneously with the formation of the LOCOS oxide films 8 and 8a. However, the present invention is not limited to this, and a dedicated heat treatment for diffusing and activating the boron 28 is performed. A process may be provided.

(6) In order to define the formation region of the third drain region, a resist pattern 34 is formed by photolithography. With the resist pattern 34 as a mask, for example, boron 36, which is a P-type impurity, is ion-implanted by ion implantation under the conditions of an acceleration energy of 180 KeV and an implantation amount of 1 × 10 ¹³ cm ⁻² (FIG. 5F). And FIG. 6).

(7) After removing the resist pattern 34 and further removing the oxide film on the surface of the P-type semiconductor substrate 2 other than the region where the LOCOS oxide films 8 and 8a are formed, a heat treatment is performed in an oxygen atmosphere to form the gate oxide film 12. To do. By this heat treatment, the boron 36 implanted in the step (6) is diffused and activated to form the P-type third drain region 10. The planar position of the end portion of the P-type second drain region 6 on the source region side substantially coincides with the boundary position between the gate oxide film 12 and the LOCOS oxide film 8a.
After the polysilicon film 38 is formed on the entire surface of the P-type semiconductor substrate 2, a resist pattern 40 for defining a gate electrode formation region is formed on the polysilicon film 38 by photolithography (FIG. 5G and FIG. 5). (See FIG. 6.)

(8) The polysilicon film 38 is patterned by the etching technique using the resist pattern 40 as a mask to form the gate electrode 14. Thereafter, the resist pattern 40 is removed. By ion implantation, using LOCOS oxide films 8 and 8a and gate electrode 14 as a mask, for example, BF ₂ (boron difluoride) 42 is accelerating energy of 30 KeV and implantation amount of 3 × 10 ¹⁵ cm ⁻² . Inject (see FIG. 5 (h)).

(9) In order to diffuse and activate the implanted BF ₂ 42, for example, heat treatment is performed for 30 minutes under conditions of a temperature of 850 ° C. and a nitrogen atmosphere, and the P-type second drain region 6 is spaced apart from the gate electrode 14. A P-type first drain region 16 is formed, and a P-type source region 18 is formed in the N-type well region 4 adjacent to or overlapping the gate electrode 14 (see FIG. 1).

  In this embodiment, the opening of the second drain region resist pattern 26 is formed so as to surround the formation region of the LOCOS oxide film resist pattern 32 b corresponding to the formation region of the P-type first drain region 16. Therefore, the high-concentration P-type first drain region 16 can be formed so as to be covered with the low-concentration P-type second drain region 6, and the high breakdown voltage of the high breakdown voltage MOSFET can be increased.

  Further, the planar position of the side of the second drain region resist pattern 26 used in the step (3) for defining the end of the second drain region on the source region side, and the step (4). The planar positions of the sides of the LOCOS oxide film resist pattern 32a that define the formation of the end portion of the LOCOS oxide film on the source region side are made to coincide with each other (see the position XX ′ in FIG. 6). .), A structure in which the planar position of the end portion of the second drain region 10 on the source region side substantially coincides with the boundary position between the gate insulating film 12 and the LOCOS oxide film 8a can be formed. The saturation current can be maximized to maximize the driving capability and achieve a high breakdown voltage.

FIG. 7 shows the evaluation result of the drain saturation current with respect to the mask positional deviation distance between the second drain region resist pattern edge and the LOCOS oxide film resist pattern edge. The vertical axis represents the drain saturation current (A (ampere)), and the horizontal axis represents the mask misalignment distance (μm). As a sample, the ion implantation conditions for the second drain region are the sample 1 in which the acceleration energy is 160 KeV and the implantation amount is 1 × 10 ¹³ cm ⁻² , the acceleration energy is 100 KeV and the implantation amount is 1 × 10 ¹³ cm ⁻² . Sample 2 was used, and Sample 3 having an acceleration energy of 50 KeV and an injection amount of 1.6 × 10 ¹³ cm ⁻² was used. The other manufacturing steps of these samples are the same conditions as in the embodiment of the manufacturing method. 8, 9, and 10 show simulation results of impurity concentration distributions of Sample 1, Sample 2, and Sample 3. FIG.

  From FIG. 7, the drain saturation current becomes maximum for Samples 2 and 3 when the mask misalignment distance is 0, that is, when the edge of the second drain region resist pattern coincides with the edge of the LOCOS oxide film resist pattern. I understand. Also for sample 1, it can be seen that the mask misalignment distance is 0 and the drain saturation current is close to the maximum value.

  Also, as shown in FIG. 10, when the acceleration energy at the time of ion implantation for the second drain region is 50 KeV, the source side end of the P-type second drain region 6 is formed in the vicinity of the gate oxide film 12. I understand. On the other hand, as shown in FIG. 9, when the acceleration energy at the time of ion implantation for the second drain region is 100 KeV, the source side end of the P-type second drain region 6 is sufficiently spaced from the gate oxide film 12. You can see that it is formed. Therefore, the acceleration energy at the time of ion implantation for the second drain region is preferably set to 100 KeV or more. Thereby, it is possible to prevent the drain breakdown voltage from being lowered due to the concentration of the electric field near the gate electrode.

FIG. 11 is a sectional view showing a schematic configuration of still another embodiment of the semiconductor device. The same parts as those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted.
This embodiment is different from the embodiment shown in FIG. 1 in that the P-type third drain region 10 is formed to extend from the region under the LOCOS oxide film 8a to the region under the P-type first drain region 16. Is a point. This structure can be formed by changing the formation region of the opening of the resist pattern 34 used in FIG. Even with this structure, the same effects as the embodiment shown in FIG. 1 can be obtained.

  However, since the P-type third drain region 10 is formed using the LOCOS oxide films 8 and 8a as an implantation mask, the P-type third drain region 10 is formed deeply in a region under the P-type first drain region 16, The punch-through breakdown voltage between the P-type third drain region 10 and the P-type semiconductor substrate 2 is lowered. Therefore, the P-type third drain region 10 is preferably formed only under the LOCOS oxide film 8a as in the embodiment shown in FIG.

FIG. 12 is a sectional view showing a schematic configuration of still another embodiment of the semiconductor device. The same parts as those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted.
This embodiment is different from the embodiment shown in FIG. 1 in that the side surface of the P-type third drain region 10 on the channel region 20 side is not covered with the P-type second drain region 6. This structure can also be formed by changing the formation region of the opening of the resist pattern 34 used in FIG. Even with this structure, the same effects as the embodiment shown in FIG. 1 can be obtained.

In the above embodiment, only the formation region of the high breakdown voltage MOSFET has been illustrated and described. However, the present invention is not limited to this, and as shown in FIG. 13, the formation region is different from the formation region of the high breakdown voltage MOSFET. A transistor for a logic circuit capable of high-speed operation with a low voltage may be provided.
FIG. 13 is a cross-sectional view showing a schematic configuration of still another embodiment of the semiconductor device. The same parts as those in FIG. Since the structure of the high voltage MOSFET is the same as that in FIG.

An N-type well region 44 for the P-channel MOSFET and a P-type well 46 for the N-channel MOSFET are formed in different regions in the region different from the high-breakdown-voltage MOSFET formation region of the P-type semiconductor substrate 2.
A gate oxide film 48, a gate electrode 50, a P-type drain region 52, and a P-type source region 54 are formed in the formation region of the N-type well region 44 to form a P-channel MOSFET.
A gate oxide film 56, a gate electrode 58, an N-type drain region 60, and an N-type source region 62 are formed in the formation region of the P-type well region 46 to form an N-channel MOSFET.
As described above, a MOSFET for a logic circuit capable of high-speed operation at a low voltage and a high breakdown voltage MOSFET can be integrated on a single chip at a low cost.

As described above, the embodiments of the present invention have been described. However, the conductivity types of the semiconductor substrate, the well region, the drain region, and the source region shown in the above embodiments are merely examples, and the present invention is not limited thereto. These may be changed to the reverse conductivity type.
Further, the implantation conditions such as the implanted ion species, ion implantation amount, and implantation energy in the ion implantation of the above-described examples are merely examples of preferred embodiments of the present invention, and the present invention is not limited thereto. .

The MOSFET constituting the semiconductor device of the present invention can be applied to a semiconductor device provided with an analog circuit, for example.
FIG. 14 is a circuit diagram showing an embodiment of a semiconductor device provided with a constant voltage generation circuit which is an analog circuit.
A constant voltage generation circuit 68 is provided in order to stably supply power from the DC power supply 64 to the load 66. The constant voltage generation circuit 68 includes an input terminal (Vbat) 70 to which a DC power supply 64 is connected, a reference voltage generation circuit (Vref) 72, an operational amplifier (comparison circuit) 74, and an output driver comprising a low on-resistance and high breakdown voltage MOSFET. 76, division resistance elements R1 and R2, and an output terminal (Vout) 78 are provided. The output driver 76 is composed of a high voltage MOSFET that constitutes the semiconductor device of the present invention.

  In the operational amplifier 74 of the constant voltage generation circuit 68, the output terminal is connected to the gate electrode of the output driver 76, the reference voltage Vref is applied from the reference voltage generation circuit 72 to the inverting input terminal (−), and the non-inverting input terminal (+ ), A voltage obtained by dividing the output voltage Vout by the resistance elements R1 and R2 is applied, and the division voltage of the resistance elements R1 and R2 is controlled to be equal to the reference voltage Vref.

  The semiconductor device to which the high voltage MOSFET constituting the present invention is applied is not limited to a semiconductor device having a constant voltage generation circuit, and the present invention is applied to any semiconductor device having a high voltage MOSFET. Can do.

The embodiments of the present invention have been described above. However, the present invention is not limited to these, and the dimensions, shapes, materials, arrangements, and the like are examples, and are within the scope of the present invention described in the claims. Various changes can be made.
For example, although the LOCOS film is used as the thick oxide film in the above embodiment, the present invention is not limited to this, and a buried STI film is used as the thick oxide film instead of the LOCOS oxide film. It can also be applied to.

  INDUSTRIAL APPLICABILITY The present invention can be used for a semiconductor device including a high breakdown voltage MOSFET having a thick oxide film under a side surface on at least the drain side of the gate electrode and a method for manufacturing the same.

It is sectional drawing which shows schematic structure of one Example of a semiconductor device. It is sectional drawing which shows the simulation result of the impurity concentration distribution of the Example. It is a figure which shows the impurity concentration profile of the depth direction in the A-A 'position of FIG. It is process sectional drawing for demonstrating the first half of one Example of a manufacturing method. It is process sectional drawing for demonstrating the second half of the Example. It is a top view for demonstrating the opening part area | region of the resist mask used in the Example. It is a figure which shows the evaluation result of the drain saturation current with respect to the mask position shift distance of the resist pattern edge for 2nd drain regions, and the resist pattern edge for LOCOS oxide films. FIG. 8 is a cross-sectional view showing the simulation result of the impurity concentration distribution of the MOSFET which is the sample 1 used in the evaluation of FIG. 7 and is an example. FIG. 8 is a cross-sectional view showing the simulation result of the impurity concentration distribution of the MOSFET which is Sample 2 used in the evaluation of FIG. 7 and is an example. FIG. 8 is a cross-sectional view showing a simulation result of impurity concentration distribution of the MOSFET which is the sample 3 used in the evaluation of FIG. 7 and which is an example. It is sectional drawing which shows schematic structure of the further another Example of a semiconductor device. It is sectional drawing which shows other schematic structure of a semiconductor device. It is sectional drawing which shows other schematic structure of a semiconductor device. 1 is a circuit diagram showing an embodiment of a semiconductor device including a constant voltage generation circuit which is an analog circuit. It is sectional drawing for demonstrating an example of the conventional semiconductor device. It is sectional drawing for demonstrating the other example of the conventional semiconductor device.

Explanation of symbols

2 P-type semiconductor substrate 4 N-type well region 6 P-type second drain region 8, 8a LOCOS oxide film 10 P-type third drain region 12 Gate oxide film 14 Gate electrode 16 First drain region 18 P-type source region 20 Channel region

Claims (14)

A source region and a drain region of a second conductivity type formed in the well region of the first conductivity type with a space therebetween, a channel region formed between the source region and the drain region, and a channel region formed on the channel region. A gate oxide film, a thick oxide film formed on the drain region adjacent to the gate insulating film and having a thickness greater than the gate insulating film, and the thick film oxide film from above the gate insulating film. Comprising a high voltage MOSFET having a gate electrode formed over the film,
The drain region includes a first drain region formed at a distance from the gate electrode, a second drain region that covers the first drain region and is formed in a region including at least under the thick oxide film, At least a lower portion is covered with the second drain region, and at least a third drain region is formed in a region including under the thick oxide film, and the first drain region is more than the third drain region. A semiconductor device having a high second conductivity type impurity concentration, wherein the third drain region has a second conductivity type impurity concentration higher than that of the second drain region.   The semiconductor device according to claim 1, wherein the third drain region is completely covered with the second drain region.   The semiconductor device according to claim 1, wherein a side surface of the third drain region on the channel region side is not covered with the second drain region.   The semiconductor device according to claim 1, wherein the third drain region is formed only in a region under the thick oxide film.   5. The semiconductor device according to claim 1, wherein the second drain region and the third drain region are formed apart from the gate insulating film.   The semiconductor device according to claim 1, wherein a planar position of an end portion of the drain region on the source region side substantially coincides with a boundary position between the gate insulating film and the thick oxide film.   The semiconductor device according to claim 1, wherein the first conductivity type is a P-type, and the second conductivity type is an N-type.   The semiconductor device according to claim 1, wherein the first conductivity type is an N type, and the second conductivity type is a P type.   The semiconductor device according to claim 1, wherein the thick oxide film is a LOCOS oxide film or an STI film. An output driver for controlling the output of the input voltage, a divided resistor circuit for dividing the output voltage and supplying a divided voltage, a reference voltage generating circuit for supplying a reference voltage, and a divided voltage from the divided resistor circuit In a semiconductor device including a constant voltage generation circuit having a comparison circuit for comparing the reference voltage from the reference voltage generation circuit and controlling the operation of the output driver according to the comparison result,
A semiconductor device comprising the high breakdown voltage MOSFET according to claim 1 as the output driver. A method for manufacturing a semiconductor device for forming a semiconductor device according to claim 1, comprising the following steps (A) to (G).
(A) forming a first conductivity type well region in a semiconductor substrate;
(B) forming a second drain region by implanting a second conductivity type impurity into a predetermined region of the well region by an ion implantation method;
(C) forming a thick oxide film at least in a predetermined region on the surface of the second drain region;
(D) A step of implanting a second conductivity type impurity into the region including under the thick oxide film by ion implantation to form a third drain region so that at least the lower part is covered with the second drain region. ,
(E) forming a gate insulating film adjacent to the thick oxide film on the surface of the well region;
(F) forming a gate electrode from above the gate insulating film to the thick oxide film;
(G) A second conductivity type impurity is implanted by ion implantation using the gate electrode and the thick oxide film as a mask to form a source region in the well region, and a first region in the second drain region. Forming a drain region;   The planar position of the side of the second drain region resist pattern for defining the source region side end of the second drain region in the step (B), and the thick oxide film in the step (C) The method of manufacturing a semiconductor device according to claim 10, wherein the planar positions of the sides of the resist pattern for a thick film oxide film for defining the formation of the end portion on the source region side of each other match.   12. The method of manufacturing a semiconductor device according to claim 10, wherein in the step (B), ion implantation is performed with an acceleration energy of 100 KeV or more.   The method of manufacturing a semiconductor device according to claim 11, wherein the thick oxide film is a LOCOS oxide film or an STI film.