CN112802902B - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

The invention provides a semiconductor device and a method of manufacturing the same. The semiconductor device comprises an asymmetric field effect transistor arranged on a semiconductor substrate, wherein the thickness of a first gate insulating layer in the asymmetric field effect transistor is more than 60nm, the first gate insulating layer is wider than a first gate on one side of a first source region to form an expansion insulating part, the asymmetric field effect transistor comprises a source expansion region which is formed in the semiconductor substrate and is positioned below the expansion insulating part, and the source expansion region is connected with the first source region and a channel region, so that the threshold voltage dispersion of the asymmetric field effect transistor is reduced, and the transistor characteristic is stable. The manufacturing method can be used for manufacturing the above semiconductor device having excellent characteristics.

Description

Semiconductor device and method for manufacturing the same

Technical Field

The invention relates to the technical field of semiconductors, in particular to a semiconductor device and a manufacturing method thereof.

Background

In a driver IC of a small panel display, an asymmetric High Voltage Metal Oxide Semiconductor (HVMOS) having an operating Voltage of about 25V to 40V is often used.

Fig. 14 is a cross-sectional view of a prior art semiconductor device including an asymmetric HVMOS. Fig. 14 illustrates an asymmetric HVMOS (i.e., HVNMOS) for an n-channel. Referring to fig. 14, an asymmetric HVMOS 200 includes a P-type semiconductor substrate 10, an N-type drift region 12, a P-type guard ring region 14, a high concentration N-type source region 16, a high concentration N-type drain region 18, a high concentration P-type tap region 20 (i.e., P + tap), an insulating region 22, an insulating region 24, a gate insulating layer 26, and a gate 28 made of polysilicon or the like. In the asymmetric HVMOS 200, the gate insulating layer 26 is formed thick, about 60nm to 100 nm. The area of the gate insulating layer 26 is larger than that of the gate electrode 28 formed thereon, and the gate insulating layer 26 extends laterally toward the source region 16 to a margin distance X1 that makes one side end of the source region 16 of the gate insulating layer 26 exceed the gate electrode 28 by about 0.1 μm to 0.2 μm. In the asymmetric HVMOS 200, the source region 16 extends beyond the gate insulating layer 26 to the substrate region under the gate 28, and the lateral distance between the end of the source region 16 side of the gate 28 and the end of the insulating region 22 formed in the drift region 12 facing the source region 16 is the channel length C. That is, source region 16 extends directly to the channel region.

Fig. 15 is a schematic cross-sectional view of a prior art semiconductor device including asymmetric HVMOS and LVMOS. As shown in fig. 14 and 15, in the conventional chip design, the asymmetric HVMOS and the LVMOS (Low Voltage Metal Oxide Semiconductor) are mostly integrated in the same Semiconductor substrate 10. In fig. 15, for the asymmetric HVMOS, only the structure thereof on the side of the source region 16, which is important in the present application, is shown.

As shown in fig. 15, the LVMOS includes a source region 32 and a drain region 34 formed in the P-type well region 30 and being high-concentration N-type, an extension region 36 extending from the source region 32 and the drain region 34 and being low-concentration N-type, a gate insulating layer 38 spanning from the source region 32 to the drain region 34, and a gate electrode 40 formed on the gate insulating layer 38 and made of polysilicon or the like. The LVMOS is insulated from other elements on the semiconductor substrate 10 by insulating regions 24.

Referring to fig. 14 and 15, the source region 16 of the asymmetric HVMOS 200 is formed by the same ion implantation process as the source region 32 and the drain region 34 of the LVMOS, both of high concentration N-type. That is, the source region 32 and the drain region 34 of the LVMOS are ion-implanted while N-type dopant ions such as phosphorus, arsenic, etc. are implanted to obtain the source region 16 and the drain region 18 of the asymmetric HVMOS 200. When ion implantation of source region 16 is performed, it is necessary to cause the implanted ions to penetrate through the portion of gate insulating layer 26 extending from gate electrode 28 toward the source region 16 side to enter substrate 10, thereby forming source region 16 extending to the channel region.

In a semiconductor integrated device in which an asymmetric HVMOS and a LVMOS are formed on the same substrate, it is generally necessary to optimize the implantation conditions according to the requirements of the LVMOS. As the size of the LVMOS to be combined becomes smaller, the width of the gate 40 of the LVMOS becomes shorter (e.g., less than 100 nm), and the junction depth of the source region 32 and the drain region 34 becomes shallower. Therefore, it is necessary to reduce the energy of the dopant ion implantation when forming the source region 32 and the drain region 34. As such, when performing the doping ion implantation to simultaneously form the source region 16 of the asymmetric HVMOS, and the source region 32 and the drain region 34 of the LVMOS, the smaller ion implantation energy results in a greater difficulty in implanting ions through the gate insulating layer 26 in the range of the margin distance X1 on the source region 16 side of the gate insulating layer 26 of the asymmetric HVMOS, thereby making it possible to create a gap between the source region 16 and the channel region (the region indicated by the channel length C) of the asymmetric HVMOS. This gap may increase the threshold voltage Vth of the asymmetric HVMOS and decrease its operating current Id, resulting in a decrease in the operating performance of the asymmetric HVMOS.

Disclosure of Invention

In order to improve the performance of asymmetric HVMOS, the invention provides a semiconductor device and a manufacturing method of the semiconductor device.

In one aspect, the present invention provides a semiconductor device comprising a semiconductor substrate of a first conductivity type and an asymmetric field effect transistor provided on the semiconductor substrate, the asymmetric field effect transistor comprising:

a first source region and a first drain region formed in the semiconductor substrate and having a second conductivity type opposite to the first conductivity type;

the first source region and the first drain region are positioned at two sides of the first grid electrode, and the channel region is positioned in the semiconductor substrate right below the first grid electrode; an insulation region is arranged between the channel region and the first drain region, so that the first source region and the first drain region are asymmetric relative to the first gate, the first drain region is arranged at a position far away from the first gate compared with the first source region, the thickness of the first gate insulation layer is more than 60nm, the first gate insulation layer comprises an extension insulation part, and the extension insulation part is a part of the first gate insulation layer, which is wider than the first gate on one side of the first source region by a margin distance; and the number of the first and second groups,

a source extension region formed within the semiconductor substrate and having a second conductivity type, the source extension region being located under the extension insulator and connecting the first source region and the channel region.

Optionally, the asymmetric field effect transistor includes a drift region disposed within the semiconductor substrate and having a second conductivity type; wherein the first drain region is disposed in the drift region, and the source extension region is shallower than the drift region relative to a top surface of the semiconductor substrate.

Optionally, the insulating region extends from the inside of the semiconductor substrate to the surface, and a region where the first gate insulating layer overlaps with the first gate electrode covers a part of the insulating region.

Optionally, the thickness of the first gate insulating layer is 100nm or less.

Optionally, the source extension region is formed in a first well region located in the semiconductor substrate and having a first conductivity type, and the first source region is formed in the source extension region.

Optionally, the operating voltage of the asymmetric field effect transistor is 25V or more and 40V or less.

Optionally, the semiconductor device further includes another field effect transistor disposed on the semiconductor substrate, where the another field effect transistor includes a second gate insulating layer on the semiconductor substrate, a second gate on the second gate insulating layer, and a second source region and a second drain region disposed in the semiconductor substrate, and a second gate insulating layer corresponding to the another field effect transistor is thinner than a first gate insulating layer corresponding to the asymmetric field effect transistor.

Optionally, the additional field effect transistor includes at least one symmetric field effect transistor, the second source region and the second drain region corresponding to each symmetric field effect transistor are symmetric with respect to the corresponding second gate, and a gate length of at least one of the symmetric field effect transistors is less than or equal to 100 nm.

Optionally, the additional field effect transistor includes a first field effect transistor and a second field effect transistor, a thickness of the second gate insulating layer corresponding to the first field effect transistor is greater than or equal to 10nm and less than or equal to 20nm, and a thickness of the second gate insulating layer corresponding to the second field effect transistor is less than 4 nm.

Optionally, a second source region and a second drain region corresponding to the first field effect transistor both have the first conductivity type or the second conductivity type, and a second source region and a second drain region corresponding to the second field effect transistor have the second conductivity type.

In one aspect, the present invention provides a method for manufacturing the semiconductor device, including the steps of:

providing a semiconductor substrate; and the number of the first and second groups,

forming a first field effect transistor and the asymmetric field effect transistor on the semiconductor substrate, wherein the first field effect transistor comprises a second source region and a second drain region which are formed in the semiconductor substrate, a second gate insulating layer which is formed on the semiconductor substrate and a second gate electrode which is formed on the second gate insulating layer, the second source region and the second drain region of the first field effect transistor are of a second conductivity type, and the thickness of the second gate insulating layer of the first field effect transistor is thinner than that of the first gate insulating layer of the asymmetric field effect transistor;

after the first grid electrode and the second grid electrode are formed and before the first source region, the first drain region, the second source region and the second drain region are formed, extension regions are formed in the semiconductor substrate on two sides of the second grid electrode through ion implantation and heat treatment, and meanwhile, the source extension regions are formed in the semiconductor substrate.

In one aspect, the present invention provides a method for manufacturing the semiconductor device, including the steps of: providing a semiconductor substrate; and the number of the first and second groups,

forming a first field effect transistor and the asymmetric field effect transistor on the semiconductor substrate, wherein the first field effect transistor comprises a well region which is formed in the semiconductor substrate and has a second conductivity type, a second source region and a second drain region which are formed in the well region, a second gate insulating layer which is formed on the semiconductor substrate, and a second gate which is formed on the second gate insulating layer, and the thickness of the second gate insulating layer of the first field effect transistor is thinner than that of the first gate insulating layer of the asymmetric field effect transistor;

before the first grid and the second grid are formed, the well region is formed in the semiconductor substrate below the second grid through ion implantation and heat treatment, and the source extension region is formed in the semiconductor substrate at the same time.

Optionally, the manufacturing method further includes forming a second field effect transistor on the semiconductor substrate, where the second field effect transistor includes a source region and a drain region formed in the semiconductor substrate, a gate insulating layer formed on the semiconductor substrate, and a gate electrode formed on the gate insulating layer, a thickness of the gate insulating layer of the second field effect transistor is thinner than that of a second gate insulating layer corresponding to the first field effect transistor, and the source region and the drain region of the second field effect transistor have a second conductivity type; and the first source region and the first drain region of the asymmetric field effect transistor and the source region and the drain region of the second field effect transistor are formed by the same ion implantation and heat treatment process.

Optionally, the gate length of the second field effect transistor is 100nm or less.

Optionally, the thickness of the first gate insulating layer is 60nm to 100nm, and the thickness of the second gate insulating layer is 10nm to 20 nm.

The semiconductor device provided by the invention comprises an asymmetric field effect transistor arranged on a semiconductor substrate, wherein the thickness of a first gate insulating layer in the asymmetric field effect transistor is more than 60nm, the first gate insulating layer is wider than a first gate on one side of a first source region to form an extended insulating part, the asymmetric field effect transistor comprises a source extension region which is formed in the semiconductor substrate and is positioned below the extended insulating part, and the source extension region is connected with the first source region and a channel region, so that the dispersion of threshold voltage of the asymmetric field effect transistor is reduced, and the transistor characteristic is stable. The manufacturing method can be used for manufacturing the above semiconductor device having excellent characteristics with similar advantages, and also contributes to simplification of the manufacturing process, thereby reducing the manufacturing cost.

Drawings

Fig. 1 is a schematic cross-sectional view of a semiconductor device including an asymmetric HVMOS according to an embodiment of the invention.

Fig. 2 is a schematic plan view of a semiconductor device including an asymmetric HVMOS according to an embodiment of the invention.

Fig. 3 is a cross-sectional schematic view of a semiconductor device including asymmetric HVMOS features according to an embodiment of the invention.

Fig. 4 is a schematic cross-sectional view of a semiconductor device including asymmetric HVMOS, MVMOS, and LVMOS devices according to an embodiment of the invention.

Fig. 5 is a schematic cross-sectional view corresponding to steps S10 to S18 in the method for manufacturing a semiconductor device according to an embodiment of the present invention.

Fig. 6 is a schematic cross-sectional view corresponding to steps S20 to S26 in the method for manufacturing a semiconductor device according to an embodiment of the present invention.

Fig. 7 is a schematic cross-sectional view of a semiconductor device including asymmetric HVMOS, MVMOS, and LVMOS devices according to an embodiment of the invention.

Fig. 8 is a schematic cross-sectional view corresponding to steps S30 to S38 in the method of manufacturing a semiconductor device according to an embodiment of the present invention.

Fig. 9 is a schematic cross-sectional view corresponding to steps S40 to S46 in the method of manufacturing a semiconductor device according to an embodiment of the present invention.

Fig. 10 is a simulation result of a relationship between a gate-source voltage and a drain-source current of an asymmetric HVMOS in a semiconductor device of the related art for different gate insulating layer thicknesses.

Fig. 11 is a simulation result of the relationship between the gate-source voltage and the drain-source current of the asymmetric HVMOS in the semiconductor device according to an embodiment of the invention at different gate insulating layer thicknesses.

Fig. 12 is a simulation result of threshold voltage variation with HVMOS gate insulator thickness.

Fig. 13 is a simulation result of drain-source current as a function of HVMOS gate insulator thickness.

Fig. 14 is a schematic cross-sectional view of a prior art semiconductor device including an asymmetric HVMOS.

Fig. 15 is a schematic cross-sectional view of a prior art semiconductor device including asymmetric HVMOS and LVMOS.

Description of reference numerals:

100. 102-a semiconductor device; 10-a semiconductor substrate; 12-a drift region; 14-a guard ring region; 16 a-a source extension region; 16. 16b, 32 b-source regions; 18. 34, 34 b-drain region; 20-a tap region; 22. 24-an insulating region; 26. 38-gate insulating layer; 28. 40-a gate; 30. 30 b-well region; 36. 36 b-extension zone.

Detailed Description

The semiconductor device and the method for manufacturing the same according to the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, but merely as a convenient and clear aid in describing embodiments of the invention, which should not be construed as limited to the specific shapes of regions illustrated in the drawings. For the sake of clarity, in all the drawings for assisting the description of the embodiments of the present invention, the same components are denoted by the same reference numerals in principle, and the duplicated description thereof is omitted. The terms "first," "second," and the like in the following description are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances. For the sake of clarity, in all the drawings for assisting the description of the embodiments of the present invention, the same components are denoted by the same reference numerals in principle, and the duplicated description thereof is omitted.

It is to be understood that the various embodiments are merely exemplary of specific embodiments of making and using embodiments and are not to be construed as limiting the scope of the invention in making and using it. Moreover, the respective descriptions of the embodiments are only for clearly explaining the meaning of the present invention, but technical features in each embodiment do not belong to features unique to the embodiment, and all the features of each embodiment may be taken as features of one general embodiment. In some embodiments, the technical features of the following embodiments can be related and inspired to form a new embodiment.

The first embodiment is as follows: semiconductor device with a plurality of transistors

Fig. 1 is a schematic cross-sectional view of a semiconductor device including an asymmetric HVMOS according to an embodiment of the invention. Fig. 2 is a schematic plan view of a semiconductor device including an asymmetric HVMOS according to an embodiment of the invention. The term "asymmetric HVMOS" as used herein refers to an asymmetric High Voltage field effect transistor (HVMOS) in which a structure on the source region side is smaller in volume than that on the drain region side, and a High Voltage is generally applied to the drain region side. The operating voltage of the asymmetric HVMOS is, for example, 25V or more and 40V or less. Semiconductor devices including asymmetric HVMOS are used, for example, for display drivers. Fig. 3 is a cross-sectional schematic view of a semiconductor device including asymmetric HVMOS features according to an embodiment of the invention. It should be noted that fig. 1 to 3 are schematic diagrams for explaining the basic structure of the asymmetric HVMOS included in the semiconductor device 100, and emphatically show the respective portions constituting the asymmetric HVMOS, and the planar direction dimensions and the thickness direction dimensions of the respective portions may not be in proportion to the actual dimensions. In fig. 2, a part of the structure (mainly, an insulating layer) of the asymmetric HVMOS is omitted for clarity of explanation.

In the following description, the dimensions of each portion refer to the dimensions in the length direction (X direction as shown in fig. 2 and 3) and the thickness direction (Z direction as shown in fig. 2 and 3) in the channel current flow direction in the cross-sectional schematic view. Further, the dimension in the width direction (Y direction as shown in fig. 2 and 3) can be set as appropriate depending on factors such as the maximum capacity required in the asymmetric HVMOS.

Referring to fig. 1 to 3, in an embodiment of the present invention, a semiconductor device 100 includes an asymmetric HVMOS including a semiconductor substrate 10, a drift region 12, a guard ring region 14, a source extension region 16a, a source region 16b (as a first source region, hereinafter the same), a drain region 18 (as a first drain region, hereinafter the same), a tap region 20, an insulating region 22, an insulating region 24, a gate insulating layer 26 (as a first gate insulating layer, hereinafter the same), and a gate electrode 28 (as a first gate electrode, hereinafter the same).

Hereinafter, a case where the asymmetric HVMOS included in the semiconductor device 100 is an n-channel HVMOS will be described. In this case, in the following description, the first conductive type is a P type, and the second conductive type opposite to the first conductive type is an N type. However, the asymmetric HVMOS included in the semiconductor device 100 is not limited to the n-channel HVMOS, and may be a p-channel HVMOS. In the latter case, it is only necessary to replace the first conductivity type with an N-type and the second conductivity type opposite to the first conductivity type with a P-type.

The asymmetric HVMOS is formed on the surface of the semiconductor substrate 10. The semiconductor substrate 10 may be, for example, a silicon substrate. The semiconductor substrate 10 has a first conductivity type.

The drift region 12 is a region where a depletion layer is formed and carrier drift occurs when the asymmetric HVMOS operates. The drift region 12 has a second conductivity type opposite to the first conductivity type. The doping concentration of the drift region 12 is, for example, 1 × 10¹⁶/cm³Above and 5 × 10¹⁷/cm³The following. Preferably, one end of drift region 12 is located near the center below gate electrode 28, and the other end is located at a distance of 2.5 μm or more and 4 μm or less from the end of gate electrode 28 facing drain region 18.

Guard ring region 14 is a well region for separating the asymmetric HVMOS from other components, and guard ring region 14 passes around the device region that contains drift region 12, gate insulating layer 26, and gate 28 of the asymmetric HVMOS. Guard ring region 14 has a first conductivity type. The doping concentration of the guard ring region 14 is, for example, 1 × 10¹⁶/cm³Above and 5 × 10¹⁷/cm³The following. On the side where the source extension region 16a and the source region 16b are disposed, the guard ring region 14 extends to a region overlapping with the gate insulating layer 26 and the gate electrode 28, which serves as a first conductivity type well region of the asymmetric HVMOS.

The source extension region 16a and the source region 16b are regions constituting the source of the asymmetric HVMOS. The source extension regions 16a have the same conductivity type as the drift region 12, i.e., the second conductivity type. The doping concentration of the source extension region 16a is, for example, 1 × 10¹⁸/cm³Above and 1 × 10¹⁹/cm³The following. The source extension region 16a extends within the guard ring region 14 to a region overlapping the gate insulating layer 26 and the gate electrode 28. That is, the source extension region 16a is under the gate 28Extending to the channel region (C denotes the channel length). Specifically, the overlap between the source extension region 16a and the gate electrode 28 is preferably in the range of 0.05 μm to 0.15 μm. Further, the source extension regions 16a are formed in regions shallower than the drift region 12 with respect to the surface of the semiconductor substrate 10.

The source extension 16a of the asymmetric HVMOS is used to connect the source region 16b and the channel region of the asymmetric HVMOS. By providing the source extension region 16a, dispersion of the threshold voltage Vth of the asymmetric HVMOS can be reduced and the characteristics of the asymmetric HVMOS become more stable.

The source region 16b has the same conductivity type as the drift region 12, i.e., the second conductivity type. The doping concentration of the source region 16b is higher than that of the source extension region 16a, and is preferably 1 × 10¹⁹/cm³Above and 1 × 10²¹/cm³The following. The source region 16b is formed in such a manner as to be connected to the source extension region 16 a. In the present embodiment, referring to fig. 1, the source region 16b extends from the end of the insulating region 24 to the vicinity of the end of the gate insulating layer 26 or extends in a direction toward the gate electrode 28 side than the end of the gate insulating layer 26 in the source extension region 16 a. The length of source region 16b (in the X direction shown in fig. 2 and 3) is, for example, 0.6 μm or more and 0.9 μm or less.

The drain region 18 is a region constituting a drain of the asymmetric HVMOS. The drain region 18 is disposed in a region spaced apart from the gate insulating layer 26 and the gate electrode 28 within the drift region 12. Specifically, the drain region 18 is disposed at a position farther from the gate electrode 28 than the source extension region 16a and the source region 16 b. That is, drain region 18 is disposed asymmetrically with respect to gate electrode 28 and source extension region 16a, and source region 16 b. The drain region 18 has the same conductivity type as the drift region 12, i.e., a second conductivity type. The doping concentration of the drain region 18 is, for example, 1 × 10¹⁹/cm³Above and 1 × 10²¹/cm³The following. The length (X direction) of the drain region 18 is preferably 0.3 μm or more and 0.5 μm or less.

The tap region 20 is a region for applying a voltage to the guard ring region 14. The tap region 20 is formed in the guard ring region 14 and is disposed to surround a device region containing the drift region 12, the gate insulating layer 26, and the gate electrode 28. The tap region 20 and the guard ring region 14 have the same conductivity type, i.e., the secondA conductive type. The doping concentration of the tap region 20 is, for example, 1 × 10¹⁹/cm³Above and 1 × 10²¹/cm³The following. The length (X direction) of the tap region 20 is preferably 0.3 μm or more and 0.5 μm or less.

Insulating region 22 is an insulating region provided to relax an electric field between drain region 18 and gate electrode 28. The insulation region 22 may be a shallow trench isolation region (STI region), but is not limited thereto. When the semiconductor substrate 10 is a silicon substrate, the insulating region 22 may be silicon oxide (SiO)₂) Films, silicon nitride (SiN) films, and the like. The insulating region 22 extends within the drift region 12 from a region overlapping the gate insulating layer 26 and the gate electrode 28 to a region proximate the drain region 18. The thickness of the insulating region 22 extending downward in the depth direction of the semiconductor substrate 10 is preferably 250nm or more and 300nm or less. The length (X direction) of the insulating region 22 is preferably 2 μm or more and 3 μm or less. Further, the insulating region 22 is preferably disposed such that the center position in the length direction (X direction) thereof is in the vicinity of the end of the gate electrode 28.

The insulating region 24 is a region for insulating components of the asymmetric HVMOS from each other. When the semiconductor substrate 10 is a silicon substrate, the insulating region 24 may be silicon oxide (SiO)₂) Films, silicon nitride (SiN) films, and the like. The length (X direction) of the insulating region 24 provided between the source region 16b and the tap region 20 is, for example, 0.4 μm or more and 0.8 μm or less. Further, the length (X direction) of the insulating region 24 provided between the drain region 18 and the tap region 20 is, for example, 1.8 μm or more and 3.2 μm.

The gate insulating layer 26 is an insulating layer of a gate member of an asymmetric HVMOS. When the semiconductor substrate 10 is a silicon substrate, the gate insulating layer 26 may be silicon oxide (SiO)₂) Layer, silicon nitride (SiN) layer, silicon oxynitride (SiO)_xN_y) And (3) a membrane. A gate insulating layer 26 is disposed over a region spanning the well region of guard ring region 14, a portion of drift region 12, and a portion of insulating region 22. In order to set the operating voltage range of the asymmetric HVMOS to about 25V to 40V, the thickness of the gate insulating layer 26 may be selected to be 60nm or more and 100nm or less.

The gate electrode 28 is an electrode for applying a gate voltage to the gate insulating layer 26. The gate 28 may be a polysilicon layer, a metal layer, or a silicide layer, or a stack of such layers. A gate electrode 28 is disposed in a region above the gate insulating layer 26. When the gate electrode 28 is a polysilicon layer, the thickness of the gate electrode 28 may be selected to be 100nm or more and 200nm or less. The length of the gate electrode 28 is, for example, 2 μm or more and 3 μm or less. Further, the end portion of the gate electrode 28 on the side toward the drain region 18 preferably extends (in the X direction) to the vicinity of the center of the insulating region 22. Of the regions where the gate electrode 28 is provided with respect to the semiconductor substrate 10 with the gate insulating layer 26 interposed therebetween, a region from the source extension region 16 a-side end portion of the gate electrode 28 to the end portion of the drift region 12 is a channel region, and the length of the channel region in the X direction is a channel length C.

In the semiconductor device 100 of the present embodiment, the extension insulating portion is provided in the gate insulating layer 26 in the region where the gate insulating layer 26 is provided, at least on the source region 16b side, and extends in the X direction by a distance, which is denoted as a margin distance X1, with the margin distance X1 being the length of the extension insulating portion. The remaining edge distance X1 can be 0.1 μm to 0.2 μm, for example.

Fig. 4 is a schematic cross-sectional view of a semiconductor device including asymmetric HVMOS, MVMOS, and LVMOS devices according to an embodiment of the invention. As shown in fig. 4, in the Semiconductor device 100 of the present embodiment, besides the asymmetric HVMOS, a Medium Voltage Metal Oxide Semiconductor (MVMOS) and a Low Voltage Metal Oxide Semiconductor (LVMOS) may be formed on the same Semiconductor substrate 10. In fig. 4, for the asymmetric HVMOS, only the structures on the source extension region 16a and the source region 16b sides, which are important for the present application, are shown. Herein, the asymmetric HVMOS is an asymmetric field effect transistor, the MVMOS is a first field effect transistor, and the LVMOS is a second field effect transistor. The voltage endurance capability of the MVMOS and the LVMOS is lower than that of the asymmetric HVMOS. The MVMOS and the LVMOS are both symmetrical field effect transistors, in the symmetrical field effect transistors, a source region and a drain region are symmetrically arranged relative to a source electrode, a channel region is arranged in a semiconductor substrate between the source region and the drain region, and no insulating region is arranged between the channel region and the source region and between the channel region and the drain region. The present invention is not limited thereto, and in another embodiment, either one of the MVMOS and LVMOS may also be an asymmetric field effect transistor.

Referring to fig. 4, each of the MVMOS and the LVMOS may include a P-type well region 30 formed in a surface region of the N-type semiconductor substrate 10, a high-concentration N-type source region 32 (serving as a second source region, the same below) and drain region 34 (serving as a second drain region, the same below) formed in the well region 30, an N-type extension region 36 extending from the source region 32 and the drain region 34 and having a lower doping concentration than the source region 32 and the drain region 34, a gate insulating layer 38 (serving as a second gate insulating layer, the same below) spanning from the source region 32 to the drain region 34, and a gate electrode 40 (serving as a second gate electrode, the same below) formed on the gate insulating layer 38 and made of polysilicon or the like. The MVMOS and LVMOS are insulated from other elements on the semiconductor substrate 10 by insulating regions 24.

In general, in the semiconductor device 100, the operating voltage range of the asymmetric HVMOS is about 25V to 40V, the operating voltage range of the MVMOS is about 5V to 7V, and the operating voltage range of the LVMOS is about 1.2V to 1.5V. In such an operating voltage range, the thickness of the gate insulating layer 38 of the MVMOS is, for example, about 10nm to 20nm, and the thickness of the gate insulating layer 38 of the LVMOS is, for example, 4nm or less. However, the operating voltage ranges of the asymmetric HVMOS, MVMOS, and LVMOS and the thicknesses of the respective gate insulating layers in the semiconductor device 100 are not limited thereto. That is, in the semiconductor device 100, the operating voltage range of the MVMOS may be lower than the operating voltage range of the asymmetric HVMOS, and the operating voltage range of the LVMOS may be lower than the operating voltage range of the MVMOS. In addition, in the semiconductor device 100, the gate insulating layer 38 of the MVMOS may be thinner than the gate insulating layer 26 of the asymmetric HVMOS, and the gate insulating layer 38 of the LVMOS may be thinner than the gate insulating layer 38 of the MVMOS.

As shown in fig. 4, in the semiconductor device 100, by providing the extension region 36 in the MVMOS, the electric field of the drain region 34 of the MVMOS can be relaxed. Similarly, by providing the extension region 36 in the LVMOS, the electric field of the drain region 34 of the LVMOS can be relaxed. In the semiconductor device 100, the gate length of the LVMOS is, for example, 100nm or less.

Example two: method for manufacturing semiconductor device

Fig. 5 and 6 illustrate a method of manufacturing the semiconductor device 100 according to the first embodiment. Fig. 5 and 6 are schematic cross-sectional structure diagrams corresponding to respective steps of a manufacturing method of the semiconductor device 100, and emphatically show respective portions constituting the semiconductor device 100, and dimensions in a plane direction and dimensions in a thickness direction of the respective portions may not be in proportion to actual dimensions.

A method of manufacturing the semiconductor device 100 including asymmetric HVMOS, MVMOS, and LVMOS, which are all n-channel, for example, will be described below. Wherein the silicon substrate is a p-type doped substrate as the first conductivity type. In the case of the semiconductor device 100 including the p-channel asymmetric HVMOS, it is only necessary to replace the first conductivity type with an n-type and the second conductivity type with a p-type.

First, in step S10, the drift region 12 and the guard ring region 14 are formed. The drift region 12 and the guard ring region 14 are formed by a dopant ion implantation process and an annealing diffusion process.

Specifically, a photoresist layer, which is an opening region corresponding to the drift region 12, may be formed on the surface of the semiconductor substrate 10 as a mask. The photoresist layer may be patterned by a photolithographic technique. In the case where the second conductive type is n-type, n-type dopant ions (phosphorus (P) or arsenic (As)) are implanted into the surface of the semiconductor substrate 10 using the photoresist layer As a mask. Among them, a two-step implantation method in which shallow ion implantation is combined with deep ion implantation using higher implantation energy than shallow ion implantation is preferable. For example, in shallow ion implantation, the energy of 200keV to 300keV and the energy of 1 × 10¹²Above and 2X 10¹²/cm²The following density implants phosphorus ions. In addition, in the deep region ion implantation, the energy of 600keV to 700keV and 4 x 10¹²Above and 6X 10¹²/cm²Ion implantation was performed at the following density. However, the implantation density, implantation depth, and the like of the dopant ions may be appropriately set according to the size and characteristics of the asymmetric HVMOS. After the ion implantation, the photoresist layer is removed.

In addition, a doping ion implantation process of the guard ring region 14 is also performed. Wherein a photoresist layer having an open region corresponding to the guard ring region 14 in the semiconductor substrate 10 is formed as a photoresist layerAnd (5) masking. The photoresist layer may be patterned by a photolithographic technique. In the case where the first conductivity type is p-type, p-type dopant ions (boron (B) or boron difluoride (BF) are implanted into the surface of the semiconductor substrate 10 using the photoresist layer as a mask₂)). Among them, a two-step implantation method in which shallow ion implantation is combined with deep ion implantation using higher implantation energy than shallow ion implantation is preferable. For example, in shallow ion implantation, the energy of 100keV to 150keV and the energy of 1 × 10¹²Above and 2X 10¹²/cm²The following density implants boron ions. In addition, in the deep region ion implantation, the energy of 300keV to 400keV and 1 × 10¹³Above and 2X 10¹³/cm²Ion implantation was performed at the following density. However, the implantation density, implantation depth, and the like of the dopant ions may be appropriately set according to the size and characteristics of the asymmetric HVMOS. After the ion implantation, the photoresist layer is removed.

After that, ion diffusion treatment is performed. After the doping ions are implanted into the drift region 12 and the guard ring region 14, respectively, the semiconductor substrate 10 is annealed (heated) at a high temperature of about 900 to 1300 ℃, so that the doping ions are diffused in the semiconductor substrate 10. The annealing treatment is performed, for example, at 1100 ℃ for 5 to 7 hours. However, the heating temperature and time may be appropriately set according to the size and characteristics of the asymmetric HVMOS. The diffused region of the second conductivity type dopant ions forms the drift region 12 and the diffused region of the first conductivity type dopant ions forms the guard ring region 14.

Next, in step S12, the insulating regions 22 and 24 are formed. The insulating regions 22 and 24 may be formed by an existing LOCOS process or STI process using a mask. In the LOCOS process, silicon oxide (SiO)₂) Using the film or silicon nitride (SiN) film as mask, and continuously supplying oxygen (O)₂) The semiconductor substrate 10 is heated under conditions to thermally oxidize the mask opening region of the surface of the semiconductor substrate 10, thereby forming the insulating region 22 or the insulating region 24. In the STI process, an etched trench may be formed in the opening region, and then the trench may be filled with an insulating film by a high density plasma CVD process or the like, and finally, by a chemical mechanical polishing method (c) (ii)CMP) planarizes the corresponding regions, thereby forming the insulating regions 22 or the insulating regions 24.

Then, in step S14, the gate insulating layer 26 is formed. The gate insulating layer 26 may be formed by Chemical Vapor Deposition (CVD) using Tetraethoxysilane (TEOS). In addition, the gate insulating layer 26 may also be formed by using oxygen (O)₂) Etc. oxygen-containing gas or nitrogen (N)₂) And the like by thermal oxidation of nitrogen-containing gas. The gate insulating layer 26 is formed to be treated by a photolithography process using a photoresist and an etching process, and the gate insulating layer 26 after the etching process is located on the surface of the semiconductor substrate 10 and covers a portion of the guard ring region 14 and the drift region 12 and a portion of the insulating region 22. When the operating voltage of the asymmetric HVMOS is about 25V to 40V, the thickness of the gate insulating layer 26 is, for example, 60nm or more and 100nm or less.

Next, in step S16, well regions 30 and gate insulating layers 38 of MVMOS and LVMOS are formed. The well regions 30 of the MVMOS and LVMOS are formed by a doping ion implantation process and an annealing diffusion process.

Specifically, on the surface of the semiconductor substrate 10, a photoresist layer with an opening region corresponding to the well region 30 of the LVMOS may be formed first to be used as a mask. The photoresist layer may be patterned by a photolithographic technique. Implanting p-type dopant ions (boron (B) or boron difluoride (BF) into the surface of the semiconductor substrate 10 using the photoresist layer as a mask₂)). In the ion implantation, boron ions are respectively doped at an energy of 150keV or more and 250keV or less and at an energy of 1.5X 10¹³Above and 2.5X 10¹³/cm²A density of 80keV or more and an energy of 120keV or less, and 4X 10¹²Above and 1 × 10¹³/cm²A density of 7keV to 20keV, and an energy sum of 1X 10¹³Above and 3 × 10¹³/cm²The following density implant. However, the implantation density, implantation depth, and the like of the dopant ions may be appropriately set according to the size and characteristics of the LVMOS. After the ion implantation, the photoresist layer is removed.

In addition, a photoresist layer having an opening region corresponding to the well region 30 of the MVMOS is formed to be used as a mask. The photoresist layer can be formed by photolithographyAnd (6) patterning. Implanting p-type dopant ions (boron (B) or boron difluoride (BF) into the surface of the semiconductor substrate 10 using the photoresist layer as a mask₂)). In the ion implantation, boron ions are respectively doped at an energy of 150keV or more and 250keV or less and at an energy of 1.5X 10¹³Above and 2.5X 10¹³/cm²A density of 80keV or more and an energy of 120keV or less, and 4X 10¹²Above and 1 × 10¹³/cm²A density of 20keV to 30keV, and an energy sum of 1X 10¹²Above and 3 × 10¹³/cm²The following density implant. However, the implantation density, implantation depth, and the like of the dopant ions may be appropriately set according to the size and characteristics of the LVMOS. After the ion implantation, the photoresist layer is removed.

After that, ion activation processing is performed. After doping ion implantation is performed on the well regions 30 of the MVMOS and the LVMOS, the doping ions in the semiconductor substrate 10 are activated by annealing (heating) the semiconductor substrate 10 at a high temperature of about 900 to 1100 ℃. The annealing treatment is performed at 1050 ℃ for 30 to 60 seconds, for example. However, the heating temperature and time may be appropriately set according to the size and characteristics of the MVMOS and LVMOS. The active region of first conductivity type doped ions forms the well region 30 of the MVMOS and LVMOS.

Subsequently, a gate insulating layer 38 of MVMOS and LVMOS is formed on the surface of the semiconductor substrate 10 over the region 30 forming region of MVMOS and LVMOS. The gate insulating layer 38 may be formed by using oxygen (O)₂) Etc. oxygen-containing gas or nitrogen (N)₂) And the like by thermal oxidation of nitrogen-containing gas. A gate insulating layer 38 of the LVMOS located on the well region 30 of the LVMOS and a gate insulating layer 38 of the MVMOS located on the well region 30b of the MVMOS are formed on the surface of the semiconductor substrate 10, respectively, by processing with a photolithography process using a photoresist and an etching process. For example, the pad oxide layer on the surface of the semiconductor substrate 10 may be removed, the gate insulating layer 38 of the MVMOS may be formed on the well region 30 of the MVMOS by thermal oxidation using the patterned photoresist layer as a mask, the photoresist layer may be removed, and then the gate insulating layer 38 of the LVMOS may be formed on the well region 30 of the LVMOS by thermal oxidation using the patterned photoresist layer as a mask. When the working voltage range of MVMOSThe gate insulating layer 38 of the MVMOS has a thickness of about 10nm to 20nm, for example, when the voltage is about 5V to 7V. When the operating voltage of the LVMOS is about 1.2V to 1.5V, the thickness of the LVMOS gate insulating layer 38 is, for example, 4nm or less.

Then, in step S18, the gate 28 of the asymmetric HVMOS and the gate 40 of the MVMOS and LVMOS are formed. In addition, the source extension region 16a of the asymmetric HVMOS and the extension region 36 of the MVMOS are also formed by ion implantation.

Specifically, the gate 28 is formed on the gate insulating layer 26 of the asymmetric HVMOS, and the gate 40 is formed on the gate insulating layer 38 of the MVMOS and LVMOS. The method for forming the gate electrode 28 and the gate electrode 40 is not particularly limited, but in the case of forming the gate electrode using polysilicon, a chemical vapor deposition method (CVD method) using a silicon-containing gas such as silane (SiH 4) may be used. When the gate electrode 28 and the gate electrode 40 are metal layers, a vapor deposition method, a sputtering method, a chemical vapor deposition method (CVD method), or the like can be used. The desired pattern for the asymmetric HVMOS gate 28 and MVMOS and LVMOS gates 40 is formed by processing with a photolithography process using photoresist and an etching process. At this time, the region of the gate insulating layer 26 is wider than the region of the gate electrode 28 by a margin distance X1 (e.g., a margin of overlap where the gate insulating layer 26 extends from the region of overlap with the gate electrode 28 to the source region side by a width of about 0.1 μm to 0.2 μm).

Subsequently, referring to fig. 5 and 6, an ion implantation process for the source extension region 16a of the asymmetric HVMOS and the extension region 36 of the MVMOS is performed. As shown in fig. 5, a photoresist layer R serving as a mask is first formed in a region other than the formation region of the source extension region 16a and MVMOS of the asymmetric HVMOS. The photoresist layer R may be patterned by a photolithography technique. In addition, when the second conductive type is N-type, N-type dopant ions (phosphorus (P) or arsenic (As)) are implanted into the surface of the semiconductor substrate 10 using the photoresist layer R As a mask. Wherein the phosphorus ions have a sum of energies of 60keV to 100keV of 1X 10¹³Above and 3 × 10¹³/cm²The following density implantation (S18 corresponds to the cross-sectional view in which N represents N-type dopant ion implantation). However, the implantation density and implantation depth of the dopant ions may be set according to the requirements of the source extension region 16a of the asymmetric HVMOS and the extension region 36 of the MVMOSIs suitably set. After the ion implantation, the photoresist layer R is removed.

Subsequently, an ion activation process is performed. After the doping ion implantation is performed for the source extension region 16a of the asymmetric HVMOS and the extension region 36 of the MVMOS, the doping ions in the semiconductor substrate 10 are activated by annealing (heating) the semiconductor substrate 10 at a high temperature of about 900 to 1050 ℃. The annealing treatment is performed for 10 to 30 seconds, for example. However, the heating temperature and time may be appropriately set according to the characteristics required for the source extension region 16a of the asymmetric HVMOS and the extension region 36 of the MVMOS. The doped ion activated region forms the source extension 16a of the asymmetric HVMOS and the extension 36 of the MVMOS.

Here, by appropriately setting the implantation energy of the dopant ions for the extension regions 36 of the MVMOS, the dopant ions can be simultaneously implanted in the semiconductor substrate 10 under the portion of the remaining edge of the gate insulating layer 26 that does not overlap with the gate electrode 28 by the distance X1. For example, by setting the implantation energy of the dopant ions for the extension region 36 of the MVMOS to 60keV or more and 100keV or less, the dopant ions can be implanted into the semiconductor substrate 10 through the gate insulating layer 26 which is thick (for example, 60nm to 100nm in thickness). Furthermore, by performing the ion activation process, a source extension region 16a of the asymmetric HVMOS may be formed in the guard ring region 14 at the same time as the extension region 36 of the MVMOS, the source extension region 16a extending from the end of the insulating region 24 close to the gate insulating layer 26 toward the channel region, and the remainder may extend by a distance X1 to extend to connect with the channel region under the gate electrode 28. As such, the number of manufacturing steps of the semiconductor device 100 may be reduced relative to separately implanting to form the source extension region 16a of the asymmetric HVMOS and the extension region 36 of the MVMOS, respectively. Further, since the source extension region 16a of the asymmetric HVMOS is formed in a Self-aligned (Self-alignment) manner with respect to the end portion on the source region side of the gate electrode 28, the accuracy of the arrangement of the source extension region 16a of the asymmetric HVMOS with respect to the gate length variation can be improved.

In the embodiment of the present invention, the source extension region 16a of the asymmetric HVMOS and the extension region 36 of the MVMOS have different functions. Specifically, the source extension region 16a of the asymmetric HVMOS serves as a region connecting the source region 16b with the channel region of the asymmetric HVMOS. Therefore, by providing the source extension region 16a of the asymmetric HVMOS, dispersion of the threshold voltage Vth of the asymmetric HVMOS can be reduced. In contrast, the extension region 36 of the MVMOS is used to relax the electric field of the drain region 34 of the MVMOS.

Next, in step S20, the extension regions 36 of the LVMOS are formed. In which a photoresist layer used as a mask is first formed in a region other than the formation region of the extension region 36 of the LVMOS. The photoresist layer may be patterned by a photolithographic technique. In addition, when the second conductive type is N-type, N-type dopant ions (phosphorus (P) or arsenic (As)) are implanted into the surface of the semiconductor substrate 10 using the photoresist layer As a mask. Wherein the arsenic ions have a sum of energies of 2keV to 4keV of 6 x 10¹⁴Above and 2X 10¹⁵/cm²The following density implant. However, the implantation density and implantation depth of the dopant ions, etc. may be set as appropriate according to the desired characteristics of the LVMOS extension region 36. After the ion implantation, the photoresist layer is removed. After that, ion activation processing is performed. After the implantation of the dopant ions in the extension regions 36 of the LVMOS, the dopant ions in the semiconductor substrate 10 are activated by spike annealing (heating) the semiconductor substrate 10 at a high temperature of about 1000 ℃ to 1050 ℃. However, the heating temperature and time may be set as appropriate according to the characteristics required for the extension region 36 of the LVMOS. The doped ion activated region forms an extension region 36 of the LVMOS.

Then, in step S22, spacers S made of an insulating material are formed on the sides of the gate 28 of the asymmetric HVMOS and the gate 40 of the MVMOS and LVMOS. The sidewalls S may be formed by Chemical Vapor Deposition (CVD) using Tetraethoxysilane (TEOS). In addition, the side wall S may be formed by using oxygen (O)₂) Etc. oxygen-containing gas or nitrogen (N)₂) And Chemical Vapor Deposition (CVD) of nitrogen-containing gas. The insulating material is etched so that only the portions of the insulating material on the side surfaces of the gate 28 of the asymmetric HVMOS and the gate 40 of the MVMOS and LVMOS remain, thereby forming the sidewall S.

Next, in step S24, the source and drain regions 16b and 18 of the asymmetric HVMOS, and the source and drain regions 32 and 34 of the MVMOS and LVMOS are formed. The source and drain regions 16b and 18 of the asymmetric HVMOS and the source and drain regions 32 and 34 of the MVMOS and LVMOS are formed by a dopant ion implantation process and an annealing diffusion process.

Specifically, a photoresist layer having an opening region corresponding to the source and drain regions 16b and 18 of the asymmetric HVMOS and the source and drain regions 32 and 34 of the MVMOS and LVMOS may be formed on the surface of the semiconductor substrate 10 to be used as a mask. The photoresist layer may be patterned by a photolithographic technique. In addition, when the second conductive type is n-type, n-type dopant ions (phosphorus (P) or arsenic (As)) are implanted into the surface of the semiconductor substrate 10 using the photoresist layer As a mask. Wherein the arsenic ions have a sum of energies of 20keV to 25keV of 2X 10¹⁵/cm²Above and 5 × 10¹⁵/cm²The following density implant. The phosphorus ions are mixed at an energy of 20keV to 30keV and 3X 10¹³Above and 1 × 10¹⁴/cm²The following density implantation (step S24 corresponds to nn in the cross-sectional view representing N-type dopant ion implantation). However, the implantation density, implantation depth, and the like of the dopant ions may be appropriately set according to the characteristics required for the source and drain regions 16b and 18 of the asymmetric HVMOS and the source and drain regions 32 and 34 of the MVMOS and LVMOS. After the ion implantation, the photoresist layer is removed.

In this manner, by simultaneously performing the doping ion implantation of the source region 16b and the drain region 18 of the asymmetric HVMOS and the source region 32 and the drain region 34 of the MVMOS and LVMOS, the manufacturing steps of the semiconductor device 100 may be reduced relative to the split implantation approach.

Then, in step S26, the tap region 20 of the asymmetric HVMOS is formed. The tap region 20 of the asymmetric HVMOS may be formed by a doping ion implantation process and an annealing diffusion process.

Specifically, a photoresist layer having an opening region corresponding to the tap region 20 of the asymmetric HVMOS may be formed on the surface of the semiconductor substrate 10 to serve as a mask. The photoresist layer may be patterned by a photolithographic technique. Implanting p-type dopant ions (boron (B) or boron difluoride (BF) into the surface of the semiconductor substrate 10 using the photoresist layer as a mask₂)). In the ion implantation, boron difluoride is doped at an energy of 5keV to 10keV and 2X 10¹⁵Above and 3 × 10¹⁵/cm²Ion implantation was performed at the following density. In addition, boronThe ions have an energy of 5keV to 10keV, for example, and 2X 10¹³Above and 5 × 10¹³/cm²The following density implant. However, the implantation density, implantation depth, and the like of the dopant ions may be appropriately set according to the size and characteristics of the asymmetric HVMOS. After the ion implantation, the photoresist layer is removed.

After that, ion activation processing is performed. After the implantation of the dopant ions in the tap region 20 of the asymmetric HVMOS, the dopant ions in the semiconductor substrate 10 are activated by spike annealing (heating) the semiconductor substrate 10 at a high temperature of about 1000 ℃ to 1050 ℃. The doped ion activated regions form source and drain regions 16b and 18 of the asymmetric HVMOS, source and drain regions 32 and 34 of the MVMOS and LVMOS, and tap region 20 of the asymmetric HVMOS.

Example three: semiconductor device with a plurality of transistors

Fig. 7 is a schematic cross-sectional view of a semiconductor device including asymmetric HVMOS, MVMOS, and LVMOS devices according to an embodiment of the invention. As shown in fig. 7, the semiconductor device 102 includes an asymmetric HVMOS structure and a symmetric MVMOS and LVMOS structure.

Fig. 7 shows only the structures on the source extension region 16a and the source region 16b side, which are important in the present embodiment, in the asymmetric HVMOS of the semiconductor device 102. Fig. 7 is a schematic diagram for explaining the basic structure of the semiconductor device 102, and emphasizes that the respective portions constituting the semiconductor device 102 are shown, and the planar direction dimensions and the thickness direction dimensions of the respective portions shown may not be in proportion to the actual dimensions.

In the present embodiment, the asymmetric HVMOS in the semiconductor device 102 includes a semiconductor substrate 10, a drift region 12, a guard ring region 14, a source extension region 16a, a source region 16b, a drain region 18, a tap region 20, an insulating region 22, an insulating region 24, a gate insulating layer 26, and a gate electrode 28.

The semiconductor device 102 differs from the semiconductor device 100 of the first embodiment mainly in the source extension region 16 a. In the present embodiment, the source extension region 16a constitutes a part of the source of the asymmetric HVMOS. The source extension regions 16a have the same conductivity type as the drift region 12, i.e., the second conductivity type. The doping concentration of the source extension region 16a is preferably 1 × 10¹⁷/cm³The aboveAnd 1X 10¹⁸/cm³The following. The source extension region 16a extends within the guard ring region 14 from beneath the region of the insulating region 24 to a region overlapping the gate insulating layer 26 and the gate electrode 28. That is, the source extension region 16a extends to the channel region under the gate 28.

In addition, in the Semiconductor device 102, in addition to the asymmetric HVMOS, a Medium Voltage Metal Oxide Semiconductor (MVMOS) and a Low Voltage Metal Oxide Semiconductor (LVMOS) are formed on the same Semiconductor substrate 10. Further, the MVMOS in the semiconductor device 102 is different from the MVMOS in the semiconductor device 100 in the first embodiment in type, the MVMOS in the semiconductor device 100 in the first embodiment is illustrated as an n-channel MOS device, the MVMOS in the semiconductor device 102 in the present embodiment is illustrated as a p-channel MOS device, and accordingly, the asymmetric HVMOS in the semiconductor device 102 in the first embodiment and the semiconductor device 100 in the present embodiment are illustrated as n-channel MOS devices. It is understood that in another embodiment, the semiconductor device of the present invention may also include both n-channel MVMOS and p-channel MVMOS.

In this embodiment, the MVMOS of the semiconductor device 102 includes a well region 30b (N-type) formed in the semiconductor substrate 10 (P-type), a source region 32b and a drain region 34b of high-concentration P-type formed in the well region 30b, a P-type extension region 36b extending from the source region 32b and the drain region 34b and having a concentration lower than that of the source region 32b and the drain region 34b, a gate insulating layer 38 spanning from the source region 32b to the drain region 34b, and a gate 40 formed on the gate insulating layer 38 and made of polysilicon or the like.

Example four: method for manufacturing semiconductor device

Fig. 8 and 9 show corresponding schematic cross-sectional views of a method of manufacturing the semiconductor device 102. Fig. 8 and 9 emphasize respective portions constituting the semiconductor device 102, and the planar direction size and the thickness direction size of the respective portions may not be proportional to actual sizes.

Hereinafter, description will be made on the case where the semiconductor substrate 10 is a p-type doped silicon substrate as the first conductivity type. In the case of the semiconductor device 102 including the p-channel asymmetric HVMOS, it is only necessary to replace the first conductivity type with an n-type and the second conductivity type with a p-type.

Referring to fig. 8, in the method of manufacturing the semiconductor device of the present embodiment, first, in step S30, the drift region 12 and the guard ring region 14 are formed. The drift region 12 and the guard ring region 14 are formed by a dopant ion implantation process and an annealing diffusion process. The process in this step is the same as the process in step S10 in the manufacturing method of the semiconductor device 100, and therefore, description thereof is omitted.

Next, in step S32, the insulating regions 22 and 24 are formed. The process in this step is the same as the process in step S12 in the manufacturing method of the semiconductor device 100, and therefore, description thereof is omitted.

Then, in step S34, the gate insulating layer 26 is formed. The process in this step is the same as the process in step S14 in the manufacturing method of the semiconductor device 100, and therefore, description thereof is omitted.

Next, in step S36, the well region 30 in the LVMOS is formed. In addition, the MVMOS well region 30b and the source extension region 16a of the asymmetric HVMOS are also ion-implanted.

Specifically, a photoresist layer with an opening region corresponding to the well region 30 of the LVMOS may be formed on the surface of the semiconductor substrate 10 to serve as a mask. The photoresist layer may be patterned by a photolithographic technique. Implanting P-type dopant ions (boron (B) or boron difluoride (BF) into the surface of the semiconductor substrate 10 using the photoresist layer as a mask₂)). In the ion implantation, boron ions are respectively doped at an energy of 150keV or more and 250keV or less and at an energy of 1.5X 10¹³Above and 2.5X 10¹³/cm²A density of 80keV or more and an energy of 120keV or less, and 4X 10¹²Above and 1 × 10¹³/cm²A density of 7keV to 20keV, and an energy sum of 1X 10¹³Above and 3 × 10¹³/cm²The following density implantation (step S36 corresponds to the cross-sectional view in which N represents N-type dopant ion implantation). However, the implantation density, implantation depth, and the like of the dopant ions may be appropriately set according to the size and characteristics of the LVMOS. After the ion implantation, the photoresist layer is removed.

In the removal ofAfter the photoresist layer defining the ion implantation range, a photoresist layer R having an opening region corresponding to the well region 30b of the MVMOS and the source extension region 16a of the asymmetric HVMOS is formed on the surface of the semiconductor substrate 10 to serve as a mask. The photoresist layer R may be patterned by a photolithography technique. A region of the photoresist layer R, which is a margin distance X1 for forming the gate insulating layer 26 described below, is also formed as an open region. N-type dopant ions (phosphorus (P) or arsenic (As)) are implanted into the surface of the semiconductor substrate 10 using the photoresist layer As a mask. In the ion implantation, phosphorus ions are respectively doped at energies of 400keV to 600keV and 1.5X 10¹³Above and 2.5X 10¹³/cm²A density of 200keV or more and 300keV or less, and an energy of 5X 10¹²Above and 1 × 10¹³/cm²A density of 60keV to 80keV, and an energy sum of 1X 10¹²Above and 3 × 10¹²/cm²Density implantation (P represents P-type dopant ion implantation) is described below. However, the implantation density and implantation depth of the doped ions, etc. may be set appropriately according to the characteristics required for the well region 30b of the MVMOS and the source extension region 16a of the asymmetric HVMOS. After the ion implantation, the photoresist layer R is removed.

Subsequently, an ion activation process is performed. After the doping ion implantation in the well region 30 of the LVMOS, the well region 30b of the MVMOS, and the source extension region 16a of the asymmetric HVMOS, the doping ion in the semiconductor substrate 10 is activated by annealing (heating) the semiconductor substrate 10 at a high temperature of about 900 to 1100 ℃. The annealing treatment is performed at 1050 ℃ for 30 to 60 seconds, for example. However, the heating temperature and time may be appropriately set according to the size and characteristics of the MVMOS and LVMOS. Thus, the well region 30 of LVMOS, the well region 30b of MVMOS and the source extension region 16a of asymmetric HVMOS are formed.

Under the implantation energy of the doping ions aiming at the well region 30b of the MVMOS, the gate insulating layer 26 with the thickness of 60 nm-100 nm of the asymmetric HVMOS is easy to penetrate, so that the doping ions can be implanted into the semiconductor substrate 10 below the gate insulating layer 26 with the remaining edge distance of X1. By further performing the ion activation process, a source extension region 16a of the asymmetric HVMOS may be formed in guard ring region 14 at the same time as well region 30b of the MVMOS, where source extension region 16a extends from an end near isolation region 24 toward the channel region, and may extend a remainder distance X1 to connect with the channel region under gate 28. As such, the fabrication steps of the semiconductor device 102 may be reduced relative to separately implanting to form the source extension regions 16a of the asymmetric HVMOS and the well regions 30b of the MVMOS, respectively.

Then, in step S38, the gate insulating layer 38 of the MVMOS and LVMOS is formed. In addition, a gate 28 for asymmetric HVMOS and a gate 40 for MVMOS and LVMOS are also formed.

A gate insulating layer 38 is formed on the surface of the semiconductor substrate 10 over the region 30b for MVMOS and the region 30 for LVMOS. The gate insulating layer 38 may be formed by using oxygen (O)₂) Etc. oxygen-containing gas or nitrogen (N)₂) And the like by thermal oxidation of nitrogen-containing gas. A gate insulating layer 38 of the LVMOS located on the well region 30 of the LVMOS and a gate insulating layer 38 of the MVMOS located on the well region 30b of the MVMOS are formed on the surface of the semiconductor substrate 10, respectively, by processing with a photolithography process using a photoresist and an etching process. For example, the pad oxide layer on the surface of the semiconductor substrate 10 may be removed, the gate insulating layer 38 of the MVMOS may be formed by thermal oxidation using the patterned photoresist layer as a mask, the photoresist layer may be removed, and then the gate insulating layer 38 of the LVMOS may be formed by thermal oxidation using the patterned photoresist layer as a mask.

When the operating voltage range of the MVMOS is about 5V to 7V, the thickness of the gate insulating layer 38 of the MVMOS is, for example, about 10nm to 20 nm. When the operating voltage of the LVMOS is about 1.2V to 1.5V, the thickness of the gate insulating layer 38 of the LVMOS is, for example, 4nm or less.

In addition, step S38 also forms gate 28 of asymmetric HVMOS and gate 40 of MVMOS and LVMOS. Gate 28 is formed on gate insulating layer 26 of asymmetric HVMOS, and gates 40 of MVMOS and LVMOS are formed on gate insulating layers 38 of MVMOS and LVMOS, respectively. The formation method of the gate electrode 28 and the gate electrode 40 is not particularly limited, but in the case of forming the gate electrode using polysilicon, Silane (SiH) may be used₄) And Chemical Vapor Deposition (CVD) of a silicon-containing gas. When the gate 28 and the gate 40 are metalIn the case of the layer, a vapor deposition method, a sputtering method, a chemical vapor deposition method (CVD method), or the like can be used. The regions required for the gate 28 of the asymmetric HVMOS and the gate 40 of the MVMOS and LVMOS are formed by processing with a photolithography process using a photoresist and an etching process. At this time, the region of the gate insulating layer 26 is wider than the region of the gate electrode 28 by a margin distance X1 (e.g., a margin of overlap where the gate insulating layer 26 extends from the region of overlap with the gate electrode 28 to the source region side by a width of about 0.1 μm to 0.2 μm).

Next, in step S40, extension regions 36b of MVMOS and extension regions 36 of LVMOS are formed.

In this case, ion implantation is performed on the extension region 36b of the MVMOS. Specifically, a photoresist layer used as a mask is formed in a region other than the formation region of the extension region 36 of the MVMOS. The photoresist layer may be patterned by a photolithographic technique. Then, using the photoresist layer as a mask, p-type doped ions (boron (B) or boron difluoride (BF) are implanted into the surface of the semiconductor substrate 10₂)). In the ion implantation, boron ions are made to have a sum of energies of 15keV to 25keV of 1X 10¹³Above and 3 × 10¹³/cm²Ion implantation was performed at the following density. However, the implantation density and implantation depth of the dopant ions, etc. may be set as appropriate according to the desired characteristics of the extension region 36b of the MVMOS. After the ion implantation, the photoresist layer is removed.

Ion implantation is also performed on the LVMOS extension region 36. Specifically, a photoresist layer used as a mask is formed in a region other than the formation region of the extension region 36 of the LVMOS. The photoresist layer may be patterned by a photolithographic technique. Then, n-type dopant ions (phosphorus (P) or arsenic (As)) are implanted into the surface of the semiconductor substrate 10 using the photoresist layer As a mask. Wherein the arsenic ions have a sum of energies of 2keV to 4keV of 6 x 10¹⁴/cm²Above and 2X 10¹⁵/cm²The following density implant. However, the implantation density and implantation depth of the dopant ions, etc. may be set as appropriate according to the desired characteristics of the LVMOS extension region 36. After the ion implantation, the photoresist layer is removed.

After that, ion activation processing is performed. After the implantation of the dopant ions into the extension regions 36b of the MVMOS and the extension regions 36 of the LVMOS is completed, the dopant ions in the semiconductor substrate 10 are activated by spike annealing (heating) the semiconductor substrate 10 at a high temperature of about 1000 ℃ to 1050 ℃. However, the heating temperature and time may be appropriately set according to the characteristics required for the extension regions 36b of the MVMOS and the extension regions 36 of the LVMOS. The doped ion activated regions form extension regions 36b for MVMOS and extension regions 36 for LVMOS.

Then, in step S42, spacers S made of an insulating material are formed on the sides of the gate 28 of the asymmetric HVMOS and the gate 40 of the MVMOS and LVMOS. The processing in this step is the same as the processing in step S22 in the manufacturing method of the semiconductor device 100 of the second embodiment, and therefore, description thereof is omitted.

Next, in step S44, an ion implantation process for forming the source and drain regions 16b and 18 of the asymmetric HVMOS and the source and drain regions 32 and 34 of the LVMOS is performed.

Specifically, a photoresist layer R having an opening region corresponding to the source region 16b and the drain region 18 of the asymmetric HVMOS and the source region 32 and the drain region 34 of the LVMOS is formed on the surface of the semiconductor substrate 10 to be used as a mask (see step S44 in fig. 9). The photoresist layer may be patterned by a photolithographic technique. Then, using the photoresist layer As a mask, N-type dopant ions (phosphorus (P) or arsenic (As)) are implanted into the surface of the semiconductor substrate 10 (step S44 represents N-type dopant ion implantation corresponding to nn in the cross-sectional view). Wherein the arsenic ions have a sum of energies of 20keV to 25keV of 2X 10¹⁵/cm²Above and 5 × 10¹⁵/cm²The following density implant. Phosphorus ions are mixed at an energy of 20keV to 30keV and 3X 10¹³Above and 1 × 10¹⁴/cm²The following density implant. However, the implantation density, implantation depth, and the like of the dopant ions may be appropriately set according to the characteristics required for the source and drain regions 16b and 18 of the asymmetric HVMOS and the source and drain regions 32 and 34 of the LVMOS. After the ion implantation, the photoresist layer R is removed.

Then, in step S46, an ion implantation process for forming the tap region 20 of the asymmetric HVMOS and the source and drain regions 32b and 34b of the MVMOS is performed.

Particularly on the surface of the semiconductor substrate 10The tap region 20 of the asymmetric HVMOS and the regions corresponding to the source region 32b and the drain region 34b of the MVMOS are the photoresist layer R of the open region to be used as a mask. The photoresist layer may be patterned by a photolithographic technique. In addition, P-type dopant ions (boron (B) or boron difluoride (BF) are implanted into the surface of the semiconductor substrate 10 using the photoresist layer as a mask₂)). In the ion implantation, boron difluoride is doped at an energy of 5keV to 10keV and 2X 10¹⁵Above and 3 × 10¹⁵/cm²Ion implantation was performed at the following density. Further, the boron ions are, for example, at an energy sum of 5keV to 10keV of 2X 10¹³Above and 5 × 10¹³/cm²The following density implant. However, the implantation density, implantation depth, and the like of the dopant ions may be appropriately set according to the characteristics required for the tap region 20 of the asymmetric HVMOS and the source and drain regions 32b and 34b of the MVMOS. After the ion implantation, the photoresist layer is removed.

Subsequently, an ion activation process is performed. In this embodiment, after the implantation of the dopant ions into the source region 16b and the drain region 18 of the asymmetric HVMOS, the source region 32 and the drain region 34 of the LVMOS, the tap region 20 of the asymmetric HVMOS, and the source region 32b and the drain region 34b of the MVMOS is completed, the dopant ions in the semiconductor substrate 10 are activated by performing spike annealing (heating) on the semiconductor substrate 10 at a high temperature of about 1000 ℃ to 1050 ℃. However, the heating temperature and time may be set as appropriate according to the desired characteristics of the source and drain regions 16b and 18, LVMOS source and drain regions 32 and 34, HVMOS tap region 20, and MVMOS source and drain regions 32b and 34b of the asymmetric HVMOS. The doped ion activated regions form HVMOS source and drain regions 16b and 18, LVMOS source and drain regions 32 and 34, HVMOS tap region 20, and MVMOS source and drain regions 32b and 34 b.

Fifth embodiment: characteristics of semiconductor device

The source region concentration distribution of the asymmetric HVMOS in the semiconductor device 200 and the source region concentration distribution of the asymmetric HVMOS in the semiconductor device 100 according to an embodiment of the present invention as shown in fig. 14 may be simulated. In these simulations, for example, the gate length of the LVMOS is set to 100nm or less, and ion implantation of the source region 32 and the drain region 34 of the LVMOS is performed using a reduced ion implantation energy. Simulation results show that in the source region of the asymmetric HVMOS structure employed in the semiconductor device 200, for the asymmetric HVMOS, the dopant did not diffuse sufficiently to the portion of the gate insulating layer 26 that is beyond the width with respect to the gate electrode 28 (corresponding to the remainder distance X1) and to the channel region under the gate electrode 28, regardless of whether the gate insulating layer 26 was 77nm or 87nm thick. In contrast, in the asymmetric HVMOS structure employed by the semiconductor device 100 of the embodiment of the invention, regardless of whether the thickness of the gate insulating layer 26 is 77nm or 87nm, by providing the source extension region 16a, the electric fields in the source extension region 16a and the source region 16b are expanded, thereby enabling the dopants to sufficiently diffuse, and pass through the excess width portion of the gate insulating layer 26 with respect to the gate electrode 28 (corresponding to the margin distance X1) and reach the channel region under the gate electrode 28.

Fig. 10 is a simulation result of the relationship between the gate-source voltage (Vgs) and the drain-source current (Ids) of the asymmetric HVMOS in the semiconductor device of the related art at different gate insulating layer thicknesses (T1). Fig. 11 is a simulation result of the relationship between the gate-source voltage and the drain-source current of the asymmetric HVMOS in the semiconductor device according to an embodiment of the invention at different gate insulating layer thicknesses. Referring to fig. 14, fig. 10 illustrates a relationship between a gate-source voltage (Vgs) and a source-drain current (Ids) in an asymmetric HVMOS structure employed by the semiconductor device 200. Referring to fig. 1, fig. 11 shows a relationship between a gate-source voltage (Vgs) and a drain-source current (Ids) in the asymmetric HVMOS structure employed in the semiconductor device 100 of the first embodiment.

As shown in fig. 10, in the conventional asymmetric HVMOS structure, when the thickness of the gate insulating layer 26 is increased from 77nm to 87nm, the relationship between the gate-source voltage (Vgs) and the drain-source current (Ids) is greatly changed. In contrast, as shown in fig. 11, in the asymmetric HVMOS structure employed in the semiconductor device 100 of the embodiment of the invention, when the thickness of the gate insulating layer 26 is increased from 77nm to 87nm, the magnitude of variation in the relationship between the gate-source voltage (Vgs) and the drain-source current (Ids) is smaller than that of the existing asymmetric HVMOS structure.

Fig. 12 is a simulation result of threshold voltage variation with HVMOS gate insulator thickness. Fig. 13 is a simulation result of drain-source current as a function of HVMOS gate insulator thickness. Fig. 12, in conjunction with fig. 14 and fig. 1, shows the relationship between the thickness of the gate insulating layer 26 of the asymmetric HVMOS and the threshold voltage (Vth) in the semiconductor device 100 of the embodiment of the present invention and the conventional semiconductor device 200. Fig. 13 shows the relationship between the thickness of the gate insulating layer 26 of the asymmetric HVMOS and the drain-source current (Ids) in the conventional semiconductor device 200 and the semiconductor device 100 of the embodiment of the present invention.

As shown in fig. 12, the semiconductor device 100 of the present embodiment employs an asymmetric HVMOS structure having a source extension region in which the magnitude of variation in threshold voltage (Vth) with variation in thickness of the gate insulating layer 26 is smaller than that in the conventional asymmetric HVMOS structure. That is, in the semiconductor device of the embodiment of the present invention, the threshold voltage (Vth) is less affected by the thickness of the gate insulating layer 26, and becomes more stable than the conventional asymmetric HVMOS structure.

Further, as shown in fig. 13, the magnitude of the variation of the drain-source current (Ids) with the variation of the thickness of the gate insulating layer 26 in the semiconductor device 100 of the embodiment of the present invention is smaller than that in the conventional asymmetric HVMOS structure. That is, in the semiconductor device of the embodiment of the present invention, the drain-source current (Ids) is less affected by the thickness of the gate insulating layer 26, and becomes more stable than the conventional asymmetric HVMOS structure.

In addition, studies have shown that the semiconductor device employing the embodiment of the present invention can reduce dispersion of the threshold voltage (Vth) and the drain-source current (Ids) of each element in the semiconductor device affected by the dispersion of the margin distance X1, in addition to the reduction in the degree of influence by the thickness of the gate insulating layer 26.

As described above, with the semiconductor device described in the embodiment of the present invention, the characteristics of the semiconductor device including the asymmetric HVMOS can be improved. It is also possible to reduce dispersion of the threshold voltage (Vth) and the source-drain current (Ids) of each element in the semiconductor device including the asymmetric HVMOS, thereby making the device performance more stable. The structure is particularly effective for the structure with the LVMOS gate length of less than 100 nm. In addition, the method for manufacturing the semiconductor device according to the embodiment of the present invention can also help to simplify the manufacturing process of the semiconductor device including the asymmetric HVMOS, MVMOS and LVMOS having the above-described excellent characteristics, thereby reducing the manufacturing cost.

It should be noted that the embodiments in the present specification are described in a progressive manner, each part is focused on differences from the previous part, and the parts which are the same or similar to each other can be understood by referring to each other.

The above description is only for the purpose of describing the preferred embodiments of the present invention and is not intended to limit the scope of the claims of the present invention, and any person skilled in the art can make possible the variations and modifications of the technical solutions of the present invention using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention, and therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention belong to the protection scope of the technical solutions of the present invention.

Claims (15)

1. A semiconductor device comprising a semiconductor substrate of a first conductivity type and an asymmetric field effect transistor disposed on the semiconductor substrate, the asymmetric field effect transistor comprising:

a first source region and a first drain region formed in the semiconductor substrate and having a second conductivity type opposite to the first conductivity type;

the first source region and the first drain region are positioned at two sides of the first grid electrode, and the channel region is positioned in the semiconductor substrate right below the first grid electrode; an insulating region is arranged between the channel region and the first drain region, so that the first source region and the first drain region are asymmetric relative to the first gate, the first drain region is arranged at a position far away from the first gate compared with the first source region, the thickness of the first gate insulating layer is more than 60nm, the first gate insulating layer comprises an extended insulating part, the extended insulating part is a part of the first gate insulating layer, which is wider than the first gate at one side of the first source region by a margin distance, and the margin distance is greater than the width of a side wall covering the side face of the first gate; the first source region and a source drain region of another field effect transistor formed on the basis of the semiconductor substrate have the same injection energy, the injection energy of the source drain region is not enough to enable injected ions to penetrate through the extension insulating part adjacent to the side wall, and a gap is formed between projections of the first source region and the side wall in the upper surface of the semiconductor substrate; and the number of the first and second groups,

and the source electrode extension region is formed in the semiconductor substrate and has a second conductive type, the injection energy of the source electrode extension region is greater than that of the source electrode extension region, and the source electrode extension region is positioned below the extension insulating part and is connected with the first source region and the channel region.

2. The semiconductor device of claim 1, wherein the asymmetric field effect transistor includes a drift region disposed within the semiconductor substrate and having a second conductivity type; wherein the first drain region is disposed in the drift region, and the source extension region is shallower than the drift region relative to a top surface of the semiconductor substrate.

3. The semiconductor device according to claim 1, wherein the insulating region extends from inside the semiconductor substrate to a surface, and a region where the first gate insulating layer overlaps with the first gate electrode covers a part of the insulating region.

4. The semiconductor device according to claim 1, wherein a thickness of the first gate insulating layer is 100nm or less.

5. The semiconductor device of claim 1, wherein said source extension region is formed within a first well region of a first conductivity type located within said semiconductor substrate, said first source region being formed within said source extension region.

6. The semiconductor device according to claim 1, wherein an operating voltage of the asymmetric field-effect transistor is 25V or more and 40V or less.

7. The semiconductor device of claim 1, further comprising an additional field effect transistor disposed on the semiconductor substrate, the additional field effect transistor comprising a second gate insulating layer on the semiconductor substrate, a second gate electrode on the second gate insulating layer, and a second source region and a second drain region disposed in the semiconductor substrate, the second gate insulating layer corresponding to the additional field effect transistor being thinner than the first gate insulating layer corresponding to the asymmetric field effect transistor.

8. The semiconductor device according to claim 7, wherein the additional field effect transistor comprises at least one symmetric field effect transistor, the second source region and the second drain region corresponding to each of the symmetric field effect transistors are symmetric with respect to the corresponding second gate, and a gate length of at least one of the symmetric field effect transistors is 100nm or less.

9. The semiconductor device according to claim 7, wherein the another field effect transistor includes a first field effect transistor and a second field effect transistor, wherein a thickness of the second gate insulating layer corresponding to the first field effect transistor is 10nm or more and 20nm or less, and a thickness of the second gate insulating layer corresponding to the second field effect transistor is less than 4 nm.

10. The semiconductor device according to claim 9, wherein the second source region and the second drain region corresponding to the first field effect transistor each have the first conductivity type or the second conductivity type, and wherein the second source region and the second drain region corresponding to the second field effect transistor each have the second conductivity type.

11. A method for manufacturing a semiconductor device according to any one of claims 1 to 10, comprising:

providing a semiconductor substrate; and the number of the first and second groups,

forming a first field effect transistor and the asymmetric field effect transistor on the semiconductor substrate, wherein the first field effect transistor comprises a second source region and a second drain region which are formed in the semiconductor substrate, a second gate insulating layer which is formed on the semiconductor substrate and a second gate electrode which is formed on the second gate insulating layer, the second source region and the second drain region of the first field effect transistor are of a second conductivity type, and the thickness of the second gate insulating layer of the first field effect transistor is thinner than that of the first gate insulating layer of the asymmetric field effect transistor;

after the first grid electrode and the second grid electrode are formed and before the first source region, the first drain region, the second source region and the second drain region are formed, extension regions are formed in the semiconductor substrate on two sides of the second grid electrode through ion implantation and heat treatment, and meanwhile, the source extension regions are formed in the semiconductor substrate.

12. A method for manufacturing a semiconductor device according to any one of claims 1 to 10, comprising:

providing a semiconductor substrate; and the number of the first and second groups,

forming a first field effect transistor and the asymmetric field effect transistor on the semiconductor substrate, wherein the first field effect transistor comprises a well region which is formed in the semiconductor substrate and has a second conductivity type, a second source region and a second drain region which are formed in the well region, a second gate insulating layer which is formed on the semiconductor substrate, and a second gate which is formed on the second gate insulating layer, and the thickness of the second gate insulating layer of the first field effect transistor is thinner than that of the first gate insulating layer of the asymmetric field effect transistor;

before the first grid and the second grid are formed, the well region is formed in the semiconductor substrate below the second grid through ion implantation and heat treatment, and the source extension region is formed in the semiconductor substrate at the same time.

13. The manufacturing method according to claim 11 or 12, further comprising:

forming a second field effect transistor on the semiconductor substrate, wherein the second field effect transistor comprises a source region and a drain region formed in the semiconductor substrate, a gate insulating layer formed on the semiconductor substrate and a gate electrode formed on the gate insulating layer, the gate insulating layer of the second field effect transistor is thinner than the second gate insulating layer corresponding to the first field effect transistor, and the source region and the drain region of the second field effect transistor have a second conductivity type;

and the first source region and the first drain region of the asymmetric field effect transistor and the source region and the drain region of the second field effect transistor are formed by the same ion implantation and heat treatment process.

14. The manufacturing method according to claim 13, wherein a gate length of the second field effect transistor is 100nm or less.

15. The manufacturing method according to claim 11 or 12, wherein a thickness of the first gate insulating layer is 60nm or more and 100nm or less, and a thickness of the second gate insulating layer is 10nm or more and 20nm or less.

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