KR20010073549A - Semiconductor apparatus forming method - Google Patents
Semiconductor apparatus forming method Download PDFInfo
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- KR20010073549A KR20010073549A KR1020000002167A KR20000002167A KR20010073549A KR 20010073549 A KR20010073549 A KR 20010073549A KR 1020000002167 A KR1020000002167 A KR 1020000002167A KR 20000002167 A KR20000002167 A KR 20000002167A KR 20010073549 A KR20010073549 A KR 20010073549A
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- 238000000034 method Methods 0.000 title claims abstract description 33
- 239000004065 semiconductor Substances 0.000 title claims abstract description 28
- 150000002500 ions Chemical class 0.000 claims abstract description 50
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 12
- 229920005591 polysilicon Polymers 0.000 claims description 11
- 238000000206 photolithography Methods 0.000 claims description 10
- 238000002955 isolation Methods 0.000 claims description 3
- 238000000059 patterning Methods 0.000 claims description 2
- 239000002019 doping agent Substances 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 abstract description 10
- 230000006866 deterioration Effects 0.000 abstract description 4
- 238000001259 photo etching Methods 0.000 abstract 2
- 229920002120 photoresistant polymer Polymers 0.000 description 18
- 238000010438 heat treatment Methods 0.000 description 6
- 230000003647 oxidation Effects 0.000 description 6
- 238000007254 oxidation reaction Methods 0.000 description 6
- 239000007924 injection Substances 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 210000004185 liver Anatomy 0.000 description 1
- 230000004807 localization Effects 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823892—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0928—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising both N- and P- wells in the substrate, e.g. twin-tub
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Abstract
Description
본 발명은 반도체장치 제조방법에 관한 것으로, 특히 0.35㎛기술에서 로직을 구성하는 일반 트랜지스터와 고전압용 트랜지스터를 동시에 형성하면서 그 형성순서를 바꾸어 공정을 단순화하면서도 과도한 확산에 의한 고전압 트랜지스터의 특성열화를 방지하기에 적당하도록 한 반도체장치 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device. In particular, in the 0.35 占 퐉 technology, a general transistor and a high voltage transistor constituting logic are simultaneously formed, and the formation order thereof is changed to simplify the process, while preventing deterioration of characteristics of the high voltage transistor due to excessive diffusion. The present invention relates to a method for manufacturing a semiconductor device suitable for the following.
종래 반도체장치 제조방법의 일실시예를 도 1a 내지 도 1e의 수순단면도를 참고하여 설명하면 다음과 같다.An embodiment of a conventional semiconductor device manufacturing method is described below with reference to the procedure cross-sectional view of FIGS.
반도체기판(1) 상부에 차례로 엔웰(2), 고농도엔웰(3), 고농도피웰(4), 피웰(5)을 각각 정의하여 형성하는 제 1공정과; 상기 형성한 고농도피웰(4)의 상부에서 고전압트랜지스터의 드리프트구조가 형성될 영역만 정의한 후 그 부분에 엔형이온을 주입하여 엔형도핑영역(6)을 형성하고, 고농도엔웰(3)의 상부에서 고전압트랜지스터의 드리프트구조가 형성될 영역만 정의한 후 그 부분에 피형이온을 주입하여 피형도핑영역(7)을 형성한 다음 열처리하여 상기 이온을 확산시켜 드리프트영역을 형성하고, 상기 각 웰(2,3,4,5) 간을 격리하기 위하여 각 웰(2,3,4,5)의 이격부분에 이온을 주입한 후 상기 각 웰(2,3,4,5)의 이격부분을 국부산화하여 국부산화영역(8)을 형성하는 제 2공정과; 상기 형성한 구조 상부전면에 고전압 트랜지스터에 적당한 높이로 제 1게이트산화막(9)을 형성한 후 형성될 트랜지스터의 문턱전압을 결정하기 위해서 각 웰(2,3,4,5) 상에 이온을 주입한 다음, 로직이 형성될 영역상의제 1게이트산화막(9)을 사진식각공정을 통해 제거한 후 상기 구조 상부전면에 얇은 제 2게이트산화막(10)을 형성하는 제 3공정과; 상기 형성한 제 2게이트산화막(10) 상부에 도핑된 폴리실리콘막(11)을 형성하고, 상기 각 웰(2,3,4,5) 상부에 게이트를 형성하도록 상기 폴리실리콘막(11) 및 제 2게이트산화막(10), 제 1게이트산화막(9)을 사진식각공정을 통해 패터닝 한 후 상기 형성한 각 게이트중 로직영역의 게이트를 하드마스크로 로직영역의 각 웰(2,5)의 특성에 맞는 이온을 주입하여 저농도 소스/드레인영역(12,13)을 형성하는 제 4공정과; 상기 형성한 구조의 상부전면에 절연막을 형성하고 이를 식각하여 각 게이트의 측면에 게이트측벽(14)을 형성한 후 상기 게이트측벽(14)을 포함한 게이트를 하드마스크로 로직영역 및 고전압영역의 각 웰(2,3,4,5)에 그 특성에 맞는 이온을 주입하여 고농도 소스/드레인영역(15,16)을 형성하는 제 5공정으로 이루어진다.A first step of defining and forming an enwell (2), a highly concentrated enwell (3), a highly concentrated pewell (4), and a pewell (5) on top of the semiconductor substrate (1), respectively; After defining only the region where the drift structure of the high voltage transistor is to be formed in the upper portion of the high concentration pwell 4, the N-type doping region 6 is formed by injecting N-type ions into the portion, and in the upper portion of the high concentration enwell 3 After defining only the region where the drift structure of the high voltage transistor is to be formed, implant the ion into the portion to form the doped region 7 and then heat treatment to diffuse the ions to form the drift region, each of the wells (2, 3) In order to isolate the liver, the ions are implanted into the wells 2,3,4,5 and then localized by the localization of the wells of the wells 2,3,4,5. A second step of forming the oxidation region 8; After forming the first gate oxide layer 9 at a suitable height for the high voltage transistor on the upper surface of the formed structure, ions are implanted into each well 2, 3, 4, 5 to determine the threshold voltage of the transistor to be formed. A third process of removing the first gate oxide film 9 on the region where logic is to be formed through a photolithography process and then forming a thin second gate oxide film 10 on the upper surface of the structure; The polysilicon layer 11 and a doped polysilicon layer 11 formed on the formed second gate oxide layer 10, and a gate formed on each of the wells 2, 3, 4, and 5; After the second gate oxide film 10 and the first gate oxide film 9 are patterned through a photolithography process, characteristics of the wells 2 and 5 of the logic regions are formed using hard gates of the logic regions of the formed gates. A fourth step of forming the low concentration source / drain regions 12 and 13 by implanting ions suitable for the ions; An insulating film is formed on the upper surface of the formed structure and etched to form a gate side wall 14 on the side of each gate, and then the gate including the gate side wall 14 is hard masked in each well of a logic region and a high voltage region. A fifth process is performed to form the highly concentrated source / drain regions 15 and 16 by implanting ions suitable to the characteristics into (2, 3, 4, 5).
먼저, 도 1a에 도시한 바와 같이 반도체기판(1) 상부에 차례로 엔웰(2), 고농도엔웰(3), 고농도피웰(4), 피웰(5)을 각각 정의하여 형성하는데, 엔웰(2)이 형성될 영역의 반도체기판(1)이 드러나도록 감광막패턴을 형성한 후 엔형이온을 도핑하고, 잔류하는 감광막패턴을 제거한 후 고농도엔웰(3)이 형성될 영역의 반도체기판(1)이 드러나도록 감광막패턴을 형성한 다음 고농도엔형이온을 도핑한다.First, as shown in FIG. 1A, an enwell 2, a high concentration enwell 3, a high concentration pewell 4, and a pewell 5 are defined on the semiconductor substrate 1 in order, and the enwell 2 is formed. After forming the photoresist pattern so that the semiconductor substrate 1 of the region to be formed is exposed, the semiconductor substrate 1 of the region where the high concentration N well 3 is to be formed is exposed after doping the N-type ion, removing the remaining photoresist pattern. After the photoresist pattern is formed, the doped high ene ions are doped.
그리고, 상기 잔류하는 감광막패턴을 제거하고, 고농도피웰(4)이 형성될 영역의 반도체기판(1)이 드러나도록 감광막패턴을 형성한 후 고농도피형이온을 도핑하고, 잔류하는 감광막패턴을 제거한 다음, 피웰(5)이 형성될 영역의 반도체기판(1)이 드러나도록 감광막패턴을 형성하고 피형이온을 도핑한 후 감광막패턴을 제거하고,상기 웨이퍼를 열처리하여 상기 주입된 이온들이 확산하면서 웰(2,3,4,5)을 형성하도록 한다.Then, the remaining photoresist pattern is removed, the photoresist pattern is formed to expose the semiconductor substrate 1 in the region where the high concentration pwell 4 is to be formed, and then the doped photoresist pattern is removed, and the remaining photoresist pattern is removed. Forming a photoresist pattern so that the semiconductor substrate 1 in the region where the pwell 5 is to be formed is exposed, doping the ion and removing the photoresist pattern, and heat-treating the wafer to diffuse the implanted ions into the wells 2, 3,4,5).
그 다음, 도 1b에 도시한 바와 같이 상기 형성한 고농도피웰(4)의 상부에서 고전압트랜지스터의 드리프트구조가 형성될 영역만 오픈 되도록 감광막패턴으로 정의하여 그 부분에 엔형이온을 주입하여 엔형도핑영역(6)을 형성하고, 상기 감광막패턴을 제거한다.Next, as shown in FIG. 1B, the photoresist pattern is defined to open only the region where the drift structure of the high voltage transistor is to be formed at the upper portion of the high concentration pwell 4, and the N-type ions are injected into the portion to form the N-type doping region ( 6) is formed and the photoresist pattern is removed.
그리고, 상기 고농도엔웰(3)의 상부에서 고전압트랜지스터의 드리프트구조가 형성될 영역만 감광막패턴으로 정의하여 그 부분에 피형이온을 주입하여 피형도핑영역(7)을 형성한 후 상기 웨이퍼를 1100℃에서 30분간 열처리하여 상기 각 도핑영역(6,7)에 주입된 이온을 확산시켜 드리프트영역을 형성한다.Then, only the region where the drift structure of the high voltage transistor is to be formed on the high concentration N well 3 is defined as a photoresist pattern, and the implanted ion is injected into the portion to form the implanted doping region 7, and then the wafer is formed at 1100 ° C. Heat treatment for 30 minutes at to diffuse the ions implanted into each of the doped regions (6,7) to form a drift region.
그리고, 상기 각 웰(2,3,4,5) 간을 격리하기 위하여 각 웰(2,3,4,5)의 이격부분에 이온을 주입하는데, 피웰(5)과 엔웰(2) 사이에는 엔형이온을 주입하고, 엔웰(2)과 고농도피웰(4) 사이에는 고농도엔형이온을 주입하며, 고농도피웰(4)과 고농도엔웰(3) 사이에는 고농도피형이온을 주입하여 인접한 소자간의 누설전류를 차단할 수 있도록 한 다음, 상기 각 웰(2,3,4,5)간의 이격부분을 국부산화하여 국부산화영역(8)을 형성한다.In order to isolate between the wells 2, 3, 4, and 5, ions are implanted into spaced portions of each of the wells 2, 3, 4, and 5, between the pewells 5 and the enwells 2. Injecting En-type ions, Injecting high-energy ions between Enwell (2) and High-concentration pewell (4), Injecting high-concentration coronary ions between High-concentration pewell (4) and High-concentration enwell (3) Leakage between adjacent devices After the current is cut off, the spaced portions between the wells 2, 3, 4 and 5 are locally oxidized to form a local oxidation region 8.
그 다음, 도 1c에 도시한 바와 같이 상기 형성한 구조 상부전면에 고전압 트랜지스터에 적당한 높이로 제 1게이트산화막(9)을 형성하는데, 450Å~550Å정도의 두께로 형성한다.Next, as shown in FIG. 1C, the first gate oxide film 9 is formed on the upper surface of the structure formed at a suitable height for the high voltage transistor, and is formed to have a thickness of about 450 to 550 Å.
그리고, 각 트랜지스터의 문턱전압을 결정하기 위해서 각 웰(2,3,4,5) 상에이온을 주입한 다음, 로직이 형성될 영역상의 제 1게이트산화막(9)을 사진식각공정을 통해 습식식각으로 제거한 후 상기 구조 상부전면에 얇은 제 2게이트산화막(10)을 125Å의 두께로 형성하여 로직이 형성되는 웰(2,5)에는 125Å두께의 제 2게이트산화막(10)이 형성되고, 고전압 트랜지스터가 형성되는 웰(3,4)에는 575~675Å두께의 제 1게이트산화막(9)과 제 2게이트산화막(10)의 적층구조가 게이트산화막으로 쓰이게 된다.In order to determine the threshold voltage of each transistor, ions are implanted into each of the wells 2, 3, 4, and 5, and the first gate oxide layer 9 on the region where the logic is to be formed is wetted by a photolithography process. After removal by etching, a thin second gate oxide film 10 is formed on the upper surface of the structure to have a thickness of 125 mA, and a second gate oxide film 10 having a thickness of 125 mA is formed in the wells 2 and 5 where logic is formed. In the wells 3 and 4 in which the transistors are formed, a stacked structure of the first gate oxide film 9 and the second gate oxide film 10 having a thickness of 575 to 675 kV is used as the gate oxide film.
그 다음, 도 1d에 도시한 바와 같이 상기 형성한 제 2게이트산화막(10) 상부에 도핑된 폴리실리콘막(11)을 형성하고, 상기 각 웰(2,3,4,5) 상부에 게이트를 형성하도록 상기 폴리실리콘막(11) 및 제 2게이트산화막(10), 제 1게이트산화막(9)을 사진식각공정을 통해 패터닝 한 후 상기 형성한 각 게이트 중 로직영역의 게이트를 하드마스크로 로직영역의 각 웰(2,5)의 특성에 맞는 이온을 주입하여 저농도 소스/드레인영역(12,13)을 형성한다.Next, as shown in FIG. 1D, a doped polysilicon film 11 is formed on the formed second gate oxide film 10, and a gate is formed on each of the wells 2, 3, 4, and 5. After the polysilicon layer 11, the second gate oxide layer 10, and the first gate oxide layer 9 are patterned through a photolithography process, a gate of the logic region among the gates formed as a hard mask is formed. Ions are implanted to match the characteristics of the wells 2 and 5 to form the low concentration source / drain regions 12 and 13.
이때, 각 웰(2,5)에 서로 틀린 이온을 주입하기 위해 감광막패턴을 이용하여 한 웰(2,5)씩 이온을 주입하게되고, 고전압 트랜지스터가 형성되는 웰(3,4)은 항상 마스킹되어 이온이 주입되지 않는다.In this case, in order to inject ions different from each other into the wells 2 and 5, ions are implanted by the wells 2 and 5 using the photoresist pattern, and the wells 3 and 4 where the high voltage transistor is formed are always masked. Ions are not implanted.
그 다음, 도 1e에 도시한 바와 같이 상기 형성한 구조의 상부전면에 절연막을 형성하고 이를 식각하여 각 게이트의 측면에 게이트측벽(14)을 형성한 후 상기 게이트측벽(14)을 포함한 게이트를 하드마스크로 로직영역 및 고전압 트랜지스터가 형성되는 각 웰(2,3,4,5)에 그 특성에 맞는 이온을 주입하여 고농도 소스/드레인영역(15,16)을 형성한다.Then, as shown in FIG. 1E, an insulating film is formed on the upper surface of the formed structure and etched to form gate side walls 14 on the side of each gate, and then hard the gate including the gate side walls 14. High concentration source / drain regions 15 and 16 are formed by implanting ions corresponding to the characteristics into wells 2, 3, 4, and 5 in which logic regions and high voltage transistors are formed using a mask.
상기한 바와 같은 종래 반도체장치 제조방법은 고전압 트랜지스터의 드리프트구조를 형성하기 위해 이온주입 후에 열처리하여 이온을 확산시키는데, 그 후에도 국부산화공정에의한 열공정등에 의해 드리프트구조가 과다확산되어 고전압 트랜지스터의 전압특성이 열화되는 문제점이 있었다.In the conventional method of manufacturing a semiconductor device as described above, ions are diffused by heat treatment after ion implantation to form a drift structure of a high voltage transistor. After that, the drift structure is excessively diffused by a thermal process by a local oxidation process, and thus, There was a problem that the voltage characteristics are deteriorated.
본 발명은 상기한 바와 같은 종래의 문제점을 해결하기 위하여 창안한 것으로, 본 발명의 목적은 공정순서를 변화시킴에 의해 고전압 트랜지스터의 드리프트구조의 과다확산을 방지하여 로직용 트랜지스터 및 고전압트랜지스터 전압특성의 열화를 방지할 수 있는 반도체장치 제조방법을 제공하는데 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the conventional problems as described above, and an object of the present invention is to prevent overdiffusion of the drift structure of a high voltage transistor by changing the order of the process so that the logic transistor and the high voltage transistor voltage characteristics are prevented. Disclosed is a semiconductor device manufacturing method which can prevent deterioration.
도 1은 종래 반도체장치 제조방법을 보인 수순단면도.1 is a cross-sectional view showing a conventional semiconductor device manufacturing method.
도 2는 본 발명 일실시예의 수순단면도.Figure 2 is a cross-sectional view of the procedure of an embodiment of the present invention.
*** 도면의 주요부분에 대한 부호의 설명 ****** Explanation of symbols for main parts of drawing ***
21 : 반도체기판 22 : 고농도엔웰21: semiconductor substrate 22: high concentration enwell
23 : 고농도피웰 24 : 엔형도핑영역23: high concentration pewell 24: end doping region
25 : 피형도핑영역 26 : 국부산화영역25: doped region 26: localized oxidation region
27 : 엔웰 28 : 피웰27: Enwell 28: Pewell
29 : 제 1게이트산화막 30 : 제 2게이트산화막29: first gate oxide film 30: second gate oxide film
31 : 폴리실리콘막 32 : 피형저농도 소스/드레인영역31 polysilicon film 32 low density source / drain region
33 : 엔형저농도 소스/드레인영역 34 : 게이트측벽33: low concentration source / drain region 34: gate side wall
35 : 피형고농도 소스/드레인영역 36 : 엔형고농도 소스/드레인영역35: high concentration source / drain area 36: high concentration source / drain area
상기한 바와 같은 본 발명의 목적을 달성하기 위한 반도체장치 제조방법은 반도체기판 상부에 차례로 고농도엔웰, 고농도피웰을 각각 형성하고 상기 형성한 고농도피웰의 상부에서 고전압트랜지스터의 드리프트구조가 형성될 영역만 정의한 후 그 부분에 엔형이온을 주입하여 엔형도핑영역을 형성하고, 고농도엔웰의 상부에서 고전압트랜지스터의 드리프트구조가 형성될 영역만 정의한 후 그 부분에 피형이온을 주입하여 피형도핑영역을 형성하는 제 1공정과; 상기 각 웰의 이격부분 및 로직영역에 형성될 웰의 이격부분을 각각 정의하면서 그 부분을 국부산화하여 국부산화영역을 형성하고, 로직영역에 차례로 엔웰, 피웰을 형성한 후 상기 국부산화영역을 통해 그 하부 반도체기판상에 각 웰간의 격리를 위한 이온을 주입하는 제 2공정과; 상기 형성한 구조 상부전면에 고전압 트랜지스터에 적당한 높이로 제 1게이트산화막을 형성한 후 형성될 트랜지스터의 문턱전압을 결정하기 위해서 각 웰 상에 이온을 주입한 다음, 로직이 형성될 영역상의 제 1게이트산화막을 사진식각공정을 통해 제거한 후 상기 구조 상부전면에 얇은 제 2게이트산화막을 형성하는 제 3공정과; 상기 형성한 제 2게이트산화막 상부에 도핑된 폴리실리콘막을 형성하고, 상기 각 웰 상부에 게이트를 형성하도록 상기 폴리실리콘막 및 제 2게이트산화막, 제 1게이트산화막을 사진식각공정을 통해 패터닝 한 후 상기 형성한 각 게이트중 로직영역의 게이트를 하드마스크로 로직영역의 각 웰의 특성에 맞는 이온을 주입하여 저농도 소스/드레인영역을 형성하는 제 4공정과; 상기 형성한 구조의 상부전면에 절연막을 형성하고 이를 식각하여 각 게이트의 측면에 게이트측벽을 형성한 후 상기 게이트측벽을 포함한 게이트를 하드마스크로 로직영역 및 고전압영역의 각 웰에 그 특성에 맞는 이온을 주입하여 고농도 소스/드레인영역을 형성하는 제 5공정으로 이루어지는 것을 특징으로 한다.In the semiconductor device manufacturing method for achieving the object of the present invention as described above, the high concentration enwell and the high concentration piwell are sequentially formed on the semiconductor substrate, respectively, and only the region where the drift structure of the high voltage transistor is to be formed on the formed high concentration pewell. After defining, the N-type ions are implanted into the portion to form the N-type doping region, and only the region where the drift structure of the high voltage transistor is to be formed at the top of the high-energy concentration well is defined. 1 step; Define the spaced portions of each well and the spaced portions of the wells to be formed in the logic regions, and localize the portions to form localized regions, and then form enwells and pewells in the logic regions in sequence, and then through the localized regions. A second step of implanting ions for isolation between the wells on the lower semiconductor substrate; After forming the first gate oxide film on the upper surface of the structure at a suitable height for the high voltage transistor, ions are implanted in each well to determine the threshold voltage of the transistor to be formed, and then the first gate on the region where logic is to be formed. A third process of forming a thin second gate oxide film on the entire upper surface of the structure after removing the oxide film through a photolithography process; Forming a doped polysilicon layer on the formed second gate oxide layer and patterning the polysilicon layer, the second gate oxide layer, and the first gate oxide layer through a photolithography process to form a gate on each of the wells; A fourth step of forming a low concentration source / drain region by implanting ions corresponding to the characteristics of each well of the logic region with a hard mask on the gate of the logic region among the formed gates; An insulating film is formed on the upper surface of the formed structure and etched to form a gate side wall on the side of each gate, and then gates including the gate side wall are hard masks in the wells of the logic region and the high voltage region. It is characterized in that the fifth step of forming a high concentration source / drain region by implanting.
상기한 바와 같은 본 발명에 의한 반도체장치 제조방법을 도 2a 내지 도 2e에 도시한 수순단면도를 일 실시예로하여 상세히 설명하면 다음과 같다.A method of manufacturing a semiconductor device according to the present invention as described above will be described in detail with reference to a cross-sectional view of the procedure shown in FIGS. 2A to 2E as an embodiment.
먼저, 도 2a에 도시한 바와 같이 반도체기판(21) 상부에 차례로 고농도엔웰(22), 고농도피웰(23)을 각각 형성하고 상기 형성한 고농도피웰(23)의 상부에서 고전압트랜지스터의 드리프트구조가 형성될 영역만 정의한 후 그 부분에 엔형이온을 주입하여 엔형도핑영역(24)을 형성하고, 고농도엔웰(22)의 상부에서 고전압트랜지스터의 드리프트구조가 형성될 영역만 정의한 후 그 부분에 피형이온을 주입하여 피형도핑영역(25)을 형성한다.First, as shown in FIG. 2A, high concentration enwells 22 and high concentration pewells 23 are sequentially formed on the semiconductor substrate 21, and a drift structure of the high voltage transistors is formed on the high concentration pewells 23. After defining only the region to be formed, the N-type ions are implanted into the portion to form the N-type doping region 24, and only the region where the drift structure of the high voltage transistor is to be formed at the top of the high concentration N well 22 is defined, and then the ion is formed in the portion. Is injected to form the doped region 25.
이때, 고농도엔웰(22)이 형성될 영역의 반도체기판(21)이 드러나도록 감광막패턴을 형성한 후 고농도엔형이온을 도핑하고, 잔류하는 감광막패턴을 제거한 다음, 고농도피웰(23)이 형성될 영역의 반도체기판(21)이 드러나도록 감광막패턴을 형성하고 고농도피형이온을 도핑한 후 상기 웨이퍼를 열처리하여 상기 주입된 이온들을 확산시켜 고농도엔웰(22) 및 고농도피웰(23)을 형성한다.At this time, after forming the photoresist pattern so that the semiconductor substrate 21 in the region where the high concentration enwell 22 is to be formed, doping the high concentration N-type ion, removing the remaining photoresist pattern, and then forming the high concentration pewell 23. A photoresist pattern is formed to expose the semiconductor substrate 21 of the region to be exposed, the doped high-concentration ions are formed, and the wafer is heat-treated to diffuse the implanted ions to form the high-energy enwell 22 and the high-concentration pwell 23. .
그 다음, 도 2b에 도시한 바와 같이 상기 각 웰(22,23)의 이격부분 및 로직영역에 형성될 웰의 이격부분을 각각 정의하면서 그 부분을 국부산화하여 국부산화영역(26)을 형성하고, 로직영역에 차례로 엔웰(27), 피웰(28)을 형성한 후 상기 국부산화영역(26)을 통해 그 하부 반도체기판(21)상에 각 웰(22,23,27,28)간의 격리를 위한 이온을 주입한다.Then, as illustrated in FIG. 2B, the localized regions 26 are formed by locally oxidizing the portions while defining the separation portions of the wells 22 and 23 and the separation portions of the wells to be formed in the logic regions. After forming the enwell 27 and the pewell 28 in the logic region, the isolation between the wells 22, 23, 27 and 28 on the lower semiconductor substrate 21 is formed through the localized region 26. Inject ions for
이때, 국부산화영역(26)을 고온에서 산화하기 때문에 상기 엔형도핑영역(24), 및 피형도핑영역(25)에 주입된 이온이 1차로 확산되고, 상기 제 1공정과 동일하게 감광막패턴을 이용하여 반도체기판(21)상에 이온을 주입한 다음 1000℃에서 30분간 열처리하여 형성하는 엔웰(27) 및 피웰(28)의 형성과정에 의해 상기 엔형도핑영역(24), 및 피형도핑영역(25)에 주입된 이온은 2차로 확산되어 완전한 드리프트구조가 되므로 별도 공정에 의한 드리프트확산이 필요 없으며 상기 국부산화영역(26) 및 로직영역의 웰(27,28)을 형성하면서 과다확산되는 것도 방지할 수 있게된다.At this time, since the local oxidation region 26 is oxidized at a high temperature, ions implanted into the n-type doped region 24 and the to-be-doped region 25 are first diffused, and the photoresist pattern is used in the same manner as in the first process. By implanting ions onto the semiconductor substrate 21 and then performing heat treatment at 1000 ° C. for 30 minutes to form the N-type doped region 24 and the P-type doped region 25. Ions implanted in the second layer are diffused into the secondary to form a complete drift structure, and thus, drift diffusion is not required by a separate process, and overdiffusion may be prevented while forming the localized region 26 and the wells 27 and 28 of the logic region. Will be.
그 다음, 도 2c에 도시한 바와 같이 상기 형성한 구조 상부전면에 고전압 트랜지스터에 적당하도록 450Å~550Å정도의 두께로 제 1게이트산화막(29)을 형성한후 형성될 트랜지스터의 문턱전압을 결정하기 위해서 각 웰(22,23,27,28) 상에 이온을 주입한 다음, 로직이 형성될 영역상의 제 1게이트산화막(29)을 사진식각공정을 통해 제거한 후 상기 구조 상부전면에 얇은 제 2게이트산화막(30)을 125Å의 두께로 형성하여 로직이 형성되는 웰(27,28)에는 125Å두께의 제 2게이트산화막(30)이 형성되고, 고전압 트랜지스터가 형성되는 웰(22,23)에는 575~675Å두께의 제 1게이트산화막(29)과 제 2게이트산화막(30)의 적층구조가 게이트산화막으로 쓰이게 된다.Next, as shown in FIG. 2C, the first gate oxide layer 29 is formed on the upper surface of the structure to be suitable for a high voltage transistor to determine the threshold voltage of the transistor to be formed. After implanting ions into the wells 22, 23, 27 and 28, the first gate oxide layer 29 on the region where logic is to be formed is removed by a photolithography process and then a thin second gate oxide layer on the upper surface of the structure. A second gate oxide film 30 having a thickness of 125 kV is formed in the wells 27 and 28 where logic is formed by forming a thickness of 125 kV, and 575 to 675 kV in the wells 22 and 23 where the high voltage transistor is formed. The stacked structure of the first gate oxide film 29 and the second gate oxide film 30 having a thickness is used as the gate oxide film.
그 다음, 도 2d에 도시한 바와 같이 상기 형성한 제 2게이트산화막(30) 상부에 도핑된 폴리실리콘막(31)을 형성하고, 상기 각 웰(22,23,27,28) 상부에 게이트를 형성하도록 상기 폴리실리콘막(31) 및 제 2게이트산화막(30), 제 1게이트산화막(29)을 사진식각공정을 통해 패터닝 한 후 상기 형성한 각 게이트 중 로직영역의 게이트를 하드마스크로 로직영역의 각 웰(27,28)의 특성에 맞는 이온을 주입하여 저농도 소스/드레인영역(32,33)을 형성한다.Next, as shown in FIG. 2D, a doped polysilicon layer 31 is formed on the formed second gate oxide layer 30, and a gate is formed on each of the wells 22, 23, 27, and 28. After the polysilicon layer 31, the second gate oxide layer 30, and the first gate oxide layer 29 are patterned through a photolithography process, a gate of the logic region among the gates formed as a hard mask is formed. Ions are implanted to match the characteristics of each well 27, 28 to form low concentration source / drain regions 32, 33.
이때, 각 웰(27,28)에 서로 틀린 이온을 주입하기 위해 감광막패턴을 이용하여 한 웰(27,28)씩 이온을 주입하게되고, 고전압 트랜지스터가 형성되는 웰(22,23)은 항상 마스킹되어 이온이 주입되지 않는다.In this case, in order to inject ions different from each other into the wells 27 and 28, the wells 27 and 28 are implanted by using a photoresist pattern, and the wells 22 and 23 in which the high voltage transistor is formed are always masked. Ions are not implanted.
그 다음, 도 2e에 도시한 바와 같이 상기 형성한 구조의 상부전면에 절연막을 형성하고 이를 식각하여 각 게이트의 측면에 게이트측벽(34)을 형성한 후 상기 게이트측벽(34)을 포함한 게이트를 하드마스크로 로직영역 및 고전압영역의 각 웰(22,23,27,28)에 그 특성에 맞는 이온을 주입하여 고농도 소스/드레인영역(35,36)을 형성한다.Next, as shown in FIG. 2E, an insulating film is formed on the upper surface of the formed structure and etched to form gate side walls 34 on the sides of each gate, and then hard the gate including the gate side walls 34. High concentration source / drain regions 35 and 36 are formed by implanting ions corresponding to the characteristics into the wells 22, 23, 27, and 28 of the logic region and the high voltage region using a mask.
상기한 바와 같은 본 발명 반도체장치 제조방법은 고전압용 트랜지스터와 로직용 트랜지스터를 동시에 형성하는 0.35㎛공정에 있어서 고전압 트랜지스터용 웰을 먼저 형성하고, 드레프트구조를 형성하기 위한 이온을 주입한 후 이를 확산하는 열처리공정을 생략하고, 이후 공정인 국부산화영역 형성공정과 로직용 웰 형성공정의 열처리를 이용하여 드레프트구조를 완성함으로써 후속공정에 의한 드레프트구조 과다확산을 방지할 수 있어 로직용 트랜지스터 및 고전압용 트랜지스터의 특성열화를 방지할 수 있는 효과가 있다.In the method of manufacturing a semiconductor device of the present invention as described above, the well for a high voltage transistor is first formed in a 0.35 μm process of simultaneously forming a high voltage transistor and a logic transistor, and then implanted with ions to form a draft structure, and then diffused. By eliminating the heat treatment step, and completing the draft structure by the heat treatment of the local oxidation region forming process and the logic well forming process, which are subsequent processes, the overdraft structure can be prevented by the subsequent process. There is an effect that can prevent the deterioration of characteristics of the high voltage transistor.
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