KR19990003543A - Manufacturing method of semiconductor device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device in which an LDD structure is formed without using sidewall spacers. In order to achieve the above object, in the manufacture of a semiconductor device of a predetermined conductivity type having an LDD structure, the step of sequentially depositing a gate oxide film and a polysilicon film on a semiconductor substrate having a first conductivity type well, a device isolation film and an active region, Etching the polysilicon layer by a photolithography process to form a gate electrode on a predetermined region of the active region, and ion implanting a second conductivity type low concentration impurity onto the entire structure to form a low concentration junction region, the overall structure Forming a contact hole by depositing an interlayer insulating film on the low concentration junction region and removing the interlayer insulating layer on the junction region; Forming a junction region of the LDD structure by forming a region. And that is characterized.

Description

Manufacturing Method of Semiconductor Device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device in which an LDD structure is formed without using sidewall spacers.

Recently, in order to achieve rapid operation and high integration of semiconductor devices throughout the semiconductor industry, design rules for semiconductor devices have been reduced. However, in the case of a short channel device having a reduced channel length of the device, unless the voltage applied to the device is lowered compared to the long channel, the electric field strength between the source and the drain increases to accelerate the carrier of the channel. Is injected into the gate oxide film or the like to degrade the characteristics of the device. This is called the hot carrier effect.

In order to improve this, a lightly doped drain (LDD) structure has been proposed, which refers to forming an LDD region, which is a low concentration junction layer, in a region adjacent to a channel of a source / drain junction. FIG. 1 illustrates a conventional LDD structure semiconductor device. In brief, a manufacturing method will be described. First, the gate oxide film 12 and the gate electrode 12 may be formed on a predetermined active region between the device isolation layers 11 of the semiconductor substrate 10. 13), then low concentration N-type ion implantation is performed to form the low concentration junction region 14a. Next, a sidewall spacer 15 is formed on the side of the gate electrode 13 to form a high concentration N-type ion implantation to form a high concentration junction region 14b on the low concentration junction region 14a to complete the LDD structure. The low concentration LDD region formed adjacent to the channel may reduce the electric field strength to prevent the effect of hot carriers.

However, there is a problem in that the process is complicated because the process of forming the sidewall spacers has to be added to form the transistor of the LDD structure as described above.

Accordingly, an object of the present invention is to provide a method of manufacturing a semiconductor device that can simplify the manufacturing process by manufacturing a semiconductor device having an LDD structure without forming sidewall spacers.

1 is a cross-sectional view showing a transistor of an LDD structure having a side-wall according to the prior art.

2A to 2B are cross-sectional views illustrating an N-type MOS transistor manufacturing process of the LDD structure according to the first embodiment of the present invention.

3A to 3D are cross-sectional views illustrating an N-type and a P-type MOS transistor manufacturing process of the LDD structure according to the second embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

10,20,30: semiconductor substrate 11,21,31: device isolation film

12,22,32 gate oxide film 13,23,33 gate electrode

14a, 24a, 35a, 36a: low concentration junction region 14a, 24a, 35b, 36b: high concentration junction region

25,37: interlayer insulation film

In order to achieve the above object, in the manufacture of a semiconductor device of a predetermined conductivity type having an LDD structure, the step of sequentially depositing a gate oxide film and a polysilicon film on a semiconductor substrate having a first conductivity type well, a device isolation film and an active region, Etching the polysilicon layer and the gate oxide layer by a photolithography process to form a gate electrode on a predetermined region of the active region, and ion implanting a second conductivity type low concentration impurity onto the entire structure to form a low concentration junction region Depositing an interlayer insulating film over the entire structure and forming a contact mask on the low concentration junction region to form a contact hole by removing the interlayer insulating layer on the junction region; Forming high-concentration junction region by implantation completes junction region of LDD structure It is characterized by including the steps:

In addition, in the manufacture of a semiconductor device comprising a first type MOS transistor having an LDD structure and a second type MOS transistor having an LDD structure according to the present invention, a first type, a second type well and a device isolation film and an active region are formed on a semiconductor substrate. Forming a gate electrode and a polysilicon layer over the entire structure, and etching the polysilicon layer by a photolithography process to form a gate electrode on a predetermined region of the active region; Forming a first mask pattern on a region where the transistor is to be formed, performing a low concentration type 2 ion implantation process on the entire structure to form a low concentration junction region of the second type MOS transistor, and forming the first mask pattern Removing, forming a mask pattern on a region where the second type MOS transistor is to be formed; Performing a low concentration type 1 ion implantation process to form a low concentration junction region of the first type MOS transistor, removing the second mask pattern, depositing an interlayer insulating film over the entire structure, and then Forming a contact hole by forming a contact mask on the low concentration junction region of the type 2 MOS transistor, forming the first mask pattern, and performing a high concentration type 2 ion implantation process on the entire structure to form a high concentration junction region. Forming a LDD structure of the second MOS transistor, removing the first mask pattern, forming the second mask pattern, and performing a high concentration type 1 ion implantation process on the entire structure to form a high concentration junction region. Forming an LDD region of the first type MOS transistor and removing the second mask pattern; It characterized.

EXAMPLE

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention.

First embodiment

A process cross-sectional view showing a method for manufacturing an NMOS Tr. Having an LDD structure according to the present invention, in which a gate oxide film 22 and a polysilicon film are deposited on a semiconductor substrate 20 on which a device isolation film 21 is formed, as shown in FIG. 2A. Next, a gate electrode 23 made of a polysilicon film is formed through a photolithography process. Subsequently, a low concentration n-type ion implantation process is performed on the entire structure to form a low concentration n-type junction region 24a. Then, the interlayer insulating film 25 is deposited over the entire structure, and then the interlayer insulating film of the junction region is etched using a contact mask (not shown) of the junction region used in a subsequent process to thereby etch the low concentration junction region 24a. A contact hole is formed on Next, as shown in FIG. 2B, a high concentration n-type impurity is ion-implanted to form a high concentration n-type junction region 24b to form a junction region having an LDD structure. The subsequent steps are the same as those of the conventional transistor formation process and will be omitted.

Second embodiment

3A to 3D are cross-sectional views illustrating a method of manufacturing an NMOS and a PMOS Tr. Having an LDD structure according to an embodiment of the present invention, and only MOS transistors having N-type and P-type LDD structures will be described. First, as shown in FIG. 3A, the gate oxide layer 32 and the polysilicon layer are deposited on the semiconductor substrate 30 on which the device isolation layer 31 is formed, and then the gate electrode 33 made of the polysilicon layer through a photolithography process. To form. Subsequently, the NMOS Tr. A mask pattern 34a is formed on the area. After the low concentration p-type ion implantation process is performed on the entire structure to form the low concentration p-type junction region 35a, the mask pattern 34a is removed. Subsequently, the same reticle is used, but the polarity of the resist is changed, so that the PMOS Tr. After forming the mask 34b on the region, a low concentration n-type ion implantation is performed to form the low concentration n-type junction region 36a and the mask pattern 34b is removed. Then, the interlayer insulating film 37 is deposited on the entire structure, and then the interlayer insulating film of the junction region is etched using the contact mask (not shown) of the junction region used in the subsequent process, as shown in FIG. 3C. And a contact hole is formed on the junction region of the PMOS Tr. Next, the NMOS Tr. A mask pattern 34a is formed on the region to perform a high concentration p-type ion implantation process to form a high concentration p-type junction region 35b, thereby producing an LDD structure of PMOS Tr. Subsequently, the mask pattern 34a is removed and the PMOS Tr. 3D shows the formation of a high concentration n-type junction region 36b by a high concentration of n-type ion implantation by forming a mask 34b on the region. The subsequent steps are the same as those of the conventional transistor formation process and will be omitted.

As described above, in order to prevent the hot carrier effect, a low concentration junction region is formed in the channel region, and the LDD structure semiconductor device is manufactured using a conventional contact mask without using sidewall spacers to simplify the manufacturing process. Can be.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.

Claims (2)

In the manufacture of a semiconductor device of a predetermined conductivity type having an LDD structure, depositing a gate oxide film and a polysilicon film on a semiconductor substrate having a first conductivity type well, a device isolation layer and an active region in sequence, the polysilicon by a photolithography process Etching a film and a gate oxide film to form a gate electrode on a predetermined region of the active region, ion implanting a second conductivity type low concentration impurity onto the entire structure to form a low concentration junction region, and an interlayer insulating film on the entire structure After forming a contact mask on the low concentration junction region to form a contact hole by etching the interlayer insulating layer on the junction region and ion implanted a second conductivity type high concentration impurity on the entire structure to form a high concentration junction region Thereby comprising the step of completing the junction region of the LDD structure The method of the conductor elements. In the manufacture of a semiconductor device comprising a first type MOS transistor having an LDD structure and a second type MOS transistor having an LDD structure, forming a first type, a second type well, an element isolation film, and an active region on a semiconductor substrate; Depositing a gate oxide film and a polysilicon film on top of the structure, etching the polysilicon film by a photolithography process to form a gate electrode on a predetermined region of the active region, and on the region where the first MOS transistor is formed Forming a first mask pattern on the second structure; forming a low concentration junction region of the second MOS transistor by performing a low concentration type 2 ion implantation process on the entire structure; removing the first mask pattern; Forming a second mask pattern on the region where the two-type MOS transistor is formed; Performing an ion implantation process to form a low concentration junction region of the first MOS transistor, removing the second mask pattern, depositing an interlayer insulating film over the entire structure, and then forming the first and second MOS transistors. Forming a contact hole by forming a contact mask on the low-concentration junction region of the substrate, forming the first mask pattern, and performing a high concentration type 2 ion implantation process on the entire structure to form a high-concentration junction region Forming a high-density junction region by forming an LDD structure of a type MOS transistor, removing the first mask pattern, forming the second mask pattern, and performing a high concentration type 1 ion implantation process on the entire structure. Fabricating a semiconductor device comprising forming an LDD region of a type 1 MOS transistor and removing the second mask pattern Way.