JPH07321015A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To reduce the number of photomask processes, by forming impurity diffusion region after an alignment mark is formed by doubly exposing a region corresponding with the alignment mark of a scribe line with incomplete exposure by using a single photomask. CONSTITUTION:A region corresponding with the alignment mark of a scribe line 11B is completely exposed by doubly exposing the region with incomplete exosure applying step exposure by using a photomask 11A. A resist film 13C of the completely exposed region is eliminated, an insulating film 12 and a semiconductor substrate 11 are eliminated by etching, and an alignmant mark 14 is formed. The whole part of a resist film 13 is etched, and an aperture is selectively formed in only the region corresponding with an impurity diffusion region 15. An impurity diffusion region 15 is selectively formed by implanting impurities of a conductivity type in the surface layer of the semiconductor substrate 11 through the aperture. Thereby the number of photomask processes is reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to an improvement in a so-called twin well forming method used for a semiconductor device which has been highly miniaturized.

[0002]

2. Description of the Related Art When forming a semiconductor device such as a MOSFET, an n-type impurity diffusion layer (n-well) and a p-type impurity diffusion layer are used.
Often, a twin well is formed in such a manner that it is formed adjacent to a p-type impurity diffusion layer (p-well). A twin well forming method according to a conventional example will be described below with reference to FIG.
This will be described with reference to FIGS. First, as shown in FIG. 10, after a SiO2 film (2) is formed on a silicon substrate (1), a positive photoresist is applied on the entire surface to form a resist film (3) having a film thickness of about 1 μm. . Then
An area corresponding to the alignment mark of the scribe line area (1B) is selectively stepwise exposed using the first photomask (1A) to form an exposure area (3A).

Next, as shown in FIG. 11, the resist film (3) is developed to remove the exposed region (3A), and the SiO2 film (2) and the silicon substrate (1) are etched using this as a mask. By removing and removing the resist film (3), an alignment mark (4) is formed on the silicon substrate (1) on the scribe line region (1B). Next, as shown in FIG. 13, after forming a resist film (5) on the SiO2 film (2), an alignment mark (4) is formed.
After that, the second photomask (1C) on which the pattern corresponding to the p-well (6) is formed is aligned with the silicon substrate (1), and the second photomask (1C) is formed. The resist film (5) is exposed through. As a result, the exposure area (5A) corresponding to the p-well (6) as shown in FIG. 13 is formed on the resist film (5).

Next, as shown in FIG. 14, a resist film (5)
Is developed to remove the exposed area (5A) to expose the SiO2 film (2), the resist film (5) is used as a mask, and boron ions (B +) are transferred through the SiO2 film (2) to the silicon substrate ( After injecting into the surface layer of 1), the resist film (5) is peeled off to form a p-well (6) as shown in FIG.

Thereafter, as shown in FIG. 16, a resist film (7) is formed again on the entire surface, and then the alignment mark (4) is used to position the silicon substrate (1) and the third photomask (1D). Then, the resist film (7) in the region corresponding to the n-well (8) is selectively exposed using the third photomask (1D) to expose the exposed region (7).
A) is formed.

Next, as shown in FIG. 17, the resist film (7) is developed to remove the exposed area (7A) to expose the SiO2 film (2), and then the resist film (7) is used as a mask to remove the SiO2 film. Phosphorus ions (P +) are implanted into the surface layer of the silicon substrate (1) through the film (2). After that, the resist film (7) is peeled off and left in a N2 atmosphere at a temperature of 1150 DEG C. for 4 hours to obtain a p-w as shown in FIG.
A twin well composed of the well (6) and the n-well (8) is formed.

[0007]

However, according to the above conventional manufacturing method, [1] the step of forming the alignment mark (4), [2] the step of forming the p-well (6), and [3] the n-well. For each of the formation steps of (8), the first to third photomasks (11A, 11C,
11D) requires a total of three photomask processes, which causes a problem that the number of mask processes increases and the cost increases.

[0008]

The present invention has been made in view of the above-mentioned conventional drawbacks, and as shown in FIGS. 1 to 9, a first chip region formed by sandwiching a scribe line (11B). (21) and a step of sequentially forming an insulating film (12) and a resist film (13) on a semiconductor substrate (11) having a second chip region (22), and a first photomask (11A). By using the resist film (13) in the region corresponding to the first impurity diffusion region (15) of the first chip region (21) and the region corresponding to the alignment mark (14) of the scribe line (11B). ) Is incompletely exposed by step exposure, and a region corresponding to the alignment mark (14) of the scribe line (11B) is formed by using the first photomask (11A) and the second photomask (11A). The resist film (13) incompletely exposed by step exposure of the chip area (22),
Double exposing the region corresponding to the alignment mark (14) of the scribe line (11B) to complete exposure, and developing the resist film (13) to develop the resist film (13C) in the completely exposed region. ) Is removed,
Using the resist film (13) as a mask, the insulating film (1
2) and the step of etching / removing the semiconductor substrate (11) to form an alignment mark (14) on the semiconductor substrate (11), and the resist film (13) is entirely etched to obtain the first impurity. Diffusion area (1
5) The step of removing the incompletely exposed region (13A) corresponding to 5) to expose the insulating film (12), and one conductivity on the surface layer of the semiconductor substrate (11) through the exposed insulating film (12). A first impurity diffusion region (1
5), and the resist film (16) is formed again after the resist film (13) is peeled off, and the second photomask and the semiconductor substrate (11) are formed by using the alignment mark (14). Are aligned, and the region corresponding to the second impurity diffusion region (17) of the resist film (16) is completely exposed and then developed to remove the exposed region, which is used as a mask to reverse conductivity type. By including the step of injecting impurities into the surface layer of the semiconductor substrate (11) to form the second impurity diffusion region (17), it becomes possible to form a twin well while reducing the mask step. A method for manufacturing a device is provided.

[0009]

[Operation] According to the method for manufacturing a semiconductor device of the present invention, as shown in FIGS.
1A), the resist film (13) in the region corresponding to the first impurity diffusion region (15) of the first chip region (21) and the region corresponding to the alignment mark (14) of the scribe line (11B). Is subjected to incomplete exposure by step exposure, and then a region corresponding to the alignment mark (14) of the scribe line (11B) and the second chip region (2) are formed using the first photomask (11A).
The resist film (13) with 2) is incompletely exposed by step exposure, the region corresponding to the alignment mark (14) of the scribe line (11B) is double exposed to be completely exposed, and the resist in the completely exposed region is exposed. The film (13C) is removed, and the resist film (13) is used as a mask to form the insulating film (1
2) and the semiconductor substrate (11) are etched and removed to form an alignment mark (14) on the semiconductor substrate (11).

In the above steps, the region corresponding to the first impurity diffusion region (15) is an incomplete exposure region,
Although not completely removed in the step of removing the resist film (13), the resist film (13) in the region corresponding to the first impurity diffusion region (15) is exposed because it is exposed to some extent. Has a recess. Next, by completely etching the resist film (13), the resist film (13) in the region where the recess is formed is completely removed, but the resist film (13) in the other regions remains to some extent. Therefore, the first impurity diffusion region (15)
It is possible to selectively form an opening only in the region corresponding to to expose the underlying insulating film (12).

Therefore, it is possible to form the first impurity diffusion region (15) by implanting the one conductivity type impurity into the surface layer of the semiconductor substrate (11) through the exposed insulating film (12). Although the alignment mark (14) and the first impurity diffusion region (15) are formed by the steps up to the above, the photomask used so far is only one of the first photomask (11A). 10 to 1
As shown in FIG. 5, the first and second photomasks (1A, 1A
It is possible to reduce the number of photomasks by one compared to the conventional manufacturing method in which the alignment mark (4) and the p-well (6) are formed by using the two photomasks in C). become.

Therefore, it is possible to reduce the number of photomask steps by that amount, and the cost can be reduced accordingly.

[0013]

EXAMPLES A method of manufacturing a semiconductor device according to an example of the present invention will be described below with reference to FIGS.
3 is a sectional view taken along the line AA of FIG. First, Fig. 1
As shown in FIG. 5, a film thickness of 5 is formed on the semiconductor substrate (11) in which the first chip region (21), the second chip region (22) and the scribe line (11B) are formed therebetween.
An oxide film (12) of 00 and a resist film (13) having a film thickness of about 1 μm are sequentially formed, and then a p-well (15) is formed.
The resist film (13) of the first chip region (21) and the scribe line (11B) is stepwise exposed by a stepper using the photomask (11A) on which the pattern of the alignment mark (14) is formed. At this time, the resist film (13) is not exposed with an amount of light such that the resist film (13) is completely exposed, but is exposed with an amount of exposure such that the resist film (13) in the exposed region remains about 100 nm. Then, as shown in FIG. 2, 100 nm from the bottom.
Exposed areas (13A, 13B) that are not exposed are formed to some extent.

Next, as shown in FIG. 3, the resist film (13) in the second chip region (22) adjacent to the first chip region (21) is subjected to stepper exposure. At this time, the first
The scribe line (11B) between the chip region (21) and the second chip region (22) is also exposed at the same time.
The exposure amount at this time is also the same as in the step of FIG. 1, so that the resist film (13) in the exposure region remains at about 100 nm.

Then, as shown in FIGS. 3 and 4, the scribe line (11B) portion is to be double exposed, which corresponds to the pattern of the alignment mark formed on the scribe line (11B). The area is completely exposed to the bottom, forming an exposed area (13C). Next, each chip region (not shown) on the semiconductor substrate (11) is similarly stepwise exposed.

After that, the resist film (13) in the exposed regions (13A, 13C) is developed and removed. In this developing process, the exposure area (13) corresponding to the p-well (15) is used.
Since A) is also removed at the same time, a recess (13D) as shown in FIG. 5 is formed in that region. Next, using the resist film (13) as shown in FIG. 5 as a mask, the oxide film (1
2) and the semiconductor substrate (11) are etched and removed to form the alignment mark (14), and then RIE (Reactive Ion) using O2 gas or the like is performed as shown in FIG.
Etching) etc. to remove 100n of resist film (13) on the entire surface.
Etch about m. In this step, the resist film of about 100 nm remaining in the recess (13A) is completely removed and the oxide film (12) is exposed.

Then, boron ions (11B +) are added to 80 ke
Implantation is performed under the conditions of V and 7.6 × 10 12 cm −2 to form a p-well (15) as shown in FIG. 7. In the steps up to that shown in FIG. 7, the alignment mark (14),
Although the p-well (15) was formed, the photomask used in this step was the first photomask (11
As shown in FIGS. 10 to 15, the alignment mark (4) is obtained by using a total of two photomasks of the first and second photomasks (1A, 1C). It becomes possible to reduce one photomask process compared with the conventional manufacturing method in which the p-well (6) was formed.

After that, the resist film (13) is peeled off, and a resist film (16) having a film thickness of 1 μm is formed on the entire surface again.
A second photomask (not shown) on which a pattern corresponding to the well (17) is formed and the semiconductor substrate (11) are aligned using the alignment mark (14), and the first chip region (21) is formed. Step), and all the chip areas formed on the semiconductor substrate (11) such as the second chip area (22) are sequentially step-exposed. In this step, exposure is performed with a light amount such that the exposure area is completely exposed.

Then, the resist film (16) is developed to remove the exposed area, and then phosphorus ions (31 P +) are added to 1 as shown in FIG. 8 using the resist film (16) as a mask.
Implantation was performed under the conditions of 60 keV and 1.8 × 10 13 cm −2, the resist film (16) was peeled off, and then 1 in an N 2 atmosphere.
Diffusion is performed for 4 hours at a temperature of 150 ° C., and p as shown in FIG.
Twin wells consisting of -well (15) and n-well (17) are formed.

As described above, according to this embodiment, the alignment mark (14) and the p-well (15) can be formed with only one first photomask (11A). Since only one photomask is required as compared with the conventional method in which photomasks are prepared one by one, it is possible to reduce the number of photomask steps and consequently the cost.

In this embodiment, first, p-we
Although n-well (17) is formed after forming 11 (15), the present invention is not limited to this, and conversely n-we
The p-well (15) may be formed after forming the ll (17). In addition, p-we as shown in FIGS.
When exposing the area corresponding to 11 (15), 100 n
Although the exposure is performed with a light amount such that the resist film (13) remains for about m, the present invention is not limited to this, and although the resist film is not completely removed by one exposure, alignment is performed when double exposure is performed. If the light amount is such that the resist film in the region corresponding to the mark (14) is completely removed, the same effect can be obtained regardless of the light amount.

[0022]

As described above, according to the method of manufacturing a semiconductor device of the present invention, the first photomask (11
A) is used to remove the resist film (13) in the region corresponding to the first impurity diffusion region (15) of the first chip region (21) and the region corresponding to the alignment mark (14) of the scribe line (11B). After the incomplete exposure by the step exposure, using the first photomask (11A), the region corresponding to the alignment mark (14) of the scribe line (11B) and the second chip region (2
The resist film (13) with 2) is incompletely exposed by step exposure, the region corresponding to the alignment mark (14) of the scribe line (11B) is double exposed to be completely exposed, and the resist in the completely exposed region is exposed. The film (13C) is removed, and the resist film (13) is used as a mask to form the insulating film (1
2) and the semiconductor substrate (11) are etched / removed to form an alignment mark (14) on the semiconductor substrate (11), and then the resist film (13) is entirely etched to form a first impurity diffusion region (15). ), An opening is selectively formed only in a region corresponding to the region (4) to expose the underlying insulating film (12), and a single conductivity type impurity is implanted into the surface layer of the semiconductor substrate (11) through the opening, One impurity diffusion region (15) can be selectively formed.

The alignment mark (14) and the first impurity diffusion region (15) are formed by the steps up to the above. The photomask used up to this point is one of the first photomask (11A). Therefore, it is possible to reduce the number of photomasks by one as compared with the conventional method in which two photomasks (1A, 1C) are used in the steps up to this point, and the cost is reduced accordingly. It becomes possible to do.

[Brief description of drawings]

FIG. 1 is a first cross-sectional view illustrating a method of manufacturing a semiconductor device according to an embodiment of the invention.

FIG. 2 is a second cross-sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the invention.

FIG. 3 is a third cross-sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the invention.

FIG. 4 is a top view illustrating the method for manufacturing the semiconductor device according to the embodiment of the invention.

FIG. 5 is a fourth sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the invention.

FIG. 6 is a fifth cross-sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the invention.

FIG. 7 is a sixth sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the invention.

FIG. 8 is a seventh cross-sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the invention.

FIG. 9 is an eighth sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the invention.

FIG. 10 is a first cross-sectional view explaining the method for manufacturing the semiconductor device according to the conventional example.

FIG. 11 is a second cross-sectional view explaining the method for manufacturing the semiconductor device according to the conventional example.

FIG. 12 is a third cross-sectional view illustrating the method for manufacturing the semiconductor device according to the conventional example.

FIG. 13 is a fourth cross-sectional view illustrating the method for manufacturing the semiconductor device according to the conventional example.

FIG. 14 is a fifth cross-sectional view illustrating the method for manufacturing the semiconductor device according to the conventional example.

FIG. 15 is a sixth cross-sectional view illustrating the method for manufacturing the semiconductor device according to the conventional example.

FIG. 16 is a seventh cross-sectional view illustrating the method for manufacturing the semiconductor device according to the conventional example.

FIG. 17 is an eighth cross-sectional view explaining the method for manufacturing the semiconductor device according to the conventional example.

FIG. 18 is a ninth cross-sectional view illustrating the method for manufacturing the semiconductor device according to the conventional example.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location H01L 21/78 L

Claims (1)

[Claims] 1. An insulating film (12) on a semiconductor substrate (11) having a first chip region (21) and a second chip region (22) formed with a scribe line (11B) interposed therebetween. A step of sequentially forming a resist film (13); a region corresponding to the first impurity diffusion region (15) of the first chip region (21) using the first photomask (11A); Incompletely exposing the resist film (13) in a region corresponding to the alignment mark (14) of the scribe line (11B) by step exposure, and using the first photomask (11A), the scribe line ( 11B) corresponding to the alignment mark (14) and the second chip area (2).
2) the resist film (13) and the resist film (13) are incompletely exposed by step exposure, and the region corresponding to the alignment mark (14) of the scribe line (11B) is double-exposed to be completely exposed; (13) is developed to remove the resist film (13C) in the completely exposed region, and the insulating film (12) and the semiconductor substrate (11) are etched using the resist film (13) as a mask. Removing and forming an alignment mark (14) on the semiconductor substrate (11); and etching the resist film (13) over the entire surface to form an incompletely exposed region corresponding to the first impurity diffusion region (15). (13A) is removed to expose the insulating film (12), and one conductivity type is provided on the surface layer of the semiconductor substrate (11) through the exposed insulating film (12). Net objects by injecting, forming a first impurity diffusion region (15), a resist film (16) again after peeling off the resist film (13), the alignment mark (1
4) using the second photomask and the semiconductor substrate (1
1) is aligned with the second film of the resist film (16).
The region corresponding to the impurity diffusion region (17) is completely exposed, and then developed to remove the exposed region. Using this as a mask, impurities of opposite conductivity type are injected into the surface layer of the semiconductor substrate (11) and 2. A method of manufacturing a semiconductor device, which comprises the step of forming a second impurity diffusion region (17).