JP2003209121A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device having a reliable MOS transistor of an LDD structure without causing shadowing. <P>SOLUTION: The method of manufacturing the semiconductor device comprises a process of applying a resist on a substrate 1 formed with a gate electrode 4a, a process of removing part of the resist so as to expose the gate electrode 4a, and a process of chamfering the end on the gate electrode 4a side of a resist 8a left over from the process for removing part of the resist by a thinner separation method. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device including a MOS transistor having an LDD structure.

[0002]

2. Description of the Related Art A conventional semiconductor device will be briefly described with reference to FIGS. FIG. 8 is a schematic cross-sectional view showing a conventional semiconductor device, and FIG. 9 is a schematic cross-sectional view showing the semiconductor device in each step of the manufacturing method.

In FIGS. 8 and 9, 1 is P as a substrate
-Type semiconductor substrate, 3 is a gate insulating film before gate processing, 3a
Is a gate insulating film after gate processing, 4 is a gate electrode layer before gate processing, 4a is a gate electrode layer after gate processing, 5 is a resist before processing for forming a gate electrode layer, 5a
Is a processed resist for forming a gate electrode layer, 1
0 is an N layer having an LDD structure, 10a is an N ⁺ layer of an N-channel transistor, and 10b is an N ⁺ layer of an N-channel transistor.
^- layer, 10c are N ^- gate insulating the layer 10b membrane 3a
The N ^- layer is shown as the adjacent portion to and.

As shown in FIG. 8, in the LDD structure MOS transistor, the diffusion layers serving as the source / drain regions have N ⁺ layers 10a with a high impurity concentration and N ⁻ layers 10b, 10c with a low impurity concentration. It has a double structure with. This can alleviate the electric field concentration at the boundary in the drain region of the MOS transistor.

The semiconductor device shown in FIG. 8 configured as described above is manufactured through the steps shown in FIGS. 9 (a) to 9 (c). The steps will be sequentially described below. First,
As shown in FIG. 9A, the gate insulating film 3 is formed on the P-type semiconductor substrate 1 as the one conductivity type semiconductor substrate by a thermal oxidation method. Then, the gate electrode layer 4 of polysilicon or the like is formed on the gate insulating film 3. Further, a resist 5 is applied on the gate electrode layer 4.

Next, as shown in FIG. 9B, a desired patterned resist 5a is formed by photolithography. Then, using the patterned resist 5a as a mask, the exposed region of the gate electrode layer 4 is removed by etching. As a result, the gate electrode layer 4a as the gate electrode of the MOS transistor is formed.

After that, as shown in FIG. 9C, the resist 5a on the gate electrode layer 4a is removed. Then, as shown by the arrow in the figure, the N layer 10 is formed by implanting ions of phosphorus or the like obliquely downward with the gate electrode layer 4a used as a mask (oblique rotation implantation method).
To form the N ⁻ layer. Here, the oblique rotation implantation method means that ions are implanted at a predetermined implantation angle β in order to form a diffusion layer just below the gate electrode 4a (the region 10c in FIG. 8), and the ions in the diagonal direction are also implanted. Ion implantation is performed while rotating the P-type semiconductor substrate 1 in order to suppress the asymmetry of the diffusion layer in the source / drain due to the implantation.

After that, using the gate electrode layer 4a as a mask, the P-type semiconductor substrate 1 is directed toward the source / drain regions.
By implanting ions of arsenic or the like from the direction perpendicular to, the N ⁺ layer in the N layer 10 is formed. As described above, the LDD structure MOS transistor having the N layer 10 including the N ⁺ layer 10a and the N ⁻ layers 10b and 10c is formed. Note that the gate insulating film 3 is not removed in the step shown in FIG. 9B, and therefore, although FIG. 9 does not strictly show the method for manufacturing the semiconductor device shown in FIG. Does not make a big difference.

[0009]

The above-described conventional semiconductor device has a problem that it is not possible to sufficiently perform ion implantation from a diagonal direction downward to the gate electrode layer due to shadowing.

A specific example will be described with reference to FIG. Figure 1
0 is a schematic cross-sectional view showing the semiconductor device in the oblique rotation implantation step of implanting phosphorus toward the lower side of the gate electrode layer 4a in the N-channel transistor region R. The semiconductor device shown in the figure is a highly integrated CMOS transistor, and in this step, a resist having a film thickness of about 1 μm is formed on the P-channel transistor region S other than the N-channel transistor region R in which phosphorus is implanted. 48 are formed. An inter-element isolation insulating film 2 is formed at the boundary between the N-channel transistor region R and the P-channel transistor region S.

However, the N-channel transistor region R
Toward the bottom of the gate electrode layer 4a at
If phosphorus is to be implanted in, the phosphorus implantation route will be blocked by the resist 48 adjacent to the gate electrode layer 4a, as indicated by the broken line arrow in FIG. This phenomenon is called shadowing. In the situation where this shadowing occurs, the implantation of phosphorus can only be achieved with an implantation angle α that is smaller than the desired implantation angle β, so that the desired LD
The D structure cannot be formed.

Such a problem becomes more serious in a miniaturized semiconductor device. That is,
In the miniaturized semiconductor device, the size of each element is further reduced, so that the width L of the diffusion layer 10 of the MOS transistor in FIG. 10 is also reduced. Therefore, the injection angle α that can be injected becomes smaller.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a method for manufacturing a semiconductor device having a highly reliable LDD structure MOS transistor which does not cause shadowing.

[0014]

According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device, wherein a step of applying a resist on a substrate on which a gate electrode is formed and the gate electrode is exposed. The method further includes the step of removing a part of the resist, and the step of chamfering the gate electrode side end of the resist remaining in the step of removing a part of the resist by a thinner peeling method.

According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising a step of applying a resist on a substrate on which a gate electrode is formed, and an exposure apparatus which exposes an exposed area of the resist. Providing a filter for reducing the exposure amount at the end of the exposure region at a position conjugate with the field stop; removing a part of the resist so that the gate electrode is exposed; and remaining the gate electrode of the resist And a step of chamfering the side end portion.

According to a third aspect of the present invention, there is provided a method of manufacturing a semiconductor device, wherein a step of applying a first resist on a substrate having a gate electrode formed thereon and the step of exposing the gate electrode are performed. From the opening of the first resist remaining in the step of removing a part of the first resist, the step of applying a second resist on the first resist, and the step of removing a part of the first resist After the exposure amount to the second resist is adjusted so as to make a large opening, a step of removing a part of the second resist is provided.

According to a fourth aspect of the present invention, there is provided a method of manufacturing a semiconductor device, wherein a step of applying a first resist on a substrate having a gate electrode formed thereon and the step of exposing the gate electrode are performed. A step of removing a part of the first resist, a step of applying a second resist on the first resist, and an opening of the first resist remaining in the step of removing a part of the first resist. Removing a part of the second resist so as to open equally,
And a step of chamfering the gate electrode side end of the second resist remaining in the step of removing a part of the resist.

According to a fifth aspect of the present invention, in the method of manufacturing a semiconductor device according to the fourth aspect, the chamfering step is an ashing step.

According to a sixth aspect of the present invention, in the method of manufacturing a semiconductor device according to the fourth aspect, the chamfering step is a heat treatment step.

According to a seventh aspect of the present invention, in the method of manufacturing a semiconductor device according to the fourth aspect, the chamfering step is a step using a thinner peeling method.

Further, in a method of manufacturing a semiconductor device according to an eighth aspect of the present invention, the step of applying a first resist on a substrate on which a gate electrode is formed, and the step of exposing the gate electrode are performed. A step of removing a part of the first resist, a step of applying a second resist on the first resist, and an opening of the first resist remaining in the step of removing a part of the first resist. And a step of removing a part of the second resist so as to equally open and chamfering the remaining end of the second resist on the gate electrode side.

The method of manufacturing a semiconductor device according to a ninth aspect of the present invention is the method according to the eighth aspect, further comprising a step of exposing the exposure region of the second resist while defocusing it. is there.

According to a tenth aspect of the present invention, there is provided a method of manufacturing a semiconductor device according to the eighth aspect, wherein the exposure area of the second resist is exposed at a position conjugate with a field stop of the exposure apparatus. The method further comprises the step of providing a filter for reducing the exposure amount at the end of the exposure area.

According to an eleventh aspect of the present invention, there is provided a method of manufacturing a semiconductor device according to the third aspect, wherein the etching rate of the first resist is set to the second resist. The etching rate is lower than the etching rate.

According to a twelfth aspect of the present invention, in the method of manufacturing a semiconductor device according to the first aspect, the ions are obliquely directed downward from the gate electrode. The method further comprises the step of rotating injection.

[0026]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will now be described in detail with reference to the drawings. In the drawings, the same or corresponding parts are designated by the same reference numerals, and the duplicate description thereof will be appropriately simplified or omitted.

Embodiment 1. A first embodiment of the present invention will be described in detail with reference to FIGS. 1 (a)-
2 (a) and 2 (b) are schematic cross-sectional views showing the semiconductor device in each step of the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

First, as shown in FIG. 1A, an element isolation insulating film 2 is formed on a P-type semiconductor substrate 1 as a substrate by, for example, the LOCOS isolation method. Then, the gate insulating film 3 is formed on the P-type semiconductor substrate 1. Then, the gate electrode layer 4 of polysilicon or the like is formed on the gate insulating film 3. Further, a resist 5 is applied on the gate electrode layer 4. Here, the film thicknesses of the gate insulating film 3 and the gate electrode layer 4 are, for example, about 6 nm and 100 nm, respectively. The element isolation insulating film 2 is formed at the boundary between the N-channel transistor and the P-channel transistor.

Next, as shown in FIG. 1B, after the resist 5 is patterned by using the photolithography method, unnecessary portions of the resist 5 are removed by the RIE method to form a desired resist 5a. Then, using the remaining resist 5a as a mask, the exposed region of the gate electrode layer 4 and the gate insulating film 3 thereunder are removed by etching. As a result, the gate electrode layer 4a as the gate electrode of the MOS transistor and the gate insulating film 3a are formed.

Thereafter, as shown in FIG. 1C, the resist 5a on the gate electrode layer 4a is removed. Then, on the P-type semiconductor substrate 1 on which the gate electrode layer 4a is formed, a resist for injecting ions, which will be described later, into desired portions is applied. Further, a desired resist 8 is formed by removing a part of the resist so that the gate electrode layer 4a and its peripheral region (which will be a diffusion layer later) are exposed.
Here, the resist 8 is formed in the P-channel transistor region which does not require ion implantation for forming the N diffusion layer.

Next, as shown in FIG.
In the resist 8 remaining in the step (c), the end portion on the gate electrode layer 4a side (the corner portion on the left side of the paper surface of the resist 8) is chamfered by a thinner peeling method to form a resist 8a having a tapered portion. To do.

Here, the thinner stripping method is a method of stripping the resist by immersing the resist in a thinner as a liquid. When a certain region is subjected to thinner treatment, the end portions of the region tend to react more strongly than the central portion. Therefore, the resist after being subjected to the thinner peeling method has a chamfered shape such that the end portions are sloping.

Further, the resist 8a having the chamfered portion formed by the thinner peeling method has sufficient resistance to the ion implantation in the implantation rotation step described below. That is, in the P-channel transistor region where it is not desired to implant the ions, the ions are not resist 8a.
The resist 8a has a necessary minimum thickness so as not to cause a problem such as penetration through.

Then, as shown in FIG. 2 (b), ions such as phosphorus are obliquely implanted downward of the gate electrode layer 4a by the oblique rotation implantation method using the gate electrode layer 4a and the resist 8a as a mask. (This is the direction indicated by the dashed arrow in the figure.). As a result, ions are implanted just below the end of the gate electrode layer 4a. Here, the gate electrode layer 4
Since the end portion of the resist 8a adjacent to a is chamfered, an ion implantation angle β larger than the ion implantation angle α when not chamfered can be secured.

Therefore, the width for forming the N layer 10
Even if L is narrow, the gate electrode layer 4a faces from the end to the center.
Therefore, ions can be implanted relatively deeply. That
Then, due to the ions implanted here, the LDD structure MOS
N of the N layer 10 of the transistor ⁻A layer is formed. In addition,
In the ion implantation process, for example, phosphorus is implanted at an energy of 8
0 keV, dose 5 × 10^Thirteencm^-2Inject at
It can be done under certain conditions.

After that, the gate electrode layer 4a and the resist 8 are formed.
Using a as a mask, P toward the source / drain regions
An N ⁺ layer in the N layer 10 is formed by implanting ions of arsenic or the like into the type semiconductor substrate 1 from the vertical direction. As described above, the LDD structure MOS transistor having the N layer 10 including the N ⁺ layer and the N ⁻ layer is formed.

As described above, in the first embodiment, the shadowing due to the resist used in the process of forming the LDD structure MOS transistor does not occur.
A highly reliable semiconductor device manufacturing method and a semiconductor device can be provided.

In the first embodiment, the resist 8 having a rectangular cross section is used to take advantage of the characteristics of the thinner processing.
A chamfered resist 8a was formed. On the contrary,
The chamfered resist 8a can be formed by taking advantage of the characteristics of the ashing process. That is, in the step of FIG. 2A, the ashing process is used instead of the thinner stripping method to form the tapered resist 8a. Here, when an ashing process is performed on a certain region, the end portions of the region tend to react more strongly than the central portion, as in the thinner process. Therefore, the resist after being subjected to the relatively weak ashing treatment has a chamfered shape such that the end portions are sloping like the resist subjected to the thinner treatment. The ashing condition for forming the chamfered resist 8a is, for example, O
Gas flow rate 400 sccm, pressure 1T in ₂ gas atmosphere
Orr (133.3 Pa) and temperature may be 140 ° C. This ashing condition is adjusted to be smaller than the ashing condition when removing all the resist 8.

In the first embodiment, the chamfered resist 8a is formed on the resist 8 having a rectangular cross section by utilizing the characteristics of the thinner peeling method. On the other hand, the chamfered resist 8a can be formed by taking advantage of the characteristics of heat treatment (cure). That is,
In the step of FIG. 2A, heat treatment is used instead of the thinner stripping method to form the tapered resist 8a. This utilizes the characteristic that when the resist is heat-treated, the end portions of the resist contract to form a chamfered shape.

Although the present invention is applied to the N-channel transistor region in the first embodiment, the present invention can also be applied to the P-channel transistor region. That is, in order to form a diffusion layer composed of a P ⁺ layer and a P ⁻ layer on an N-type semiconductor substrate, a tapered resist may be formed on the N-channel transistor region and oblique rotation implantation of ions may be performed. it can. Also in this case, the same effect as that of the first embodiment can be obtained.

Here, in the first embodiment, the resist 8 is used.
Although the shape of the chamfered portion a is shown as the C surface for simplicity, the shape may not be a clean chamfered shape depending on the degree of thinner treatment. However, even in that case, the effect of the first embodiment can be obtained by ensuring the desired injection angle β.

Embodiment 2. The second embodiment of the present invention will be described in detail with reference to FIGS. Fig.3 (a)-
FIGS. 4B and 4A to 4B are schematic cross-sectional views showing the semiconductor device in each step of the method for manufacturing the semiconductor device according to the second embodiment of the present invention. Second Embodiment
The method of manufacturing a semiconductor device according to the first embodiment is different from the first embodiment in that the chamfered portion of the resist is formed under the exposure conditions in the photolithography process instead of the thinner peeling method.

First, as shown in FIG. 3A, an element isolation insulating film 2 is formed on a P-type semiconductor substrate 1 as a substrate, as in the first embodiment. Then, on the P-type semiconductor substrate 1, the gate insulating film 3, the gate electrode layer 4, the resist 5 are formed.
Are sequentially formed.

Next, as shown in FIG. 3B, the desired resist 5 patterned by the photolithography method and the RIE method is applied as in the first embodiment.
a is formed. Then, using the remaining resist 5a as a mask, the exposed region of the gate electrode layer 4 is removed by etching.

After that, as shown in FIG. 4A, the resist 5a on the gate electrode layer 4a is removed. Then, on the P-type semiconductor substrate 1 on which the gate electrode layer 4a is formed, a resist for injecting ions, which will be described later, into desired portions is applied.

Then, an exposure device (not shown) exposes the surface of the resist formed on the P-type semiconductor substrate 1 to the desired resist 18 which will be described later. That is, when the negative resist is used, the desired resist 18 region becomes the exposure region, and when the positive resist is used, the region other than the desired resist 18 region becomes the exposure region.

Here, a filter for reducing the exposure amount at the end of the exposure area of the resist 5 is installed at a position conjugate with the field stop of the exposure apparatus. Specifically, for example, a donut-shaped filter in which a filter is formed only on the peripheral portion is installed at the light source position of the exposure apparatus or at a position optically conjugate with it. As a result, in the exposed area on the resist, the exposure amount at the end is reduced. Then, in the step of removing the resist, which will be described below, unnecessary resist can be removed and the remaining end portions of the resist can be chamfered.

Thereafter, a part of the resist 5 is removed so that the gate electrode layer 4a and its peripheral region (which will be a diffusion layer later) are exposed, and the remaining resist is on the gate electrode 4a side. The end portion is chamfered to form a desired resist 18. Then, as shown in FIG. 4B, as in the first embodiment, by the oblique rotation injection method,
Ions such as phosphorus are implanted obliquely downward from the gate electrode layer 4a using the resist 18 and the like as a mask (the direction indicated by the broken line arrow in the figure). Thus, the N ⁻ layer is formed immediately below the end portion of the gate electrode layer 4a.

The resist 18 having the chamfered portion is
It has sufficient resistance to the ion implantation in the above-mentioned implantation rotation step. That is, in the P-channel transistor region where it is not desired to implant ions, a problem such as penetrating the resist 18 does not occur,
The resist 18 has a required minimum thickness.

Then, as in the first embodiment, ions of arsenic or the like are vertically implanted into the P-type semiconductor substrate 1 toward the source / drain regions by using the gate electrode layer 4a or the like as a mask. Therefore, N in the N layer 10
⁺ Layer is formed. As described above, the LDD structure MOS transistor having the N layer 10 including the N ⁺ layer and the N ⁻ layer is formed.

As described above, also in the second embodiment, as in the first embodiment, the LDD structure MOS is formed.
A highly reliable manufacturing method of a semiconductor device and a semiconductor device in which shadowing due to a resist used in a transistor formation step does not occur can be provided.

In the second embodiment, a filter for reducing the exposure amount at the edge of the exposure area of the resist 5 is provided at a position conjugate with the field stop of the exposure device, so that the edge of the exposure area on the resist 5 is exposed. After that, the resist 18 having a chamfered portion was formed. On the contrary,
By intentionally shifting the focus when the exposure area of the resist 5 is exposed by the exposure device, the intensity of light at the end portion in the exposure area, that is, the exposure amount (light intensity × time) is adjusted. Thus, the resist 18 having the chamfered portion can be formed.

Specifically, for example, when an i-line stepper is used as the exposure apparatus, the stage on which the semiconductor device is mounted is moved vertically with respect to the exposure apparatus, and the resist 5 is removed.
The focus position (focus position) on the surface is 0.1-0.2μ
Exposure is performed so as to shift by m. In this way, when the exposure is performed with the focal position shifted with respect to the surface of the resist 5, weak light is irradiated at the boundary between the exposed area and the non-exposed area, and the resist in that portion reacts weakly. .
Thereby, in the step of removing the resist described below, unnecessary resist can be removed and the remaining end portion of the resist can be chamfered.

Embodiment 3. The third embodiment of the present invention will be described in detail with reference to FIGS. FIG. 5 (a)-
6C and 6A to 6B are schematic cross-sectional views showing the semiconductor device in each step of the method for manufacturing the semiconductor device according to the third embodiment of the present invention. Third Embodiment
The method of manufacturing a semiconductor device according to the third embodiment differs from the above-described embodiments in that a resist is formed in two steps in a region where ion implantation is unnecessary.

First, as shown in FIG. 5A, the element isolation insulating film 2 is formed on the P-type semiconductor substrate 1 as in the above-described embodiments. Then, the gate insulating film 3, the gate electrode layer 4, and the resist 5 are sequentially formed on the P-type semiconductor substrate 1. Next, as shown in FIG. 5B, a desired patterned resist 5a is formed by performing a photolithography method and an RIE method, as in the above-described embodiments. Then, using the remaining resist 5a as a mask, the exposed region of the gate electrode layer 4 and the like are removed by etching.

After that, as shown in FIG. 5C, the resist 5a on the gate electrode layer 4a is removed. Then, a thin-film first resist is applied on the P-type semiconductor substrate 1 on which the gate electrode layer 4a is formed. Here, the film thickness of the first resist is relatively thin, for example, about 0.5 μm. Then, the first resist 28 having a desired shape is formed through processing by the photolithography method.

Then, as shown in FIG. 6A, a second resist is applied on the P-type semiconductor substrate 1 shown in FIG. 5C. Here, the film thickness of the second resist is also relatively small, and the combined film thickness of the first resist and the second resist is almost the same as the film thickness of the resists 8a and 18 in each of the above-described embodiments.

Then, the second resist 29 having a desired shape is formed through the processing by the photolithography method. Here, in the exposure step when forming the second resist 29, the opening of the second resist 29 (the region where the second resist 29 does not exist) is changed to the opening of the first resist 28 (the first resist 29).
This is a region without the resist 28. The exposure amount to the resist is adjusted so that the opening area becomes larger than that of (1).
Specifically, when the first resist 28 and the second resist 29 are positive resists, the exposure amount when forming the second resist 29 is larger than the exposure amount when forming the first resist 28. To do.

As described above, when the exposure amount applied to the resist surface is increased, the reaction proceeds in a wider range than when the exposure amount is small. As a result, stepped resists 28 and 29 can be formed. The first
Even when the resist 28 and the second resist 29 are negative resists, by setting the exposure amount when forming the second resist 29 smaller than the exposure amount when forming the first resist 28, Step-shaped resists 28 and 29 can be formed.

Then, as shown in FIG. 6B, the first resist 28 and the second resist 2 are formed by the oblique rotation injection method.
Using 9 as a mask, ions such as phosphorus are implanted obliquely downward from the gate electrode layer 4a. Thus, the N ⁻ layer is formed immediately below the end portion of the gate electrode layer 4a.

After that, using the gate electrode layer 4a, the first resist 28, and the second resist 29 as masks, ions of arsenic or the like are vertically injected into the P-type semiconductor substrate 1 toward the source / drain regions. Thus, the N ⁺ layer in the N layer 10 is formed. As described above, the LDD structure MOS transistor having the N layer 10 including the N ⁺ layer and the N ⁻ layer is formed.

As described above, in the third embodiment, since the step-shaped resists 28 and 29 are formed to secure a large implantation angle β, shadowing by the resist used in the process of forming the LDD structure MOS transistor is performed. It is possible to provide a highly reliable method for manufacturing a semiconductor device and a semiconductor device which are free from the above problems.

In the third embodiment, the resist 2 is used.
Although 8 and 29 are formed by being divided into two steps, the number of dividing steps is not limited to this. That is, it is possible to form a stepped resist having a number of steps larger than two. Then, also in that case, the same effect as that of the third embodiment can be obtained.

Fourth Embodiment A fourth embodiment of the present invention will be described in detail with reference to FIG. 7 is a schematic cross-sectional view showing a semiconductor device in a second resist forming step in a method of manufacturing a semiconductor device according to a fourth embodiment of the present invention. The semiconductor device manufacturing method according to the fourth embodiment is similar to the third embodiment in that the resist is formed twice in a region where ion implantation is not necessary, but the upper end of the resist is not formed. The chamfered shape is different from that of the third embodiment. That is, the fourth embodiment is a combination of the first or second embodiment and the third embodiment.

In the fourth embodiment, first, the same steps as the steps shown in FIGS. 5A to 5C in the third embodiment are performed. Here, illustration and description of steps corresponding to FIGS. 5A to 5C are omitted. The first resist 38 in the fourth embodiment is the same as the first resist 38 in the third embodiment.
Corresponds to the resist 28. That is, the first resist 38
Is formed by subjecting the thin-film first resist applied on the P-type semiconductor substrate 1 having the gate electrode layer 4a formed thereon to a photolithography process, as in the third embodiment.

Then, as shown in FIG. 7, a second resist is applied on the P-type semiconductor substrate 1 on which the first resist 38 is formed. Then, the second resist 39 having a desired shape is formed through processing by the photolithography method. Here, unlike the third embodiment, the exposure amount for the second resist 39 in the exposure step for forming the second resist 39 is set equal to the exposure amount for forming the first resist 38. . As a result, the opening of the second resist 39 has the same opening area as the opening of the first resist 38.

Thereafter, the second resist 39 on the upper stage is subjected to an ashing process to remove the gate electrode 4a of the second resist 39.
Chamfer the side edges. Here, the first resist 38 and the second resist 38
The resist 39 is a resist having a different selection ratio. Specifically, the etching rate of the first resist 38 is
It is lower than the etching rate of the resist 39.
As a result, the influence of the ashing process on the second resist 39 on the first resist 38 is reduced. That is, since the first resist 38 maintains its original shape substantially even after the ashing process is performed, it is possible to relieve the implantation stress in the subsequent ion implantation process and to suppress problems such as ion implantation punch-through. . This means that the first resist 38 and the second resist 3
By changing the selection ratio with respect to 9
This means that the workability of Nos. 8 and 39 is improved.

After that, although not shown, the gate electrode layer 4 is formed by the oblique rotation implantation method as in each of the above-described embodiments.
Using a, the first resist 38, and the second resist 39 as masks, ions such as phosphorus are implanted obliquely downward from the gate electrode layer 4a. Thereby, the gate electrode layer 4a
An N ⁻ layer is formed immediately below the edge.

Further, using the gate electrode layer 4a, the first resist 38, and the second resist 39 as a mask, ions of arsenic or the like are vertically injected into the P-type semiconductor substrate 1 toward the source / drain regions. Thus, the N ⁺ layer in the N layer 10 is formed. As described above, the LDD structure MOS transistor having the N layer 10 including the N ⁺ layer and the N ⁻ layer is formed.

As described above, in the fourth embodiment, the chamfered portion is formed in the upper second resist 39 of the two resists 38 and 39 to secure a large implantation angle β, so that the LDD structure is obtained. It is possible to provide a highly reliable manufacturing method of a semiconductor device and a semiconductor device in which shadowing due to a resist used in a process of forming a MOS transistor does not occur.

In the fourth embodiment, two layers of resists 38 and 39 are formed in the P-channel transistor region and then ashing is performed to form an upper layer second resist 39.
A chamfered portion was formed on the. On the other hand, after forming the two layers of resists 38 and 39, it is possible to form a chamfered portion on the second resist 39 by performing a thinner peeling method or a heat treatment.

In the fourth embodiment, the chamfered portion is formed in the upper second resist 39 after the two resists 38 and 39 are formed in the P-channel transistor region. This is a combination of the third form and the third form. On the other hand, even in the mode in which the second embodiment and the third embodiment are combined, the same effect as in the fourth embodiment can be obtained. That is, after the first resist is formed in the P-channel transistor region, the chamfered portion is subjected to the exposure process of shifting the focus position of the second embodiment on the second resist or the exposure process of installing the filter at the field stop position. Desired second having
The resist 39 can be formed.

In each of the above embodiments, the present invention is applied to the process of forming a CMOC transistor having an LDD structure. The present invention can be similarly applied.

It should be noted that the present invention is not limited to the above-mentioned respective embodiments, and the respective embodiments may be appropriately modified within the scope of the technical idea of the present invention, in addition to those suggested in the respective embodiments. That is clear. Also, the number of the above-mentioned constituent members,
The position, shape, etc. are not limited to those in the above-described embodiment, and can be any number, position, shape, etc. suitable for carrying out the present invention.

[0075]

Since the present invention is configured as described above, it is possible to provide a method of manufacturing a semiconductor device having a highly reliable LDD structure MOS transistor which does not cause shadowing.

[Brief description of drawings]

FIG. 1 is a schematic cross-sectional view showing a semiconductor device in each step in a method of manufacturing a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a schematic cross-sectional view showing a semiconductor device in each step following FIG.

FIG. 3 is a schematic cross-sectional view showing the semiconductor device in each step of the method of manufacturing the semiconductor device according to the second embodiment of the present invention.

FIG. 4 is a schematic cross-sectional view showing the semiconductor device in each step following FIG.

FIG. 5 is a schematic cross-sectional view showing the semiconductor device in each step of the method of manufacturing the semiconductor device according to the third embodiment of the present invention.

FIG. 6 is a schematic cross-sectional view showing a semiconductor device in each step following FIG.

FIG. 7 is a schematic cross-sectional view showing a semiconductor device in a second resist forming step in a method of manufacturing a semiconductor device according to a fourth embodiment of the present invention.

FIG. 8 is a schematic sectional view showing a conventional semiconductor device.

FIG. 9 is a schematic cross-sectional view showing a semiconductor device in each step in a conventional method for manufacturing a semiconductor device.

10 is a schematic cross-sectional view showing the semiconductor device in the ion rotation implantation step of FIG.

[Explanation of symbols]

1 P-type semiconductor substrate (substrate), 2 element isolation insulating film, 3 and 3a gate insulating film, 4 and 4a gate electrode layer (gate electrode), 5 and 5a resist, 8 and 8a,
18, 48 resist, 10 N layer, 10a N
⁺ Layer, 10b, 10c N ^- layer, 28, 38 1st
Resist, 29, 39 Second resist.

─────────────────────────────────────────────────── ─── Continued Front Page (51) Int.Cl. ⁷ Identification Code FI Theme Coat (Reference) H01L 29/78 H01L 29/78 301P

Claims (12)

[Claims] 1. A step of applying a resist on a substrate having a gate electrode formed thereon, a step of removing a part of the resist so that the gate electrode is exposed, and a step of removing a part of the resist. And a step of chamfering the end portion of the resist remaining on the side of the gate electrode by a thinner peeling method. 2. A step of applying a resist on a substrate on which a gate electrode is formed, and a step of reducing an exposure amount at an end portion of the exposure area at a position conjugate with a field stop of an exposure device which exposes the exposure area of the resist. A semiconductor device comprising: a step of providing a filter; and a step of removing a part of the resist so that the gate electrode is exposed and chamfering an end of the resist on the gate electrode side. Production method. 3. A step of applying a first resist on a substrate on which a gate electrode is formed, a step of removing a part of the first resist so that the gate electrode is exposed, and a step of removing the first resist on the first resist. After the step of applying the second resist and the step of removing a part of the first resist, after adjusting the exposure amount to the second resist so that the opening is larger than the remaining opening of the first resist, And a step of removing a portion of the second resist. 4. A step of applying a first resist on a substrate on which a gate electrode is formed, a step of removing a part of the first resist so that the gate electrode is exposed, and a step of applying a resist on the first resist. A step of applying a second resist, and a step of removing a part of the second resist so as to have an opening equivalent to the opening of the first resist remaining in the step of removing a part of the first resist. And a step of chamfering the gate electrode side end of the second resist remaining in the step of removing a part of the second resist. 5. The method of manufacturing a semiconductor device according to claim 4, wherein the chamfering step is an ashing step. 6. The method of manufacturing a semiconductor device according to claim 4, wherein the chamfering step is a heat treatment step. 7. The method for manufacturing a semiconductor device according to claim 4, wherein the chamfering step is a step using a thinner peeling method. 8. A step of applying a first resist on a substrate having a gate electrode formed thereon, a step of removing a part of the first resist so that the gate electrode is exposed, and a step of removing the first resist on the first resist. In the step of applying a second resist and in the step of removing a part of the first resist, while removing a part of the second resist so as to have an opening equivalent to the opening of the first resist remaining, And a step of chamfering the remaining end of the second resist on the side of the gate electrode. 9. The method of manufacturing a semiconductor device according to claim 8, further comprising the step of exposing the exposure area of the second resist while defocusing it. 10. The method further comprising the step of providing a filter for reducing an exposure amount at an end portion of the exposure area at a position conjugate with a field stop of an exposure device for exposing the exposure area of the second resist. 8. The method for manufacturing a semiconductor device according to item 8. 11. The method of manufacturing a semiconductor device according to claim 3, wherein an etching rate of the first resist is lower than an etching rate of the second resist. 12. The method of manufacturing a semiconductor device according to claim 1, further comprising the step of rotationally implanting ions from a diagonal direction toward the lower side of the gate electrode.