JPH07326745A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH07326745A
JPH07326745A JP11847294A JP11847294A JPH07326745A JP H07326745 A JPH07326745 A JP H07326745A JP 11847294 A JP11847294 A JP 11847294A JP 11847294 A JP11847294 A JP 11847294A JP H07326745 A JPH07326745 A JP H07326745A
Authority
JP
Japan
Prior art keywords
film
mask
conductivity type
layer
nitride film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11847294A
Other languages
Japanese (ja)
Inventor
Toshimitsu Taniguchi
敏光 谷口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP11847294A priority Critical patent/JPH07326745A/en
Publication of JPH07326745A publication Critical patent/JPH07326745A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To contrive the improvement of a method of forming the so-called twin well, which is used in a semiconductor device which is made progress in high miniaturization. CONSTITUTION:An oxide film 12, a first nitride film 13, a polysilicon layer 14 and a second nitride film 15 are formed in order on a semiconductor substrate 11, a resist film 16 is selectively formed on the film 15, the film 15 is removed by etching using the film 16 as a mask, one conductivity type impurities are implanted using the films 16 and 15 as masks and a one conductivity type impurity region layer 17 is formed in the surface layer of the substrate 11. Moreover, the layer 14 is selectively oxidized using the film 15 as a mask to form a selective oxide film 18 on the layer 17, the film 15 is removed, reverse conductivity type impurities are implanted using the film 18 as a mask and a reverse conductivity type impurity region layer 19 is formed in the surface layer of the substrate 11.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は半導体装置の製造方法に
関し、更に詳しく言えば、高微細化が進んだ半導体装置
に用いられるいわゆるツインウエルの形成方法の改善に
関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to an improvement in a so-called twin well forming method used for a semiconductor device which has been highly miniaturized.

【0002】[0002]

【従来の技術】以下で、従来例に係る半導体装置の製造
方法について図面を参照しながら説明する。MOSFE
Tなどの半導体装置を形成するときには、n型の不純物
拡散層(n−well)とp型の不純物拡散層(p−w
ell)とが隣接して形成されてなる、いわゆるツイン
ウエルを形成する場合がある。
2. Description of the Related Art A conventional method of manufacturing a semiconductor device will be described below with reference to the drawings. MOSFE
When forming a semiconductor device such as T, an n-type impurity diffusion layer (n-well) and a p-type impurity diffusion layer (p-w) are formed.
cell) may be formed adjacent to each other to form a so-called twin well.

【0003】この場合、n−wellとp−wellと
を、別々のマスク工程で形成するには、まずマスク工程
が2回必要であり、さらにn−wellとp−well
のマスクの位置合わせのずれ分を考慮して、両者の境界
に、余裕をもった空き領域を作らなければならないの
で、その空き領域の分だけ微細化ができなくなる。よっ
て、両者をセルフアラインで形成してマスク工程を1回
で済ませたいという要求がある。
In this case, in order to form the n-well and the p-well in separate mask processes, the mask process needs to be performed twice, and the n-well and p-well are further required.
In consideration of the misalignment of the mask alignment, it is necessary to create a vacant area with a margin at the boundary between the two, so miniaturization cannot be achieved by the vacant area. Therefore, there is a demand for forming both of them by self-alignment so as to complete the mask process only once.

【0004】その一法として、LOCOS(Local Oxid
ation of Silicon)法による選択酸化膜を形成する方法
が提案されている。以下でその方法について図11〜図
14を参照しながら説明する。まず、図11に示すよう
に、シリコン基板(1)上にSiO2膜(2)、SiN 膜
(3)を順次形成し、のちにp−wellが形成される
領域が露出するようにレジスト膜(4)を選択形成し、
レジスト膜(4)をマスクにしてSiN 膜(3)をエッチ
ング・除去してボロン(B)をイオン注入し、p−we
ll(5)を形成する。
One of the methods is LOCOS (Local Oxid).
A method of forming a selective oxide film by the cation of silicon) method has been proposed. The method will be described below with reference to FIGS. 11 to 14. First, as shown in FIG. 11, a SiO2 film (2) and a SiN film (3) are sequentially formed on a silicon substrate (1), and then a resist film (so as to expose a region where a p-well is formed). 4) Selectively form
Using the resist film (4) as a mask, the SiN film (3) is etched and removed, boron (B) is ion-implanted, and p-we
to form 11 (5).

【0005】次に、レジスト膜(4)を除去し、図12
に示すようにSiO2膜(2)をLOCOS法によって選択
酸化して、p−well(5)上に選択酸化膜(6)を
選択形成する。次いで、SiN 膜(3)を除去し、図13
に示すように選択酸化膜(6)をマスクにして燐(P)
イオンを注入し、n−well(7)を形成する。
Next, the resist film (4) is removed, and FIG.
As shown in FIG. 3, the SiO2 film (2) is selectively oxidized by the LOCOS method to selectively form the selective oxide film (6) on the p-well (5). Then, the SiN film (3) is removed, and FIG.
As shown in, phosphorus (P) is used with the selective oxide film (6) as a mask.
Ions are implanted to form an n-well (7).

【0006】その後、図14に示すように、全面の選択
酸化膜(6)及びSiO2膜(2)をエッチング・除去し
て、p−well(5),n−well(7)の表面を
露出する。以上により、セルフアラインで位置合わせの
ずれを考慮した空き領域を形成する必要がないツインウ
エルを形成していた。
Thereafter, as shown in FIG. 14, the selective oxide film (6) and the SiO2 film (2) on the entire surface are etched and removed to expose the surfaces of the p-well (5) and the n-well (7). To do. As described above, the twin well is formed by self-alignment in which it is not necessary to form a vacant region in consideration of misalignment.

【0007】[0007]

【発明が解決しようとする課題】しかしながら、上記従
来の製造方法によると、セルフアラインでツインウエル
を形成することはできるものの、図12に示すように、
選択酸化膜(6)を形成する際に、半導体基板(1)の
表面まで酸化されて、p−well(5)上の選択酸化
膜(6)が半導体基板(1)の表層にめりこんでしま
う。
However, according to the above conventional manufacturing method, although the twin well can be formed by self-alignment, as shown in FIG.
When the selective oxide film (6) is formed, the surface of the semiconductor substrate (1) is oxidized and the selective oxide film (6) on the p-well (5) is embedded in the surface layer of the semiconductor substrate (1). I will end up.

【0008】このため、その後n−well(7)を形
成すると、n−well(7)の表層は平坦なので、選
択酸化膜(6)を除去した後に半導体基板(1)の表面
に約3000Å程度の段差(ΔL)が形成されてしま
い、平坦性が損なわれてしまうといった問題が生じてい
た。
For this reason, when the n-well (7) is formed thereafter, the surface layer of the n-well (7) is flat. Therefore, after removing the selective oxide film (6), the surface of the semiconductor substrate (1) is about 3000 Å. The level difference (ΔL) is formed and the flatness is impaired.

【0009】[0009]

【課題を解決するための手段】本発明は上記従来の欠点
に鑑み成されたもので、図1〜図5に示すように、半導
体基板(11)上に酸化膜(12)、第1の窒化膜(1
3)、ポリシリコン層(14)及び第2の窒化膜(1
5)を順次形成する工程と、前記第2の窒化膜(15)
上にレジスト膜(16)を選択形成し、該レジスト膜
(16)をマスクにして、前記第2の窒化膜(15)を
エッチング・除去する工程と、前記レジスト膜(16)
及び前記第2の窒化膜(15)をマスクにして一導電型
の不純物を注入し、前記半導体基板(11)の表層に一
導電型不純物領域層(17)を形成する工程と、前記第
2の窒化膜(15)をマスクにして前記ポリシリコン層
(14)を選択酸化して前記一導電型不純物領域層(1
7)上に選択酸化膜(18)を形成する工程と、前記第
2の窒化膜(15)を除去し、前記選択酸化膜(18)
をマスクにして逆導電型の不純物を注入し、前記半導体
基板(11)の表層に逆導電型不純物領域層(19)を
形成する工程とを有することにより、セルフアラインで
段差のないツインウエルの形成が可能になる半導体装置
の製造方法を提供するものである。
The present invention has been made in view of the above-mentioned conventional drawbacks. As shown in FIGS. 1 to 5, an oxide film (12) and a first oxide film (12) are formed on a semiconductor substrate (11). Nitride film (1
3), the polysilicon layer (14) and the second nitride film (1
5) step of sequentially forming the second nitride film (15)
A step of selectively forming a resist film (16) on the upper surface, etching and removing the second nitride film (15) using the resist film (16) as a mask, and the resist film (16)
And a step of implanting an impurity of one conductivity type using the second nitride film (15) as a mask to form an impurity region layer (17) of one conductivity type in a surface layer of the semiconductor substrate (11); Of the first conductivity type impurity region layer (1) by selectively oxidizing the polysilicon layer (14) using the nitride film (15) of (1) as a mask.
7) a step of forming a selective oxide film (18) thereon, and removing the second nitride film (15) to remove the selective oxide film (18).
And a step of injecting an impurity of opposite conductivity type to form an impurity region layer (19) of opposite conductivity type on the surface layer of the semiconductor substrate (11) by self-alignment without a step. A method of manufacturing a semiconductor device that can be formed.

【0010】[0010]

【作 用】本発明に係る第1の半導体装置の製造方法に
よれば、図1〜図5に示すように、半導体基板(11)
上に酸化膜(12)、第1の窒化膜(13)、ポリシリ
コン層(14)及び第2の窒化膜(15)を順次形成
し、第2の窒化膜(15)とレジスト膜(16)とをパ
ターニングし、これらをマスクにして一導電型の不純物
を注入し、半導体基板(11)の表層に一導電型不純物
領域層(17)を形成し、第2の窒化膜(15)をマス
クにしてポリシリコン層(14)を選択酸化して一導電
型不純物領域層(17)上に選択酸化膜(18)を形成
し、第2の窒化膜(15)を除去し、選択酸化膜(1
8)をマスクにして逆導電型の不純物を注入し、半導体
基板(11)の表層に逆導電型不純物領域層(19)を
形成している。
[Operation] According to the first method for manufacturing a semiconductor device of the present invention, as shown in FIGS.
An oxide film (12), a first nitride film (13), a polysilicon layer (14) and a second nitride film (15) are sequentially formed on the second nitride film (15) and a resist film (16). ) And are used as a mask to implant an impurity of one conductivity type to form an impurity region layer (17) of one conductivity type on the surface layer of the semiconductor substrate (11) and to form a second nitride film (15). Using the mask as a mask, the polysilicon layer (14) is selectively oxidized to form a selective oxide film (18) on the one conductivity type impurity region layer (17), the second nitride film (15) is removed, and the selective oxide film is removed. (1
Reverse conductivity type impurities are implanted using 8) as a mask to form a reverse conductivity type impurity region layer (19) on the surface layer of the semiconductor substrate (11).

【0011】このため、ポリシリコン層(14)を選択
酸化して選択酸化膜(18)を形成する工程の際に、ポ
リシリコン層(14)の下に、第1の窒化膜(13)が
設けられているので、ポリシリコン層(14)の酸化は
ここで止まり、その下の半導体基板(11)が酸化され
ることが防止されているので、選択酸化膜(18)は半
導体基板(11)の表層にはめりこまない。
Therefore, in the step of selectively oxidizing the polysilicon layer (14) to form the selective oxide film (18), the first nitride film (13) is formed below the polysilicon layer (14). Since it is provided, the oxidation of the polysilicon layer (14) is stopped here, and the semiconductor substrate (11) thereunder is prevented from being oxidized, so that the selective oxide film (18) is formed on the semiconductor substrate (11). ) Does not go into the surface.

【0012】これにより、その後選択酸化膜(18)を
マスクにして逆導電型の不純物を注入し、半導体基板
(11)の表層に逆導電型不純物領域層(19)を形成
しても、選択酸化膜(18)が半導体基板(11)にめ
りこんでいないので、従来このことによって生じていた
段差の発生を極力抑止することができ、半導体基板表面
の平坦性が損なわれることを極力抑止し、かつセルフア
ラインでツインウエルを形成することが可能となる。
As a result, even if the opposite conductivity type impurity is implanted by using the selective oxide film (18) as a mask and the opposite conductivity type impurity region layer (19) is formed on the surface layer of the semiconductor substrate (11), the selection is performed. Since the oxide film (18) does not sink into the semiconductor substrate (11), it is possible to suppress the generation of a step which has been conventionally caused by this as much as possible, and to prevent the flatness of the semiconductor substrate surface from being impaired as much as possible. Moreover, it is possible to form the twin well by self-alignment.

【0013】また、本発明に係る第2の半導体装置の製
造方法によれば、図6〜図10に示すように、半導体基
板(21)上に酸化膜(22)、ポリシリコン層(2
3)及び窒化膜(24)を順次形成し、窒化膜(24)
及びレジスト膜(25)をパターニングしてこれらをマ
スクにして一導電型の不純物を注入して、半導体基板
(21)の表層に一導電型不純物領域層(26)を形成
し、窒化膜(24)をマスクにし、適当な条件で半導体
基板(21)が酸化されない程度にポリシリコン層(2
3)を選択酸化して一導電型不純物領域層(26)上に
選択酸化膜(27)を形成している。
According to the second method for manufacturing a semiconductor device of the present invention, as shown in FIGS. 6 to 10, an oxide film (22) and a polysilicon layer (2) are formed on a semiconductor substrate (21).
3) and a nitride film (24) are sequentially formed to form a nitride film (24)
And the resist film (25) is patterned and one conductivity type impurities are implanted using these as a mask to form a one conductivity type impurity region layer (26) on the surface layer of the semiconductor substrate (21), and the nitride film (24 ) As a mask, and the polysilicon layer (2
3) is selectively oxidized to form a selective oxide film (27) on the one conductivity type impurity region layer (26).

【0014】このため、選択酸化膜(27)を形成する
際に、適当な酸化条件を選択することで半導体基板(2
1)が酸化されることが防止されているので、選択酸化
膜(27)は半導体基板(21)の表層にはめりこまな
い。これにより、選択酸化膜(21)が半導体基板(2
1)にめりこむことによって従来生じていた段差の発生
を極力抑止することができるので、半導体基板表面の平
坦性が損なわれることを極力抑止し、かつセルフアライ
ンでツインウエルを形成することが可能となる。
Therefore, when the selective oxidation film (27) is formed, the semiconductor substrate (2
Since 1) is prevented from being oxidized, the selective oxide film (27) does not sink into the surface layer of the semiconductor substrate (21). As a result, the selective oxide film (21) is removed from the semiconductor substrate (2).
Since it is possible to suppress the generation of a step which has been conventionally caused by being recessed into 1), it is possible to prevent the flatness of the semiconductor substrate surface from being impaired as much as possible, and it is possible to form a twin well by self-alignment. Become.

【0015】[0015]

【実施例】【Example】

(1)第1の実施例 以下で、本発明の第1の実施例に係る半導体装置の製造
方法について図面を参照しながら説明する。まず、図1
に示すように、シリコン基板(11)上に膜厚200〜
300Åの酸化膜(12)、膜厚100〜200Åの第
1の窒化膜(13)、膜厚2000〜3000Åのポリ
シリコン層(14)及び膜厚1000Åの第2の窒化膜
(15)を順次形成する。
(1) First Example Hereinafter, a method for manufacturing a semiconductor device according to a first example of the present invention will be described with reference to the drawings. First, Fig. 1
As shown in FIG.
An oxide film (12) of 300 Å, a first nitride film (13) of 100 to 200 Å film thickness, a polysilicon layer (14) of 2000 to 3000 Å film thickness and a second nitride film (15) of 1000 Å film thickness are sequentially formed. Form.

【0016】次に、図2に示すように、フォトレジスト
を第2の窒化膜(15)上に塗布し、露光・現像して、
のちにp−well(17)を形成する領域が露出する
ようにパターニングして膜厚1μm程度のレジスト膜
(16)を選択形成し、該レジスト膜(16)をマスク
にして第2の窒化膜(14)をエッチング・除去したの
ちに、レジスト膜(16)及び第2の窒化膜(15)を
マスクにして、ボロン(B)をイオン注入してp−we
ll(17)を形成する。
Next, as shown in FIG. 2, a photoresist is applied on the second nitride film (15), exposed and developed,
After that, patterning is performed so that a region for forming the p-well (17) is exposed to selectively form a resist film (16) having a film thickness of about 1 μm, and the second nitride film is formed using the resist film (16) as a mask. After etching and removing (14), boron (B) is ion-implanted using the resist film (16) and the second nitride film (15) as a mask to p-we
11 (17) is formed.

【0017】次いで、図3に示すように、レジスト膜
(16)を除去し、第2の窒化膜(15)をマスクにし
て、LOCOS法によってポリシリコン層(14)を選
択酸化して膜厚2000〜3000Åの選択酸化膜(1
8)を形成する。この工程において、ポリシリコン層
(14)の下に、耐酸化性を有する第1の窒化膜(1
3)が形成されているので、ポリシリコン層(14)の
酸化はここまでで止まり、その下層のシリコン基板(1
1)までは酸化されない。
Then, as shown in FIG. 3, the resist film (16) is removed, the second nitride film (15) is used as a mask, and the polysilicon layer (14) is selectively oxidized by the LOCOS method to obtain a film thickness. 2000-3000Å selective oxide film (1
8) is formed. In this step, a first nitride film (1) having oxidation resistance is formed under the polysilicon layer (14).
3) is formed, the oxidation of the polysilicon layer (14) is stopped up to this point, and the silicon substrate (1) below it is oxidized.
It is not oxidized until 1).

【0018】このため、従来のようにシリコン基板(1
1)が酸化されて選択酸化膜(18)が基板表面にめり
こむことを抑止できる。次に、図4に示すように第2の
窒化膜(15)及びポリシリコン層(14)を順次ドラ
イエッチングでエッチング・除去し、選択酸化膜(1
8)をマスクにして燐(P)イオンをシリコン基板(1
1)の表層にイオン注入し、n−well(19)を形
成する。
Therefore, the silicon substrate (1
It is possible to prevent the selective oxide film (18) from being dented on the substrate surface due to the oxidation of 1). Next, as shown in FIG. 4, the second nitride film (15) and the polysilicon layer (14) are sequentially etched and removed by dry etching to remove the selective oxide film (1
8) is used as a mask and phosphorus (P) ions are added to the silicon substrate (1
Ions are implanted into the surface layer of 1) to form an n-well (19).

【0019】その後、選択酸化膜(18)及び酸化膜
(12)を除去して、図5に示すように、p−well
(17)、n−well(19)を露出することによ
り、セルフアラインでツインウエルを形成する。これに
より、上述の通り選択酸化膜(18)がシリコン基板
(11)の表面にめりこんでいないので、図14に示す
ように従来選択酸化膜が基板表面にめりこむことによっ
て生じていた段差の発生を極力抑止することができ、シ
リコン基板(11)の平坦性が損なわれることを極力抑
止しつつ、セルフアラインでツインウエルを形成するこ
とが可能となる。
After that, the selective oxide film (18) and the oxide film (12) are removed, and as shown in FIG.
(17) By exposing the n-well (19), twin wells are formed by self-alignment. As a result, since the selective oxide film (18) does not sink into the surface of the silicon substrate (11) as described above, a step which is generated by the conventional selective oxide film sinking into the substrate surface is generated as shown in FIG. Can be suppressed as much as possible, and the twin well can be formed by self-alignment while suppressing the flatness of the silicon substrate (11) as much as possible.

【0020】(2)第2の実施例 以下で、本発明の第2の実施例に係る半導体装置の製造
方法について図面を参照しながら説明する。なお、第1
の実施例と共通する事項については、重複を避けるため
説明を省略する。まず、図6に示すように、シリコン基
板(21)上に膜厚500Åの酸化膜(22)、膜厚2
000〜3000Åのポリシリコン層(23)及び膜厚
1000Å程度の窒化膜(24)を順次形成する。
(2) Second Embodiment A semiconductor device manufacturing method according to the second embodiment of the present invention will be described below with reference to the drawings. The first
The description of the items common to those of the first embodiment will be omitted to avoid duplication. First, as shown in FIG. 6, an oxide film (22) having a film thickness of 500Å and a film thickness of 2 are formed on a silicon substrate (21).
A polysilicon layer (23) having a thickness of 000 to 3000 Å and a nitride film (24) having a film thickness of about 1000 Å are sequentially formed.

【0021】次に、図7に示すように、フォトレジスト
を窒化膜(24)上に塗布し、露光・現像してのちにp
−well(26)を形成する領域が露出するようにパ
ターニングすることにより膜厚1μm程度のレジスト膜
(25)を選択形成し、該レジスト膜(25)をマスク
にして窒化膜(24)をエッチング・除去したのちに、
レジスト膜(25)及び窒化膜(24)をマスクにし
て、ボロン(B)をイオン注入してp−well(2
6)を形成する。
Next, as shown in FIG. 7, a photoresist is applied on the nitride film (24), exposed and developed, and then p.
-A resist film (25) having a film thickness of about 1 μm is selectively formed by patterning so as to expose a region where a well (26) is formed, and the nitride film (24) is etched using the resist film (25) as a mask.・ After removal,
Boron (B) is ion-implanted by using the resist film (25) and the nitride film (24) as a mask to p-well (2
6) is formed.

【0022】次いで、図8に示すように、レジスト膜
(25)を除去し、窒化膜(24)をマスクにして、H
2 Oガスを導入して、温度900℃の条件下で、ポリシ
リコン層(23)を200分選択酸化して膜厚2000
〜3000Åの選択酸化膜(27)を形成する。このと
き、上記の条件を選択することにより、ポリシリコン層
(14)の選択酸化の際に同時にシリコン基板(21)
が酸化されないようにしておく。
Then, as shown in FIG. 8, the resist film (25) is removed, and the nitride film (24) is used as a mask to remove H.
A film thickness of 2000 is obtained by introducing 2 O gas and selectively oxidizing the polysilicon layer (23) for 200 minutes at a temperature of 900 ° C.
A selective oxide film (27) of ˜3000 Å is formed. At this time, by selecting the above conditions, the silicon substrate (21) is simultaneously oxidized during the selective oxidation of the polysilicon layer (14).
Keep it from being oxidized.

【0023】よって、従来のようにシリコン基板(2
1)が酸化されて選択酸化膜(27)が基板表面にめり
こむことを抑止できる。次に、図9に示すように窒化膜
(24)及びポリシリコン層(23)を順次ドライエッ
チングでエッチング・除去し、選択酸化膜(27)をマ
スクにして燐(P)イオンをシリコン基板(21)の表
層にイオン注入し、n−well(28)を形成する。
Therefore, the silicon substrate (2
It is possible to prevent the selective oxide film (27) from invading the substrate surface due to the oxidation of 1). Next, as shown in FIG. 9, the nitride film (24) and the polysilicon layer (23) are sequentially etched and removed by dry etching, and the selective oxide film (27) is used as a mask to remove phosphorus (P) ions from the silicon substrate ( Ions are implanted into the surface layer of 21) to form an n-well (28).

【0024】その後、選択酸化膜(27)及び酸化膜
(22)を除去して、図10に示すように、p−wel
l(26)及びn−well(28)を露出して、ツイ
ンウエルを形成できる。これにより、上述の通り選択酸
化膜(27)がシリコン基板(21)の表面にめりこん
でいないので、図14に示すように従来選択酸化膜が基
板表面にめりこむことによって生じていた段差の発生を
極力抑止することができ、シリコン基板(21)の平坦
性が損なわれることを極力抑止しつつ、セルフアライン
でツインウエルを形成する。
After that, the selective oxide film (27) and the oxide film (22) are removed, and as shown in FIG.
Twin wells can be formed by exposing l (26) and n-well (28). As a result, since the selective oxide film (27) is not recessed into the surface of the silicon substrate (21) as described above, the step generated by the conventional selective oxide film being recessed into the substrate surface is generated as shown in FIG. Can be suppressed as much as possible, and the twin well is formed by self-alignment while suppressing the flatness of the silicon substrate (21) as much as possible.

【0025】また、第1の実施例のように、ポリシリコ
ン層の下層に耐酸化性のある窒化膜を形成せずに、LO
COS酸化の条件を調整することにより、シリコン基板
(21)が酸化されることを抑止しているので、そのた
めの窒化膜を形成しない分だけ、工程の省力化が可能に
なる。
Further, unlike the first embodiment, the LO layer is formed without forming the oxidation resistant nitride film under the polysilicon layer.
Since the oxidation of the silicon substrate (21) is suppressed by adjusting the conditions of COS oxidation, the labor saving of the process can be realized because the nitride film for that is not formed.

【0026】[0026]

【発明の効果】以上説明したように本発明に係る第1の
半導体装置の製造方法によれば、第2の窒化膜(15)
とレジスト膜(16)とをパターニングし、これらをマ
スクにして一導電型の不純物を注入し、半導体基板(1
1)の表層に一導電型不純物領域層(17)を形成し、
第2の窒化膜(15)をマスクにしてポリシリコン層
(14)を選択酸化して一導電型不純物領域層(17)
上に選択酸化膜(18)を形成し、第2の窒化膜(1
5)を除去し、選択酸化膜(18)をマスクにして逆導
電型の不純物を注入し、半導体基板(11)の表層に逆
導電型不純物領域層(19)を形成している。
As described above, according to the first semiconductor device manufacturing method of the present invention, the second nitride film (15) is formed.
And the resist film (16) are patterned, and impurities of one conductivity type are implanted using these as a mask, and the semiconductor substrate (1
Forming a one conductivity type impurity region layer (17) on the surface layer of 1),
The polysilicon layer (14) is selectively oxidized by using the second nitride film (15) as a mask to form the one conductivity type impurity region layer (17).
A selective oxide film (18) is formed on the second nitride film (1
5) is removed, and an impurity of opposite conductivity type is implanted using the selective oxide film (18) as a mask to form an impurity region layer of opposite conductivity type (19) on the surface layer of the semiconductor substrate (11).

【0027】このため、選択酸化膜(18)が半導体基
板(11)にめりこんでいないので、従来このことによ
って生じていた段差の発生を極力抑止することができ、
半導体基板表面の平坦性が損なわれることを極力抑止
し、かつセルフアラインでツインウエルを形成すること
が可能となる。また、本発明に係る第2の半導体装置の
製造方法によれば、窒化膜(24)及びレジスト膜(2
5)をパターニングしてこれらをマスクにして一導電型
の不純物を注入して、半導体基板(21)の表層に一導
電型不純物領域層(26)を形成し、窒化膜(24)を
マスクにし、適当な条件で半導体基板(21)が酸化さ
れない程度にポリシリコン層(23)を選択酸化して一
導電型不純物領域層(26)上に選択酸化膜(27)を
形成している。
For this reason, since the selective oxide film (18) is not embedded in the semiconductor substrate (11), it is possible to suppress the occurrence of a step which has been conventionally caused by this as much as possible.
It becomes possible to prevent the flatness of the surface of the semiconductor substrate from being impaired as much as possible and to form the twin well by self-alignment. Further, according to the second semiconductor device manufacturing method of the present invention, the nitride film (24) and the resist film (2
5) is patterned and one conductivity type impurities are implanted using these as a mask to form a one conductivity type impurity region layer (26) on the surface layer of the semiconductor substrate (21), and the nitride film (24) is used as a mask. The selective oxidation film (27) is formed on the one conductivity type impurity region layer (26) by selectively oxidizing the polysilicon layer (23) to such an extent that the semiconductor substrate (21) is not oxidized under appropriate conditions.

【0028】このため、選択酸化膜(27)を形成する
際に、適当な酸化条件を選択することで半導体基板(2
1)が酸化されることが防止され、選択酸化膜(21)
が半導体基板(21)にめりこむことによって従来生じ
ていた段差の発生を極力抑止することができるので、半
導体基板表面の平坦性が損なわれることを極力抑止し、
かつセルフアラインでツインウエルを形成することが可
能となる。
Therefore, when the selective oxide film (27) is formed, the semiconductor substrate (2
1) is prevented from being oxidized, and the selective oxide film (21)
Since it is possible to suppress as much as possible the generation of a step that has conventionally occurred when the semiconductor substrate (21) is embedded in the semiconductor substrate (21), it is possible to prevent the flatness of the semiconductor substrate surface from being impaired as much as possible.
In addition, twin wells can be formed by self-alignment.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の第1の実施例に係る半導体装置の製造
方法を説明する第1の断面図である。
FIG. 1 is a first sectional view illustrating a method for manufacturing a semiconductor device according to a first embodiment of the present invention.

【図2】本発明の第1の実施例に係る半導体装置の製造
方法を説明する第2の断面図である。
FIG. 2 is a second sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment of the invention.

【図3】本発明の第1の実施例に係る半導体装置の製造
方法を説明する第3の断面図である。
FIG. 3 is a third sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment of the invention.

【図4】本発明の第1の実施例に係る半導体装置の製造
方法を説明する第4の断面図である。
FIG. 4 is a fourth sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment of the invention.

【図5】本発明の第1の実施例に係る半導体装置の製造
方法を説明する第5の断面図である。
FIG. 5 is a fifth sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment of the invention.

【図6】本発明の第2の実施例に係る半導体装置の製造
方法を説明する第1の断面図である。
FIG. 6 is a first cross-sectional view illustrating the method for manufacturing the semiconductor device according to the second embodiment of the invention.

【図7】本発明の第2の実施例に係る半導体装置の製造
方法を説明する第2の断面図である。
FIG. 7 is a second sectional view illustrating the method for manufacturing the semiconductor device according to the second embodiment of the invention.

【図8】本発明の第2の実施例に係る半導体装置の製造
方法を説明する第3の断面図である。
FIG. 8 is a third cross-sectional view illustrating the method for manufacturing the semiconductor device according to the second embodiment of the invention.

【図9】本発明の第2の実施例に係る半導体装置の製造
方法を説明する第4の断面図である。
FIG. 9 is a fourth sectional view illustrating the method for manufacturing the semiconductor device according to the second embodiment of the invention.

【図10】本発明の第2の実施例に係る半導体装置の製
造方法を説明する第5の断面図である。
FIG. 10 is a fifth sectional view illustrating the method for manufacturing the semiconductor device according to the second embodiment of the invention.

【図11】従来例に係る半導体装置の製造方法を説明す
る第1の断面図である。
FIG. 11 is a first cross-sectional view illustrating the method for manufacturing the semiconductor device according to the conventional example.

【図12】従来例に係る半導体装置の製造方法を説明す
る第2の断面図である。
FIG. 12 is a second cross-sectional view illustrating the method for manufacturing the semiconductor device according to the conventional example.

【図13】従来例に係る半導体装置の製造方法を説明す
る第3の断面図である。
FIG. 13 is a third cross-sectional view illustrating the method for manufacturing the semiconductor device according to the conventional example.

【図14】従来例に係る半導体装置の製造方法を説明す
る第4の断面図である。
FIG. 14 is a fourth cross-sectional view illustrating the method for manufacturing the semiconductor device according to the conventional example.

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 FI 技術表示箇所 H01L 21/316 21/336 9274−4M H01L 21/94 A 29/78 301 P ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification number Office reference number FI technical display location H01L 21/316 21/336 9274-4M H01L 21/94 A 29/78 301 P

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 半導体基板(11)上に酸化膜(1
2)、第1の窒化膜(13)、ポリシリコン層(14)
及び第2の窒化膜(15)を順次形成する工程と、 前記第2の窒化膜(15)上にレジスト膜(16)を選
択形成し、該レジスト膜(16)をマスクにして、前記
第2の窒化膜(15)をエッチング・除去する工程と、 前記レジスト膜(16)及び前記第2の窒化膜(15)
をマスクにして一導電型の不純物を注入し、前記半導体
基板(11)の表層に一導電型不純物領域層(17)を
形成する工程と、 前記第2の窒化膜(15)をマスクにして前記ポリシリ
コン層(14)を選択酸化して前記一導電型不純物領域
層(17)上に選択酸化膜(18)を形成する工程と、 前記第2の窒化膜(15)を除去し、前記選択酸化膜
(18)をマスクにして逆導電型の不純物を注入し、前
記半導体基板(11)の表層に逆導電型不純物領域層
(19)を形成する工程とを有することを特徴とする半
導体装置の製造方法。
1. An oxide film (1) is formed on a semiconductor substrate (11).
2), first nitride film (13), polysilicon layer (14)
And a step of sequentially forming the second nitride film (15), a resist film (16) is selectively formed on the second nitride film (15), and the resist film (16) is used as a mask to form the first film. Etching and removing the second nitride film (15), and the resist film (16) and the second nitride film (15)
Is used as a mask to implant an impurity of one conductivity type to form a one conductivity type impurity region layer (17) on the surface layer of the semiconductor substrate (11); and using the second nitride film (15) as a mask. Selectively oxidizing the polysilicon layer (14) to form a selective oxide film (18) on the one conductivity type impurity region layer (17); removing the second nitride film (15); A step of implanting an impurity of opposite conductivity type using the selective oxide film (18) as a mask to form an impurity region layer (19) of opposite conductivity type on the surface layer of the semiconductor substrate (11). Device manufacturing method.
【請求項2】 半導体基板(21)上に酸化膜(2
2)、ポリシリコン層(23)及び窒化膜(24)を順
次形成する工程と、 前記窒化膜(24)上にレジスト膜(25)を選択形成
し、該レジスト膜(25)をマスクにして、窒化膜(2
4)をエッチング・除去する工程と、 前記レジスト膜(25)及び前記窒化膜(24)をマス
クにして一導電型の不純物を注入し、前記半導体基板
(21)の表層に一導電型不純物領域層(26)を形成
する工程と、 前記窒化膜(24)をマスクにし、前記半導体基板(2
1)が酸化されない程度に前記ポリシリコン層(23)
を選択酸化して前記一導電型不純物領域層(26)上に
選択酸化膜(27)を形成する工程と、 前記窒化膜(24)を除去し、前記選択酸化膜(27)
をマスクにして逆導電型の不純物を注入し、前記半導体
基板(21)の表層に逆導電型不純物領域層(28)を
形成する工程とを有することを特徴とする半導体装置の
製造方法。
2. An oxide film (2) is formed on a semiconductor substrate (21).
2), a step of sequentially forming a polysilicon layer (23) and a nitride film (24), and a resist film (25) is selectively formed on the nitride film (24) and the resist film (25) is used as a mask. , Nitride film (2
4) Etching / removing, and using the resist film (25) and the nitride film (24) as a mask, implanting an impurity of one conductivity type to form an impurity region of one conductivity type in a surface layer of the semiconductor substrate (21). Forming a layer (26), and using the nitride film (24) as a mask, the semiconductor substrate (2)
Polysilicon layer (23) to the extent that 1) is not oxidized
Selectively oxidizing the first conductive type impurity region layer (26) to form a selective oxide film (27), and removing the nitride film (24) to remove the selective oxide film (27).
Is used as a mask to implant an impurity of opposite conductivity type to form an impurity region layer of opposite conductivity type (28) on the surface layer of the semiconductor substrate (21).
JP11847294A 1994-05-31 1994-05-31 Manufacture of semiconductor device Pending JPH07326745A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11847294A JPH07326745A (en) 1994-05-31 1994-05-31 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11847294A JPH07326745A (en) 1994-05-31 1994-05-31 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH07326745A true JPH07326745A (en) 1995-12-12

Family

ID=14737526

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11847294A Pending JPH07326745A (en) 1994-05-31 1994-05-31 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH07326745A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0889518A1 (en) * 1997-06-30 1999-01-07 Harris Corporation Method for forming complementary wells and self-aligned trench with a single mask

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0889518A1 (en) * 1997-06-30 1999-01-07 Harris Corporation Method for forming complementary wells and self-aligned trench with a single mask

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