JPH0870039A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE: To reduce the number of processes and to stabilize process by performing dry etching of a buried oxide film once with a resist pattern as a mask and then polishing away the remaining unneeded buried oxide film. CONSTITUTION: A first resist pattern 7 and a second resist pattern 7a are formed so that they cover the buried oxide film at the upper portion of a first silicon groove 5 and the buried oxide film at the upper portion of a second silicon groove 5a. Then, with the resist patterns 7 and 7a as masks, a buried oxide film 6 is etched. Then, the resist patterns 7 and 7a are eliminated. After this, a protruding part 6a of the buried oxide film at the first silicon groove 5 and the second silicon groove 5a or other remaining buried oxide films are polished away by CMP, thus flatly forming a buried insulator 8 at the first silicon groove 5, the second silicon groove 5a for burial.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a trench type element isolation.

[0002]

2. Description of the Related Art A semiconductor integrated circuit formed on a semiconductor substrate, particularly a silicon semiconductor substrate, has been densified or highly integrated, and an integrated circuit such as SRAM has a product level of 1 megabit to 4 megabits. The degree of integration is increasing beyond that. Furthermore, this SRAM
Therefore, there is a strong demand for higher speed circuit operation and lower power consumption.

In large-scale integrated circuits including not only SRAMs but also DRAMs, many elements must be formed on one chip, while it is necessary to reduce the chip size as much as possible from the viewpoint of product cost or yield. is there. here,
The reduction in chip size depends on how small the memory cell is. In particular, in the reduction of the SRAM memory cell that has a complicated memory cell structure and requires fine processing,
The development of a method for reducing an element isolation region for isolating elements in a memory cell has become the most important.

Conventionally, in the method of forming the element isolation region, the LO
The COS method or modified LOCOS method has been well known and used. However, this method has become difficult to apply to a semiconductor device having an element isolation region or an element formation region having a width of 0.3 μm.

Therefore, the LOCOS method or modified LOCOS
As an element isolation method replacing the method, various trench element isolation methods have been proposed in which a trench is formed on the surface of a semiconductor substrate and an insulator is embedded in the trench. Incidentally, here, it is required to simultaneously bury the insulator in the wide-width trench and the narrow-width trench.

Regarding a method of burying an insulating material in this trench, an IEDM Technical Digest, 1
986, pp. 61-64, which is a process of combining RIE (reactive ion etching) and CMP (chemical mechanical polishing) of an insulator, which is an effective method for planarizing an element isolation insulating film. Proposed.

5A to 5C are sectional views showing a method of manufacturing the trench element isolation shown in the above-mentioned paper in the order of steps. Figure 5
As shown in (a), a silicon oxide film 102 and a silicon nitride film 103 are laminated on a silicon substrate 101 to be formed in a predetermined region, and a wide silicon groove 104 or a narrow silicon groove 104a is provided, and then a buried oxide film is formed. 105 is deposited on the surface of the silicon substrate.

Next, as shown in FIG. 5B, the buried oxide film 1 covering the wide trench groove 104 region.
The block resist 106 is selectively formed only on 05. After this, the flattening resist 107 is applied.

Next, the above-mentioned flattening resist 107 is etched back by RIE, and subsequently the buried oxide film 105 is etched back. In this way, FIG.
As shown in FIG. 5, the buried oxide film 105 remains in the wide silicon trench 104. This is because the block resist 106 or the residual resist 107a described above serves as a mask,
This is because the underlying buried oxide film 105 is protected from etchback. After this etch back process, oxide film projections 109 are formed so as to surround the remaining resist 107a. Furthermore, a local depression 108a is also formed. The local depression 108a is formed by the block resist 1 described above.
The resist dents 108 generated by misalignment when forming 06 are transferred to the buried oxide film 105.

Next, as shown in FIG. 5 (d), after removing the block resist 106 and the residual resist 107a, CMP is performed to remove unnecessary oxides such as the oxide film projections 109, and wide silicon grooves 104 and Narrow silicon groove 10
Buried insulator 110 is formed together with 4a.

[0011]

This element isolation formation method has a small dimensional conversion difference of the element isolation pattern, reduces the step between the element formation region and the element isolation region, and is extremely effective for forming fine element isolation. Is. However, it is difficult to secure the flatness in the steps before the CMP flattening step, because the resist dents 108 at the edge of the block resist are likely to occur or the global flatness of the flattening resist 107 is easily damaged. In addition, the flattening resist 107 and the buried oxide film 105
It is difficult to control the amount of etch back by RIE. For this reason, this manufacturing method has a problem that the margin of the process becomes very narrow.

Further, the above-mentioned local depression 108a may occur due to the positional deviation of the block resist 106, and a recess may be formed in the buried insulator 110. Therefore, this manufacturing method also has a problem that the process is unstable.

An object of the present invention is to solve the above-mentioned problems and to provide a method of manufacturing a trench element isolation with a wide process margin and a stable process by reducing the number of steps.

[0014]

To this end, the present invention provides a step of forming a laminated thin film on a predetermined region of a main surface of a semiconductor substrate, and a step of forming a recess on the main surface of a semiconductor substrate on which the laminated thin film is not formed. A step of forming, a step of forming a buried insulating film by covering the laminated thin film and the concave portion, a step of selectively forming a resist pattern in the concave portion, and an embedding on the laminated thin film using the resist pattern as an etching mask. Including the step of dry etching the insulating film and the step of chemically mechanically polishing the embedded insulating film remaining in the recess using the thin film as a protective film for chemical mechanical polishing, the embedded insulation only in the recess of the main surface of the semiconductor substrate. Embed the membrane.

Preferably, after forming the recess, the semiconductor substrate is thermally oxidized to previously form a thin insulating film on the sidewall of the recess, and then the insulating film is formed.

Here, a laminated film of silicon nitride film / silicon oxide film or polysilicon film / silicon oxide film is used as the laminated thin film.

Alternatively, the laminated thin film is composed of a gate isolation film formed on the main surface of the semiconductor substrate and a gate electrode film formed thereon.

[0018]

The present invention will be described below with reference to the drawings. 1 and 2 are sectional views showing a method of forming an element isolation of a first embodiment of the present invention in the order of steps. Hereinafter, an example of forming an isolation region of an n-channel type element using a semiconductor substrate having a p-type conductivity type will be described, but it should be noted that the same applies to the case of the p-channel type. In this case, the p-type may be replaced with the n-type.

As shown in FIG. 1A, the specific resistance is 1 to 4
A first silicon oxide film 2, a silicon nitride film 3, and a second silicon oxide film 4 are laminated on a silicon substrate 1 of Ω-cm and a conductivity type of p type to form a predetermined region. Here, the film thickness of the first silicon oxide film 2 is 5 to 50 nm, and the silicon nitride film 3 is
Is set to 50 to 200 nm, and the thickness of the second silicon oxide film 4 is set to 100 to 300 nm.

Next, as shown in FIG. 1B, the surface of the silicon substrate 1 is dry-etched using the second silicon oxide film 4 as a mask. Here, a mixed gas of Cl ₂ , O ₂ and HBr is used as a reaction gas for this dry etching. In this way, the first silicon groove 5, the second silicon groove 5a, and the third silicon groove 5b are formed. Here, the depth of these silicon grooves is set to 0.5 μm to 1 μm. A wide element isolation region, a medium width element isolation region, and a narrow element isolation region are formed in these silicon trenches, respectively.

In this embodiment, the step of forming the above-mentioned silicon groove by using the second silicon oxide film 4 as a mask is explained. However, a known photoresist is used as a mask for dry etching of the silicon substrate. Good.
In this case, the second silicon oxide film 4 becomes unnecessary.

Next, as shown in FIG. 1C, a buried oxide film 6 is formed. The thickness of the buried oxide film 6 is set to be approximately the same as the depth of the silicon trench. In order to reduce the interface state of the side wall of the silicon groove, the first silicon groove 5, the second silicon groove 5a and the third silicon groove 5 are formed.
The surface of b may be thermally oxidized by about 2 to 10 nm to form a thermal oxide film in advance. In this case, buried oxide film 6 is formed so as to cover this thermal oxide film.

Next, as shown in FIG. 1D, the first resist pattern 7 and the second resist pattern 7a are respectively a buried oxide film above the first silicon groove 5 and a buried oxide film above the second silicon groove 5a. Is formed so as to cover. Here, since the buried oxide film 6 is completely buried in the silicon trench 5b, such a resist pattern is unnecessary. The resist patterns 7 and 7a described above are formed by using a mask for reversing the silicon groove pattern.
Further, the pattern size may be increased by 0.2 to 0.5 μm in consideration of misalignment in the step of forming the resist pattern.

Next, as shown in FIG. 2A, the first resist pattern 7 and the second resist pattern 7a are formed.
Is used as an etching mask for RIE to etch the buried oxide film 6. Here, the reaction gas for dry etching by RIE is a mixed gas of C ₄ F ₈ and CO.
The silicon nitride film 3 has a role as a stopper in this dry etching.

Next, the first resist pattern 7 and the second resist pattern 7a are removed. After this, the convex portions 6a of the buried oxide film in the regions of the first silicon trench 5 and the second silicon trench 5a or other remaining buried oxide film are polished and removed by CMP. This CMP method is the same as the polishing method for a semiconductor substrate such as a silicon substrate. However, in this case, as is well known, an abrasive containing silicon particles is used. Here, the silicon nitride film 3 has a role of an etching stopper for CMP,
When MP reaches the silicon nitride film 3, the progress of CMP is stopped. In this way, as shown in FIG. 2B, the embedded insulator 8 is flatly formed and embedded in the first silicon groove 5, the second silicon groove 5a, and the third silicon groove 5b.

After this, the silicon nitride film 3 and the silicon oxide film 2 are sequentially removed to form a gate insulating film 9 as shown in FIG. 2 (c). After that, a gate electrode and the like are formed to form a MOS transistor.

In this embodiment, the case where a silicon nitride film is used as an etching stopper for CMP has been described. It should be noted that a polysilicon film has the same effect as a stopper for this etching.

According to the present invention, the insulator can be uniformly buried in the wide silicon groove or the narrow silicon groove. Then, the step between the element formation region and the element isolation region is
It becomes 50 nm or less.

Next, the present invention will be described with reference to the second embodiment.
3 and 4 are sectional views showing a second embodiment of the present invention in the order of steps. As shown in FIG. 3A, a gate insulating film 12, a gate electrode 13, a silicon nitride film 14, and a silicon oxide film 15 of a MOS transistor are formed on a p-type silicon substrate 11 by laminating them. Here, the gate insulating film 12
Is formed of a silicon oxide film having a film thickness of about 10 nm, and the gate electrode 13 is formed of polysilicon containing phosphorus and having a film thickness of about 50 nm. The thickness of the silicon nitride film 14 is 20 to 50 nm, and the thickness of the silicon oxide film 15 is 100 to 50 nm.
It is set to 300 nm.

Next, as shown in FIG. 3B, the silicon oxide film 15 is used as a mask to dry-etch the silicon substrate 11. This step is performed in the same way as described in the first embodiment. Thus, the first silicon groove 16, the second silicon groove 16a, and the third silicon groove 16b are formed in the same manner as in the first embodiment. Here, the depth of these grooves is about 0.5 μm. Then, a wide element isolation region, a medium width element isolation region, and a narrow element isolation region are formed in these silicon trench regions, respectively.

Next, as shown in FIG. 3C, a buried oxide film 17 is formed. In this case, the buried oxide film thickness is set to 1.2 times or more the depth of the silicon trench.
Further, in order to reduce the interface state of the side wall of the silicon groove,
Forming a thermal oxide film in this region in advance is the same as that described in the first embodiment.

Next, as shown in FIG. 3D, a first resist pattern 18 and a second resist pattern 18a are formed on the buried oxide film of the first silicon trench 16 and the buried oxide film of the second silicon trench 16a, respectively. Form. here,
It is not necessary to form such a resist pattern on the silicon groove 16b. As in the first embodiment, the buried oxide film 17 is formed in the silicon trench 16b.
Because it is completely buried.

Next, as shown in FIG. 4A, the first resist pattern 18 and the second resist pattern 1 are formed.
The buried oxide film 17 is dry-etched using 8a as an etching mask for RIE. Here, by the dry etching by the RIE, a buried oxide film having a film thickness of about 100 nm is left on the silicon nitride film 14 and the residual oxide film 19 is left.
To form.

Next, the first resist pattern 18 and the second
The resist pattern 18a is removed. Subsequently, the convex portion 17a of the buried oxide film and the residual oxide film 19 are polished and removed by CMP. Here, the silicon nitride film 14 is the CM
It has a role of a P etching stopper. In this way, as shown in FIG. 4B, the embedded insulator 20 is flatly formed and embedded in the first silicon groove 16, the second silicon groove 16a, and the third silicon groove 16b.

Next, as shown in FIG. 4C, the silicon nitride film 14 is removed. In this way, the silicon substrate 1
The gate insulating film 12 and the gate electrode 13 of the MOS transistor are formed on the surface of the MOS transistor 1, and an element isolation region in which a buried insulator 20 is formed is formed in a silicon groove for electrically insulating and isolating these semiconductor elements. In this case, for wiring the gate electrode, for example, tungsten silicide is deposited on the gate electrode 13 and further patterned.

In this embodiment, the gate insulating film and the gate electrode of the MOS transistor are formed in advance, and the element isolation region is formed so as to be self-aligned with the gate insulating film or the gate electrode. Therefore, the process is further simplified and the process margin is increased as compared with the case of the first embodiment.

[0037]

As described above, according to the present invention, in order to form the element isolation regions having various widths in the semiconductor device, after the buried oxide film is deposited in the silicon trench having the width corresponding to this width. A resist pattern is provided on the buried oxide film in the wide silicon trench. The buried oxide film is once dry-etched using this resist pattern as a mask, and the remaining unnecessary buried oxide film is polished and removed by CMP.

Thus, it becomes easy to uniformly bury the buried insulator in both the wide silicon trench and the narrow silicon trench. Then, the step difference between the element formation region and the element isolation region can be set to 50 nm or less.

Further, since a process which is difficult to control, such as the conventional resist etch back, is not used, the process margin is increased, and it is possible to form the element isolation region with high reproducibility and stable process.

[Brief description of drawings]

FIG. 1 is a cross-sectional view illustrating a first embodiment of the present invention in process order.

FIG. 2 is a cross-sectional view illustrating the first embodiment of the present invention in process order.

FIG. 3 is a sectional view illustrating a second embodiment of the present invention in process order.

FIG. 4 is a sectional view illustrating a second embodiment of the present invention in process order.

FIG. 5 is a cross-sectional view showing a conventional manufacturing method in the order of steps.

[Explanation of symbols]

 1, 11, 101 Silicon substrate 2 First silicon oxide film 3, 14, 103 Silicon nitride film 4 Second silicon oxide film 5, 16 First silicon groove 5a, 16a Second silicon groove 5b, 16b Third silicon groove 6, 17,105 Buried oxide film 6a, 17a Convex portion of buried oxide film 7,18 First resist pattern 7a, 18a Second resist pattern 8,20,110 Buried insulator 9,12 Gate insulating film 13 Gate electrode 15 Silicon oxide film 19 Residual oxide film 104 Wide silicon groove 104a Narrow silicon groove 106 Block resist 107 Flattening resist 107a Residual resist 108 Resist dent 108a Local dent 109 109 Oxide film protrusion

Claims (5)

[Claims] 1. A step of selectively forming a laminated thin film on a main surface of a semiconductor substrate, a step of forming a concave portion on the main surface of the semiconductor substrate on which the laminated thin film is not formed, and a step of forming the laminated thin film and the concave portion. A step of forming a buried insulating film to cover, a step of selectively forming a resist pattern on the buried insulating film in the recess, a step of dry etching the buried insulating film on the laminated thin film, and a step of forming the laminated thin film. And a step of chemically mechanically polishing the insulating film embedded in the recess as a protective film for chemical mechanical polishing. 2. The buried insulating film is formed after the recess is formed, the semiconductor substrate is thermally oxidized to form a thin insulating film on a sidewall of the recess in advance, and then the buried insulating film is formed. Of manufacturing a semiconductor device of. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the laminated thin film is composed of a silicon nitride film / silicon oxide film. 4. The method of manufacturing a semiconductor device according to claim 1, wherein the laminated thin film is composed of a polysilicon film / silicon oxide film. 5. The semiconductor according to claim 1, wherein the laminated thin film is composed of a gate insulating film formed on the main surface of the semiconductor substrate and a gate electrode film covering the gate insulating film. Device manufacturing method.