JP4955880B2 - Method for fabricating an integrated circuit forming a trench in a substrate - Google Patents

Description

[0001]
【Technical field】
The present invention relates generally to integrated circuits having increased gate coupling capacitance. The invention further relates to an integrated circuit having a conductive layer optimized for gate coupling capacitance.
[0002]
[Background]
The invention is particularly applicable to the fabrication of non-volatile memory integrated circuits (eg, flash, EPROM, EEPROM, etc.), but may be applied to other integrated circuits. Nonvolatile memory integrated circuits are used in a wide range of commercial and military electronic devices, including handheld phones, radios, and digital cameras. There continues to be a demand for lower voltages, lower power consumption, and smaller chip sizes in the market for these electronic devices. Also, the design rules are becoming lower due to the demand for higher functionality, from today's 0.35-0.25 micron technology to 0.18 microns, 0.15 microns and even lower.
[0003]
A conventional flash memory cell of a flash memory IC is shown in FIGS. FIG. 1 shows a cross-sectional view along the bit line direction of a single flash memory cell 10 on a substrate 11. The cell 10 includes a first transistor 12 and a second transistor 14. Each of the transistors 12 and 14 includes a tunnel oxide layer 16, a first polysilicon layer 18, 20, an interpoly dielectric layer 22, 24, a second polysilicon layer 26, 28, a silicide layer 30, 32, And sidewall spacers 34,36.
[0004]
Referring first to FIGS. 2-7, a conventional flash memory cell fabrication process is shown. The substrate 11 is shown in FIGS. 2 to 7 in a cross-sectional view along the word line direction. The substrate 11 includes a shallow trench isolation structure (STI) 40 between elements (not shown) such as metal oxide semiconductor field effect transistors (MOSFETs), memory cells, or other elements. STI 40 includes an oxide fill material 42. A tunnel oxide layer 16 is provided on the substrate 11. A first polysilicon wing 46 and a second polysilicon wing 48 are patterned in the first polysilicon layer 20. An interpoly dielectric layer 24 is provided over the polysilicon wings 46, 48 and the STI 40. A second polysilicon layer 28 and a silicide layer 32 are provided on the interpoly dielectric layer 24.
[0005]
Referring to FIG. 3, STI 40 is formed by first applying pad oxide layer 50 on substrate 11 and then growing or depositing nitride layer 52. STI masking and etching steps form STI depressions 54. Referring to FIG. 4, an STI liner oxide 56 is provided to provide a liner for the recess 54, followed by a PECVD (plasma enhanced chemical vapor deposition) oxide fill material 58 to fill the trench. As shown in FIG. 5, a planarization and trench CMP (Chemical Mechanical Polishing) step is applied to the PECVD oxide fill material 58 to provide a top of the nitride layer 52 and the sides 60, 62 of the nitride layer 52. To remove the oxide with the part along the part.
[0006]
Referring to FIG. 6, a nitride strip step removes nitride layer 52. The pad oxide layer 50 is removed by sacrificial oxidation. Thereafter, a tunnel oxide layer 62 is grown on the substrate 11. Referring to FIG. 7, the first polysilicon layer 20 is applied. Layer 20 is patterned (ie, masked and etched) to form wings 46,48. Referring again to FIG. 2, an interpoly dielectric layer 24 (eg, oxide nitride oxide) is grown on the wings 46,48. Next, a second polysilicon layer 28 is deposited followed by a silicide layer 32.
[0007]
In operation, data elements are stored in polysilicon layers 18, 20 (FIG. 1), also called floating gates. Access to data elements is obtained through second polysilicon layers 26, 28, also called control gates or word lines. The voltage of the data element is typically on the order of 3.3 volts, but the voltage that must be applied to the control gate to access this data element is on the order of 9 volts. Therefore, by placing a charge pump (not shown) on the flash memory IC, the chip voltage is increased from 3.3 volts to a target voltage of 9 volts.
[0008]
The charge pump is large and takes up substantial space on the flash memory cell and further impairs the reliability of the IC. As design rules continue to shrink, the size of the charge pump becomes an obstacle in chip design. However, by reducing the target voltage, the size of the charge pump can be reduced. The target voltage is decreased by increasing the gate coupling ratio (α) of the memory cell. The gate coupling ratio (α) is determined as follows.
α = C _ono / (C _ono + C _tox )
_Where C _ono is the capacitance between the first polysilicon layer 18, 20 and the second polysilicon layer 26, 28, and C _tox is between the substrate 11 and the first polysilicon layer 26, 28. Capacitance between.
[0009]
Therefore, what is needed is an IC that increases the gate coupling ratio, reduces the target voltage of the charge pump, reduces the power consumption of the IC, reduces the size of the charge pump, and further improves reliability, And a method for manufacturing an IC.
[0010]
DISCLOSURE OF THE INVENTION
These and other limitations of the prior art are addressed by the present invention for integrated circuits having increased gate coupling capacitance. The integrated circuit includes a substrate having a surface, the substrate having a trench extending below the surface. A trench fill material is disposed within the trench and extends partially over the surface. A first conductive layer is adjacent to the trench fill material and a portion extends over a portion of the insulating material. An insulating layer is adjacent to the first conductive layer, and a second conductive layer is adjacent to the insulating layer.
[0011]
In accordance with another embodiment of the present invention, an integrated circuit having increased gate coupling capacitance is disclosed. The method for fabricating an integrated circuit is:
Forming a trench in the substrate, the trench extending below a surface of the substrate, the method further comprising:
Providing the trench fill material in the trench such that the trench fill material extends over the surface of the substrate;
Providing a first conductive layer on at least a portion of the trench fill material.
[0012]
The invention will be more fully understood when the following detailed description is read in conjunction with the accompanying drawings, in which like reference numerals refer to like parts.
[0013]
BEST MODE FOR CARRYING OUT THE INVENTION
As mentioned above, it is necessary to increase the gate coupling ratio in order to reduce the target voltage of the charge pump and thus reduce the size of the charge pump. The present invention increases the capacitance across an interpoly dielectric layer between a first polysilicon layer and a second polysilicon layer (also referred to as “poly 1” and “poly 2”, respectively). , Increase the gate coupling ratio. As shown, this increase is obtained by increasing the surface area of contact between poly 1 and poly 2 and increasing the surface area of the capacitor formed by poly 1, poly 2 and the interpoly dielectric layer.
[0014]
Referring to FIG. 8, a portion 100 of an integrated circuit (IC) having an improved gate coupling ratio according to one embodiment of the present invention is shown in cross-sectional view along the word line direction. The IC is a flash memory device, but may alternatively be another non-volatile memory (eg, EPROM, EEPROM, etc.) or other integrated circuit. A semiconductor substrate 102 (eg, silicon, germanium, gallium arsenide, etc.) includes an isolation structure 104 defined in a recess or trench 106. In this embodiment, isolation structure 104 is a shallow trench isolation structure that includes trench fill material 108. The trench filling material 108 is an insulating material such as PECVD oxide. The trench fill material 108 extends from the bottom of the recess 106 to the upper surface 110 of the substrate 102 and includes a portion 109 extending on the upper surface 110. The recess 106 has a bottom surface 105 of about 1000 to 7000 angstroms (Å) from below the top surface 110, which is preferably about 4000 inches from below the top surface 110.
[0015]
A first insulating layer 111 such as a tunnel oxide layer is provided on the upper surface 110 of the substrate 102 and the sidewalls 112 and 114 of the recess 106. A first conductive layer 116 such as doped polysilicon is provided adjacent to the first insulating layer 111 and the trench filling material 108. The first conductive layer 116 is masked and etched to form a first conductive wing or portion 118 and a second conductive wing or portion 120. The first conductive layer 116 also defines a via 140 between the conductive portions 118 and 120. The first conductive portion 118 and the second conductive portion 120 extend at least partially over the portion 109 of the trench fill material, increasing the surface area that the conductive layer 116 exposes to subsequent layers as compared to the prior art. . This increase in surface area results in an increase in capacitance and increases the gate coupling ratio as described above. In this exemplary embodiment, the top surface 134 of the trench fill material 108 is at least 100 inches from the top of the top surface 110 of the substrate 102. The top surface 134 may be as high as 5000 inches from the top surface 110 of the substrate 102, and probably about 1000 to 2000 inches from the top surface 110 of the substrate 102.
[0016]
A second insulating layer 122 such as an interlayer dielectric layer (eg, oxide nitride oxide) is provided over the first conductive layer 116 and the trench fill material 108. Insulating layer 122 forms a conductive barrier between conductive portions 118 and 120. A second conductive layer 124 such as doped polysilicon is provided over the second insulating layer 122. Thus, insulating layer 122 also insulates layers 116 and 124 from each other. A silicide layer 126 is provided over the second conductive layer 124.
[0017]
With reference to FIGS. 9-13, a method for fabricating portion 100 will be described. In FIG. 9, an isolation structure 104 is formed by providing an insulating layer 128 on the substrate 102 that includes an oxide material (eg, a pad oxide material such as SiO ₂ ). Layer 128 is grown by a conventional thermal process or applied by a chemical vapor deposition (CVD) or physical vapor deposition (PVD) process. Thereafter, a barrier layer 130, preferably a silicon nitride layer, such as Si ₃ N _4, is applied over the insulating layer 128 with a thickness of about 500 to 5000 mm, preferably about 1000 to 2000 mm. Aperture 129 is formed at the desired location in layers 128, 130 using a standard photolithography process. The recess 106 is then etched in the substrate 102 using a conventional trench etching process such as dry or plasma etching. A liner oxidation step forms an insulating liner (not shown) along the walls of the recess 106.
[0018]
The recess 106 is then filled with an insulating trench fill material 108, for example by a PECVD oxide step. The trench fill material 108 is deposited with a thickness less than that of the conventional trench fill material 58 (FIG. 4). Specifically, assuming that the trench depth from top surface 110 to bottom surface 105 is about 4000 mm, trench fill material 108 is deposited with a thickness less than about 7000 mm.
[0019]
Referring to FIG. 10, a mask layer 131 (eg, a photoresist layer) is applied over the trench fill material 108. The mask layer 131 is preferably applied to ensure that the lateral width of the opening 133 is somewhat wider than the lateral width of the barrier layer 130 and that subsequent etching completely removes the barrier layer 130.
[0020]
Referring to FIG. 11, the etching step removes the insulating layer 128, the barrier layer 130, and the portion 135 of the trench fill material 108. In this embodiment, trench fill material 108 is etched until upper surface 110 of substrate 102 is exposed. It can be seen that the portion 109 of the trench fill material 108 extends beyond the top surface 110. Note that in the prior art (FIG. 6) only the nitride layer 52 is etched off by selective etching.
[0021]
In FIG. 12, sacrificial oxidation and strip-off steps are performed to round corners 136,138. In sacrificial oxidation, a thin oxide layer is grown and stripped off to round the corners of the trench. This rounding prevents the “double hump effect” in the IV characteristic curve of the transistor. During this sacrificial oxidation, the level of trench fill material 108 may or may not be further reduced from the etch associated with FIG.
[0022]
In FIG. 13, the first insulating layer 111 is grown on the substrate 120 by heat or otherwise provided on the substrate 120 using a known vapor deposition process (eg, chemical vapor deposition, physical vapor deposition). In this embodiment, the first insulating layer 111 is a tunnel oxide layer (SiO ₂ ). Next, a first conductive layer 116 (“poly 1”) is deposited over the first insulating layer 111 and the trench fill material 108. Note that poly 1 layer 116 extends over portion 109 of trench fill material 108.
[0023]
Referring again to FIG. 8, the poly 1 layer 116 is masked and etched (ie, patterned) to form a via 140 between the first conductive portion or wing 118 and the second conductive portion or wing 120. . Next, a second insulating layer 112 (eg, ONO) is provided or grown adjacent to the first conductive layer 116. The second insulating layer 122 electrically insulates the first conductive portion 118 and the second conductive portion 120. Next, a second conductive layer 124 (eg, polysilicon) is deposited followed by a silicide layer 126.
[0024]
With reference to FIGS. 14-17, an alternative embodiment of the present invention is disclosed. In the second embodiment, the use of the mask layer 131 described in FIG. 10 of the first embodiment is omitted. Referring to FIG. 14, an isolation structure 204 is formed by providing an insulating layer 228 on the substrate 202 that includes an oxide material (eg, a pad oxide material such as SiO ₂ ). Layer 128 is provided on layer 128 as described in FIG. 9 above. Thereafter, a barrier layer 230, preferably a silicon nitride layer, such as Si ₃ N _4, is applied over the insulating layer 228 with a thickness somewhat greater than that of the layer 128. For example, the barrier layer 230 is between about 1000 angstroms and 5000 angstroms thick. Aperture 229 is formed at the desired location in layers 228, 230 using a standard photolithography process. The recess 206 is then etched in the substrate 202 using a conventional trench etching process such as dry or plasma etching. A liner oxidation step forms an insulating liner (not shown) along the walls of the recess 206.
[0025]
The recess 206 is then filled with an insulating trench fill material 208, for example by a PECVD oxide step. A trench fill material 208 is deposited over the recess 206 and the barrier layer 230 with a thickness less than that of the conventional trench fill material 58 (FIG. 4). Specifically, assuming that the trench depth from top surface 210 to bottom surface 205 is about 4000 mm, trench fill material 208 is deposited with a thickness less than about 7000 mm. Next, the trench fill material 208 is planarized (eg, by chemical mechanical planarization or CMP) until the top surface 237 of the material 208 is substantially flush with the top surface of the barrier layer 230. Thus, as will be appreciated, the barrier layer thickness 229 defines the extent to which the trench fill material 208 extends beyond the top surface 210 of the substrate 202.
[0026]
Referring to FIG. 15, the strip step removes the insulating layer 228 and the barrier layer 230, leaving the trench fill material 208. It can be seen that the portion 209 of the trench fill material 208 extends beyond the top surface 210. Also in FIG. 15, sacrificial oxidation and strip-off steps are performed to round corners 236, 238. During this sacrificial oxidation, the height and width of the trench fill material 208 may or may not be selectively reduced.
[0027]
In FIG. 16, the first insulating layer 211 is grown on the substrate 220 by heat or is otherwise provided on the substrate 220 using a known vapor deposition process (eg, chemical vapor deposition, physical vapor deposition). In this embodiment, the first insulating layer 211 is a tunnel oxide layer (SiO ₂ ). Next, a first conductive layer 216 (“poly 1”) is deposited over the first insulating layer 211 and the trench fill material 208. Note that the poly 1 layer 216 extends over the portion 209 of the trench fill material 208.
[0028]
Referring to FIG. 17, the poly 1 layer 216 is masked and etched (ie, patterned) to form a via 240 between the first conductive portion or wing 218 and the second conductive portion or wing 220. Next, a second insulating layer 222 (eg, ONO) is provided or grown adjacent to the first conductive layer 216. The second insulating layer 222 electrically insulates the first conductive portion 218 and the second conductive portion 220 from each other. Next, a second conductive layer (not shown) is deposited, and subsequently a silicide layer (not shown) is deposited in the same manner as in the first embodiment.
[0029]
Referring to FIGS. 18 to 23, a third embodiment of the present invention is shown. In this third embodiment, the trench fill material includes a first trench fill material provided in the first fabrication step and a second trench fill material in the second fabrication step. In FIG. 18, an isolation structure 304 is formed by providing an insulating layer 328 containing an oxide material (eg, a pad oxide material such as SiO ₂ ) on the substrate 302. Layer 328 is grown by a conventional thermal process or applied by chemical vapor deposition (CVD) or physical vapor deposition (PVD) processes. Thereafter, a barrier layer 330, preferably a nitride layer, such as Si ₃ N _4, is applied over the insulating layer 328 with a thickness of about 1000 to 7000 mm, typically 2000 to 4000 mm. Note that this thickness is somewhat thicker than that of the embodiment described in FIG. Aperture 329 is formed at a desired location in layers 328, 330 using a standard photolithography process. The recess 306 is then etched in the substrate 302 using a conventional trench etching process such as dry or plasma etching. A liner oxidation step forms an insulating liner (not shown) along the walls of the recess 306.
[0030]
The recess 306 is then filled with insulating trench fill material 308, for example by a PECVD oxide step. Trench fill material 308 is deposited with a thickness less than that of conventional trench fill material 58 (FIG. 4). Specifically, trench fill material 308 is deposited with a thickness of less than about 7000 mm. The trench fill material 308 is then planarized (eg, by chemical mechanical planarization or CMP) until the top surface 337 of the material 308 is substantially flush with the top surface of the barrier layer 330.
[0031]
Referring to FIG. 19, an etching step removes the insulating layer 328, the barrier layer 330, and the portion 335 of the trench fill material 308. In this example, trench fill material 308 is etched until upper surface 310 of substrate 302 is exposed.
[0032]
Referring to FIG. 20, an insulating layer 342 (eg, CVD oxide) is applied over the trench fill material 308 with a thickness of about 1000 to 5000 inches, typically 2000 to 4000 inches. The insulating layer 342 is then patterned (ie, masked and etched as described with respect to FIG. 10 above) to form a second trench fill material 346 (FIG. 21) over the trench fill material 308. It can be seen that the trench fill material 346 extends over the top surface 310.
[0033]
In FIG. 22, sacrificial oxidation and strip-off steps are performed to round corners 336, 338. During this sacrificial oxidation, the level of the second trench fill material 346 may or may not be further reduced from the stripping associated with FIG. The first insulating layer 311 is grown on the substrate 320 by heat or is otherwise provided on the substrate 320 using a known vapor deposition process (eg, chemical vapor deposition, physical vapor deposition). In this embodiment, the first insulating layer 311 is a tunnel oxide layer (SiO ₂ ). Next, a first conductive layer 316 (“poly 1”) is deposited over the first insulating layer 311 and the trench fill material 308. In this example, the first poly 1 layer 316 also extends over the second trench fill material 346.
[0034]
Referring to FIG. 23, the poly 1 layer 316 is masked and etched (ie, patterned) to form a via 340 between the first conductive portion or wing 318 and the second conductive portion or wing 320. Next, a second insulating layer 322 (eg, ONO) is provided or grown adjacent to the first conductive layer 316. The second insulating layer 322 electrically insulates the first conductive portion 318 and the second conductive portion 320 from each other. Next, a second conductive layer (not shown) is deposited, and subsequently a silicide layer (not shown) is deposited in the same manner as in the first embodiment.
[0035]
Although the embodiments illustrated and described above are presently preferred, it should be understood that these embodiments are provided as examples only. For example, the specific materials and dimensions used in the preferred embodiments disclosed herein are provided by way of example and are not meant to exclude the substitution of similar materials or dimensions. Also, although the disclosed embodiments are particularly suitable for flash EPROM or other non-volatile memory, they may be applied in non-memory devices. The invention is not limited to specific embodiments, but also applies to various modifications that fall within the scope of the appended claims.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view of a conventional flash memory cell along a bit line direction.
FIG. 2 is a cross-sectional view of the memory cell of FIG. 1 along the word line direction.
FIG. 3 is a diagram showing steps of a conventional flash memory cell manufacturing method of FIGS. 1 and 2;
FIG. 4 is a diagram showing steps of a conventional flash memory cell manufacturing method shown in FIGS. 1 and 2;
FIG. 5 is a diagram showing steps of a conventional flash memory cell manufacturing method shown in FIGS. 1 and 2;
6 is a diagram showing steps of a conventional flash memory cell manufacturing method shown in FIGS. 1 and 2. FIG.
FIG. 7 is a diagram showing steps of a conventional flash memory cell manufacturing method shown in FIGS. 1 and 2;
FIG. 8 illustrates a portion of an integrated circuit according to an exemplary embodiment of the present invention.
FIG. 9 is a diagram showing steps in a method for fabricating the integrated circuit portion of FIG. 8;
FIG. 10 is a diagram showing steps in a method of manufacturing a portion of the integrated circuit of FIG.
FIG. 11 is a diagram showing steps in a method for fabricating the integrated circuit portion of FIG. 8;
FIG. 12 is a diagram showing steps in a method of fabricating the integrated circuit portion of FIG. 8;
FIG. 13 is a diagram showing steps in a method of fabricating the integrated circuit portion of FIG. 8;
FIG. 14 shows the steps of a method for fabricating a part of an integrated circuit according to a second exemplary embodiment of the invention.
FIG. 15 is a diagram showing steps in a method of fabricating the integrated circuit portion of FIG. 14;
FIG. 16 is a diagram showing steps in a method of manufacturing a portion of the integrated circuit of FIG. 14;
FIG. 17 is a diagram showing steps in a method for fabricating the integrated circuit portion of FIG. 14;
FIG. 18 illustrates steps of a method of fabricating a portion of an integrated circuit according to a third exemplary embodiment of the present invention.
FIG. 19 is a diagram showing steps in a method of fabricating the integrated circuit portion of FIG. 18;
FIG. 20 is a diagram showing steps in a method of fabricating the integrated circuit portion of FIG. 18;
FIG. 21 is a diagram showing steps in a method of fabricating the integrated circuit portion of FIG. 18;
22 is a diagram showing steps in a method of fabricating the integrated circuit portion of FIG. 18;
FIG. 23 is a diagram showing steps in a method for fabricating the integrated circuit portion of FIG. 18;

Claims (1)

A method for fabricating an integrated circuit (100) that forms a trench (106) in a substrate (102), the trench (106) extending below a surface (110) of the substrate (102), the method comprising:
Providing the trench fill material (108) in the trench (106) such that the trench fill material (108) extends over the surface (110) of the substrate (102);
Providing a first conductive layer (116) on at least a portion of the trench fill material (108);
Providing the trench fill material (108) comprises providing a trench fill oxide (108) over the trench (106);
Applying a photoresist mask (131) over the trench (106);
Etching the trench fill oxide (108), the method further comprising:
Providing an insulating material (342) on the trench fill material (108);
Patterning an insulating material (342) to produce a second trench fill material (346) over the trench (106);
The first conductive layer (116) extends over at least a portion of the second trench fill material (346);
The photoresist mask (108) has a mask portion (131) on the trench (106) and an opening (133) on the surface (110) of the substrate, the method comprising:
Providing a barrier layer (130) on a substrate (102);
Forming an aperture (129) in the barrier layer (130), the barrier layer (130) having a lateral width between the apertures (129), and an opening (133) in the mask portion (131). the aperture (129) rather somewhat wider than the width of the barrier layer between each other (130), a barrier layer (130), by etching using a mask portion (131), characterized in that it is completely removed, Method.

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