JPH0758213A - Well forming method in semiconductor device - Google Patents

Abstract

PURPOSE:To eliminate the non-uniformity of impurity density of a well due to microscopic formation in the method of well formation in a semiconductor device. CONSTITUTION:First, an impurity layer 16, which is smaller than a well-forming region, is formed, impurities 16 are diffused by heat treatment and a well 17 is formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming wells in a semiconductor substrate (hereinafter simply referred to as a substrate) more uniformly in a semiconductor device. As is well known, when a combination of PMOS and NMOS is formed on the same substrate, if the substrate is p-type, an n-type impurity diffusion region is formed in a predetermined portion of the substrate, and the impurity diffusion region is called a well.

[0002]

2. Description of the Related Art A conventional method for forming a well described above is shown in FIG.
The process of the main part is shown in a sectional view, and will be described below.

First, the substrate shown in FIG.
A silicon dioxide film, a so-called oxide film 22, having a thickness of about 1000 Å is formed on the (type silicon substrate) 21 by a thermal oxidation method to obtain the shape of FIG.

Next, as shown in FIG. 3 (c), a resist is applied on the structure and a well-known photolithography (etching) etching technique is used to form an opening at a corresponding well formation region. Patterning is performed to form a resist pattern 25. Then, the resist pattern 25
Is used as a mask to implant impurities (n-type impurities in this example, for example, phosphorus) by an ion implantation technique (commonly called ion implantation), as shown in FIG. ) 23 can be done.

After that, the resist 25 is removed and N ₂ is removed.
When heat treatment is performed in an atmosphere at a temperature of 1150 ° C. for a processing time of about 300 minutes, the impurity layer 23 is diffused in the vertical and horizontal directions, and an impurity region, that is, a well 24 reaching the surface of the substrate 21 is formed. In FIG. 3, two wells having a large area (left side) and a small well (right side) are schematically shown.

[0006]

However, in the above-described method, when the size of the well is reduced as the semiconductor device is miniaturized in recent years, as shown in FIG. Since the impurity concentration tends to be high in the central portion of the pattern and low in the peripheral portion, the impurity concentration becomes non-uniform in the entire well. When the well is large (wide) (a in FIG. 4), it does not matter so much, but when the well is small (narrow in width), the above tendency is conspicuous and large as shown in FIG. When the well a and the small well b are mixed, a difference occurs in the peak concentration of the impurity concentration of both.

According to the present invention, in order to eliminate the above-mentioned problem of non-uniformity of well concentration due to miniaturization, when forming a well, first, a plurality of impurity layers having a pattern smaller than the well to be formed are formed, The purpose is to form a well with a more uniform concentration by diffusing it into one well by heat treatment.

[0008]

In order to achieve the above object, the present invention provides a method for forming a well by first removing impurities by using a resist pattern corresponding to an impurity layer smaller than the size of at least one of the smallest wells as a mask. It is formed by implantation, and is diffused by heat treatment (if diffused, a plurality of impurity layers are connected. Of course, the pattern is also formed in this way) to form one well.

[0009]

As described above, according to the present invention, a plurality of impurity layers that divide the well region are first formed, and the well layers are formed by diffusing the impurity layers by heat treatment. Injection is possible, and a well having a uniform impurity concentration can be formed.

[0010]

EXAMPLE FIG. 1 shows a well forming method according to an example of the present invention.
Similar to the conventional example, the process of the main part is shown in a sectional view, which will be described below.

First, an oxide film 12 is formed on a substrate 11 (a p-type silicon substrate in this embodiment as in the prior art) 11 shown in FIG. 1A as in the prior art to obtain the shape shown in FIG. 1B.

Next, a resist is applied thereon and patterned 13 as shown in FIG. 1C by a known photolithographic etching technique. The pattern 13 serves as a mask 15 for forming a plurality of impurity layers 16 to be the well within the width of the well (17 in FIG. 1D) to be finally formed by the impurity ion implantation method. The opening 14 is provided in the pattern. And the condition of the pattern 13 is
The impurity layer 1 formed of the resist pattern 13
6 are diffused in the heat treatment of the next step so that they are connected to each other to form one well 17. That is, when the distance between the openings 14 of the resist pattern 13 (width of the mask pattern 15) is L, the heat treatment time of the implanted impurities (16) is t, and the impurity diffusion coefficient at that time is D, L <√.
It is set to be Dt / 2. That is, the impurity layer 16
The diffusion length by the heat treatment of is √Dt, and if L is smaller than ½ of that (that is, the distance between the impurity layers 16), the impurity layers 16 are connected by diffusion as shown in FIG. Impurities (n-type impurities, such as phosphorus, are also implanted in the present embodiment as in the conventional example) by ion implantation using the resist pattern 13 as a mask (for example, phosphorus is implanted under the conditions of 150 keV and 2E13 cm ⁻² ). As shown in FIG. 1C, a plurality of impurity layers 16 are formed in an upper layer portion of the substrate 16 in one desired well region. Needless to say, this impurity layer 16 is the smallest well (see FIG. 1) when wells of different sizes are mixed.
In (d), the pattern is smaller than 17) on the right side.

After that, the resist 13 is removed, and N ₂
When heat treatment is performed in an atmosphere at a temperature of 1150 ° C. for a treatment time of about 300 minutes, the plurality of impurity layers 16 are vertically and horizontally diffused and connected to form a well 17 reaching the surface of the substrate 11.

When the well 17 is formed by the method described above, if the initial formation of the impurity layer 16 is made as small as possible, regardless of the size of the target well 17,
Since the impurity layers 16 having the same size and the same concentration can be formed and are diffused by the heat treatment to form one well 17, the wells 17 having different impurity concentrations are mixed. However, there is no difference in the density and it becomes uniform.

[0015]

As described above, according to the present invention, as a well forming method, a plurality of impurity layers each having a size smaller than the size of the well are first formed in one well forming region, and the impurity layers are diffused by heat treatment. Since the number of wells is one, the impurity implantation can be performed without depending on the size of the well, and a well having a uniform impurity concentration can be formed. Therefore, the non-uniformity of the impurity concentration in the well due to the miniaturization of the semiconductor device is eliminated, which greatly contributes to the improvement of the reliability of the device.

[Brief description of drawings]

FIG. 1 is a process sectional view of an embodiment of the present invention.

FIG. 2 is an explanatory diagram of well formation according to an embodiment of the present invention.

FIG. 3 is a process sectional view of a conventional example.

[Fig. 4] Illustration of problems

[Explanation of symbols]

 Reference Signs List 11 substrate 12 oxide film 13 resist pattern 14 resist pattern opening 15 resist pattern mask portion (mask width) 16 impurity layer 17 well

Claims (3)

[Claims] 1. A method for forming a well in a semiconductor substrate, which comprises first forming a plurality of impurity layers smaller than the size of the well to be formed within the well formation region, and then forming the plurality of impurity layers. A method for forming a well in a semiconductor device, characterized in that the well is formed by diffusion by heat treatment. 2. As a method of forming the plurality of impurity layers, a resist pattern having an opening corresponding to the plurality of impurity layer forming portions is formed on a semiconductor substrate, and the resist pattern is used as a mask to remove impurities. To form the plurality of impurity layers, and the resist pattern has a pattern in which one well forming region formed by the resist pattern has the opening portions which are adjacent to each other by heat treatment. The method for forming a well in a semiconductor device according to claim 1, wherein: 3. As a condition of the resist pattern, a distance (mask pattern width) L between the adjacent openings of the resist pattern is a heat treatment time of the impurities,
3. The method of forming a well in a semiconductor device according to claim 2, wherein when the impurity diffusion coefficient is D, L <√Dt / 2 is set.