KR850000037B1 - The method of mos with self alignment metal electroid - Google Patents
The method of mos with self alignment metal electroid Download PDFInfo
- Publication number
- KR850000037B1 KR850000037B1 KR8204596A KR820004596A KR850000037B1 KR 850000037 B1 KR850000037 B1 KR 850000037B1 KR 8204596 A KR8204596 A KR 8204596A KR 820004596 A KR820004596 A KR 820004596A KR 850000037 B1 KR850000037 B1 KR 850000037B1
- Authority
- KR
- South Korea
- Prior art keywords
- oxide film
- silicon nitride
- film
- silicon
- nitride film
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 17
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 13
- 239000002184 metal Substances 0.000 title claims abstract description 13
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 20
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 20
- 238000009792 diffusion process Methods 0.000 claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 10
- 229910052796 boron Inorganic materials 0.000 claims abstract description 7
- -1 boron ions Chemical class 0.000 claims abstract description 7
- 239000012535 impurity Substances 0.000 claims abstract description 7
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 8
- 229910052710 silicon Inorganic materials 0.000 claims description 8
- 239000010703 silicon Substances 0.000 claims description 8
- 239000012298 atmosphere Substances 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 4
- 229910052698 phosphorus Inorganic materials 0.000 claims description 4
- 239000011574 phosphorus Substances 0.000 claims description 4
- 239000002131 composite material Substances 0.000 claims description 2
- 238000005468 ion implantation Methods 0.000 description 11
- 229920002120 photoresistant polymer Polymers 0.000 description 10
- 230000003647 oxidation Effects 0.000 description 9
- 238000007254 oxidation reaction Methods 0.000 description 9
- 229910052782 aluminium Inorganic materials 0.000 description 7
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 7
- 238000004519 manufacturing process Methods 0.000 description 7
- 238000000206 photolithography Methods 0.000 description 6
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- 230000001133 acceleration Effects 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 239000012299 nitrogen atmosphere Substances 0.000 description 2
- 230000007261 regionalization Effects 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 1
- 229910052582 BN Inorganic materials 0.000 description 1
- PZNSFCLAULLKQX-UHFFFAOYSA-N Boron nitride Chemical compound N#B PZNSFCLAULLKQX-UHFFFAOYSA-N 0.000 description 1
- 229910017855 NH 4 F Inorganic materials 0.000 description 1
- UMVBXBACMIOFDO-UHFFFAOYSA-N [N].[Si] Chemical compound [N].[Si] UMVBXBACMIOFDO-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 229910001423 beryllium ion Inorganic materials 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 229910001873 dinitrogen Inorganic materials 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 239000011148 porous material Substances 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 238000005389 semiconductor device fabrication Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000007858 starting material Substances 0.000 description 1
- 238000001771 vacuum deposition Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/92—Capacitors with potential-jump barrier or surface barrier
- H01L29/94—Metal-insulator-semiconductors, e.g. MOS
Abstract
Description
제1도는 본 발명의 실시예인 반전회로 구조의 평면도.1 is a plan view of an inverting circuit structure which is an embodiment of the present invention.
제2로는 제1도의 전기적인 회로도.2 is the electrical circuit diagram of FIG.
제3도는 제1도의 A-A선 및 B-B선 단면도.3 is a cross-sectional view taken along line A-A and line B-B of FIG.
제4도는 본 발명의 제조방법을 예시하기 위한 제조공정도.4 is a manufacturing process diagram for illustrating the manufacturing method of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1, 2 : 금속선 3, 5 : P+확산영역1, 2: metal wire 3, 5: P + diffusion region
4, 6 : N+확산영역 7, 8 : 게이트영역4, 6: N + diffusion region 7, 8: gate region
10, 11 : 콘택트 부분 12 : P웰(Well)의 가이드밴드10, 11: contact portion 12: guide band of P-well
20 : 포토레지스트 15, 17 : 휠드로핑부20:
14. 16. 18. 22. 23 : 산화막 24 : 질소규소막14. 16. 18. 22. 23: oxide film 24: nitrogen silicon film
25, 26 : 포토레지스트층 27, 28 : PSG/CVD층.25, 26
본 발명은 반도체소자 제조공정에 있어서, N형 단결정 규소기판에 이온 주입과 확산에 의해 P 우물을 형성시키고 P채널 및 N채널 MOS FET를 복합적으로 만드는 이른바 C MOS 제조공정에 관할 것이다.The present invention relates to a so-called C MOS fabrication process in which a P well is formed by ion implantation and diffusion into an N-type single crystal silicon substrate in a semiconductor device fabrication process, and a P-channel and an N-channel MOS FET are combined.
동일한 기능을 지니는 집적회로를 제작함에 있어서 생산수율을 높이고 생산성의 향상을 위해서는 칩 사이즈(chip-size)의 축소, 다시말해, 단위 면적당의 집적도 증대가 불가피한 것으로서, 칩 사이즈를 축소하고자 할 경우에 대두되는 가장 큰 문제점은 금속연결선의 형성시에 있어서 연결선의 신뢰도가 저하된다는 것인데, 일반적으로 금속연결선은 알루미늄으로 만들어지는데 이것은 진공증착 혹은 스퍼터링(sputtering)방법으로 알루미늄을 증착시키고 사진 식각에 의해 패턴(pattern)을 형성한다.In order to increase production yield and increase productivity in manufacturing integrated circuits having the same function, it is inevitable to reduce the chip size, that is, increase the density per unit area, and to raise the chip size. The main problem is that the reliability of the connection line is reduced when forming the metal connection line. In general, the metal connection line is made of aluminum, which is deposited by vacuum deposition or sputtering, and deposited by patterning. ).
이때의 두께차로 인해 생긴 스탭(step)으로 알루미늄의 두께가 불균일하게 되므로 패턴을 형성할 때 알루미늄선이 끊어지는 경우가 자주 발생하게 되는 것이다. 이를 고려하여 종래에는 이산화 규소(sro2)의 두께차를 줄이기 위해 공정의 최종단계에서 이산화규소막을 길러주고, 경사창 식각(taper etching)방법을 사용하였으나, 이러한 경우에는 패턴의 크기를 줄이기 어렵기 때문에 집적도를 높이는데 문제시 되는 한편, 제조공정에 있어서 소오스와 드레인을 확산시키고, 게이트 부분을 사진 식각(photoetching)법에 의해 형성하기 때문에 마스크 레이어(Masklayer) 간의 얼라이닝(aligning) 문제로 게이트와 드레인 혹은 게이트와 소오스간의 기생용량이 커지게 되어 동작속도가 느려지게 되었던 것으로, 이를 해결하고자 종래에는 게이트 부분의 금속선폭을 게이트길이 보다 좁게 형성하고 이온주입에 의해 드레인과 소오스 영역을 넓혁주는 방식을 취하고 있으나 이는 이온 주입 공정이 두번 더 추가되어야 할 뿐 아니라 그 신뢰도가 저하됐던 것이다.Since the thickness of the aluminum becomes uneven due to the step caused by the thickness difference at this time, the aluminum wire is often broken when the pattern is formed. In consideration of this, conventionally, in order to reduce the thickness difference of silicon dioxide (sro 2 ), a silicon dioxide film was grown at the final stage of the process and a taper etching method was used, but in this case, it is difficult to reduce the size of the pattern. Therefore, it is problematic to increase the density, while in the manufacturing process, the source and the drain are diffused, and the gate portion is formed by photoetching, so the alignment between the mask layer and the mask layer is problematic. As the parasitic capacitance between the drain or the gate and the source is increased, the operation speed is slowed. In order to solve this problem, the metal line width of the gate portion is narrower than the gate length, and the drain and source regions are widened by ion implantation. But the ion implantation process has to be added twice as well The credibility was deteriorated.
본 발명은 이와 같은 점을 감안하여 채널스토퍼를 이온주입에 의해 형성하고 질화규소(Si3N4)막을 이용하여 선택적으로 산화시켜서 알루미늄선의 스텝 커버리지(step coverage)를 향상시키고, 선택산화법에 의해 셀프 얼라인(self align)되도록 함으로써 단위 면적당 많은 수의 소자를 형성할 수 있게하고, 동작속도를 빠르게 함과 동시에 동작전압의 범위를 확대시킬 목적으로 발명한 것으로서, 이를 구체적으로 설명하면 다음과 같다.In view of the above, the present invention forms a channel stopper by ion implantation, selectively oxidizes using a silicon nitride (Si 3 N 4 ) film to improve step coverage of aluminum wire, and self-aligns by selective oxidation. It is invented to be able to form a large number of devices per unit area by being self-aligned, to increase the operating speed and to expand the range of the operating voltage, which will be described in detail as follows.
이온 주입에 의해 휠드(Field)반전 전압을 높이기위한 불순물을 주입하고 질화규소막을 이용한 선택 산화법에 의해 확산 영역 및 게이트 이외의 부분을 열화산화(thermal oxidation) 시킨후 게이트 영역만을 남기고 P+및 N+확산영역의 질화규소막을 식각(Etching)한 다음 HH 웨이퍼(Boron Nitride wafer) 및 PSG를 사용하여 P+와 N+를 동시 확산하고 다시 열화 산화시킨 것이다.Impurities are implanted to increase the field reversal voltage by ion implantation, and thermal oxidation of the diffusion region and the non-gate region is performed by selective oxidation using a silicon nitride film, and only P + and N + diffusions remain behind the gate region. The silicon nitride film was etched and then co-diffused with P + and N + using HH wafer (Boron Nitride wafer) and PSG, followed by deterioration oxidation.
이와 같은 본 발명의 반전회로의 구조를 도면에서와 같은 실시예로서 살펴보면, 제1도는 본 발명에 의해 실시된 반전회로의 구조의고, 제2도는 제1도의 전기적 회로도로서 각 부분에 표시된 숫자는 제1도의 숫자와 대응되는 것이다. 즉, 제1도와 제2도의 반전회로는 일반적인 C-MOS 반전회로로서 P채널 FET(Q1)과 N채널 FET(Q2)로 구성되어 있으며, P채널 FET(Q1)은 N형 규소기판에 P+확산영역(3), (5) 및 게이트 영역(7)과 금속선(1)으로 구성되어 있고, N채널 FET(Q2)는 N형 규소기판에 이온 주입과 고온 확산에 의해 형성된 P웰 영역에 N+확산영역(4)(6) 및 게이트 영역(8)과 금속선(1)으로 구성되어 있는 것으로서 P채널 FET(Q1)와 N채널 FET(Q2)의 게이트가 연결되어 반전회로의 입력이 되고, 확산영역(5), (6)이 콘택트부분(10),(11)을 통해서 금속선(2)에 의해 연결되어 출력단이 된다.Looking at the structure of the inverting circuit of the present invention as an embodiment as shown in the drawings, Figure 1 is the structure of the inverting circuit implemented by the present invention, Figure 2 is the electrical circuit diagram of Figure 1 is the number shown in each part Corresponds to the number in FIG. That is, the inverting circuits of FIG. 1 and FIG. 2 are general C-MOS inverting circuits and are composed of P-channel FETs (Q 1 ) and N-channel FETs (Q 2 ), and P-channel FETs (Q 1 ) are N-type silicon substrates. Is composed of P + diffusion regions (3), (5), gate region (7), and metal lines (1), and the N-channel FET (Q 2 ) is formed by ion implantation and high temperature diffusion into an N-type silicon substrate. It is composed of N + diffusion region (4) (6), gate region (8) and metal line (1) in the well region, and the gates of P-channel FET (Q 1 ) and N-channel FET (Q 2 ) are connected and inverted. The circuit is input, and the diffusion regions 5 and 6 are connected by the
제3(a)도, 제3(b)도는 각각 제1도의 A-A, B-B단면을 도시한 것으로서 "14"는 선택 산화법에 의해 형성된 산화막이고, "15", "17"은 각각 이온 주입에 의해 형성된 휠드도핑(field doping)을 나타내며, "16"은 게이트산화막, "12"는 P웰의 가아드 밴드(guard band)이다.3 (a) and 3 (b) show AA and BB cross-sections of FIG. 1, respectively, where “14” is an oxide film formed by a selective oxidation method, and “15” and “17” are respectively implanted by ion implantation. "16" is a gate oxide film and "12" is a guard band of a P well.
제4도는 본 발명의 실제 제조공정도로서 이를 도면에 의거 상세히 설명하고자 한다.4 is an actual manufacturing process diagram of the present invention will be described in detail based on the drawings.
출발물질은 N형 단결정 규소판으로 직경 3"-5" 두께 15-25mil, 방향성은 (1.0.0)이고, 비저항이 1-5Ω/cm이며 결정 결함이 없어야 한다는 것을 전제로 하고, 공정순서를 살펴보면, 제1공정 제4(a)도는 산화막 형성1단계로서 우선 기판을 잘 세척한 후에 1000℃ 정도의 고온로에서 H2/O2/HCl의 분위기로 산화를 시켜 두께가 1700Å정도의 산화막(18)을 형성한다.The starting material is an N-type single crystal silicon plate with a diameter of 3 "-5", 15-25 mils in thickness, directional (1.0.0), resistivity of 1-5 Ω / cm and no crystal defects. Referring to FIG. 4 (a), the first step of forming the oxide film, the substrate is first washed well and then oxidized in an atmosphere of H 2 / O 2 / HCl in a high temperature furnace at about 1000 ° C. to form an oxide film having a thickness of about 1700 μs ( 18).
제2공정 제4(b)도는 포로레지스트(photo resist) 패턴 형성단계로서, 전면에 포로레지스트(20)를 7000-8000A°의 두께로 도포한 후 마스크(Mask)를 통해 U.V광선에 노출시켜 P웰 포로레지스트패턴을 형성하고 가속전압 100kev로 8*1013cm-2정도의 붕소이온을 "21" 부분에 이온 주입기로 주입한다. 이에 "21"을 제외한 다른 부분은 포토레지스트(20)와 산화막(18)에 의해 이온 주입이 안된다.FIG. 4 (b) shows a process of forming a photoresist pattern. The photoresist 20 is applied to the entire surface with a thickness of 7000-8000 A °, and then exposed to UV light through a mask. A well pores resist pattern is formed, and boron ions of about 8 * 10 13 cm -2 are implanted into the "21" portion with an ion implanter at an acceleration voltage of 100 kev. Therefore, other portions except for "21" cannot be ion implanted by the photoresist 20 and the oxide film 18.
제3공정 제4(c)도는 산화막형성 2단계로서, 이온주입을 한 후 NH4F 혹은 BHF로 산화막을 식각해내고, H2SO4혹은 O2를 플라즈마(plasma) 장치를 써서 포토레지스트를 벗겨내고 다시 웨이퍼를 세척한 후 1160℃의 고온로에서 N2/O2분위기로 장시간 확산을 시켜 접합깊이(junction depth)가 8-10㎛, N형 기판 위의 산화막(22)이 3000A 정도 되게한다.Step 3 (c) of FIG. 3 shows a step of forming an oxide film. After ion implantation, the oxide film is etched with NH 4 F or BHF, and H 2 SO 4 or O 2 is converted into a photoresist using a plasma apparatus. After peeling off, the wafer is washed again and then diffused for a long time in an N 2 / O 2 atmosphere in a high temperature furnace at 1160 ° C. so that the junction depth is 8-10 μm and the oxide film 22 on the N-type substrate is about 3000 A. do.
제4공정 제4(a)도는 질화규소(si3N4)막 형성단계로서, 웨이퍼를 BHF에 3분 가량 담가 전면 산화막을 제거하고 잘 세척하여 950℃의 고온로에서 H2/O2/HCl 분위기로 하여 900-1000Å 정도의 산화막(23)을 기른 후에 CVD 혹은 LPCVD 방법으로 2000-3000Å의 질화규소막(24)를 형성한다.Step 4 (a) is a step of forming a silicon nitride (si 3 N 4 ) film, and the wafer is immersed in BHF for about 3 minutes to remove the entire surface oxide film and washed well in a H 2 / O 2 / HCl furnace at 950 ° C. An
제5공정 제4(e)도는 산화막 패턴 형성단계로서, P웰 패턴 형성과 동일한 사진술에 의해 P+, N+확산될 부분과 게이트 영역을 제외한 피드(Field) 영역을 플라즈마 에칭 혹은 160℃ 정로의 인산(H3PO4) 용액으로 식각해낸다. 인산으로 식각할 경우는 포로레지스트를 도포하기 전에 고온로에서 질화 규소막을 산화시키거나 CVD 산화막을 1000Å 정도 입힌후에 사진식각술에 의해 산화막의 패턴을 형성하고 포토레지스트를 벗겨낸 후 질화 규소막을 식각해야 한다.The fourth step (e) of the fifth step is an oxide film pattern forming step, in which the P + , N + areas to be diffused by the same photography as the P well pattern formation and the feed (Field) area except the gate area are plasma-etched or 160 ° C. Etch with a solution of phosphoric acid (H 3 PO 4 ). In case of etching with phosphoric acid, the silicon nitride film should be oxidized in a high temperature furnace or coated with CVD oxide film at 1000Å before forming the photoresist. Then, the pattern of the oxide film is formed by photolithography, the photoresist is peeled off, and the silicon nitride film is etched. do.
제6, 7공정 제4(f)도, 제4(g)도는 휠드도핑을 위한 이온 주입단계로서, 사진 공정에 의해 P+휠드도핑 패턴(25)를 형성하고 가속전압 40kev 으로 8×1012cm-2의 붕소이온을 주입기로 "15" 부분에 주입한 후, 포토레지스트층(25)를 제거하고 다시 사진공정으로 N+칩드도핑 패턴을 형성하여 가속전압 130kev으로 3×1012cm-2의 인(P) 이온을 "17"영역에 주입한 후 포토레지스트층(26)을 제거하고 BHF로 "15", "17"영역의 산화막을 식각해 낸다.The sixth, seventh step of claim 4 (f) also, the 4 (g) turning as an ion implantation step for Wheeled doped, with P + Wheeled doped pattern formation and the acceleration voltage 40kev to 25 by the photolithography process 8 × 10 12 After implanting the cm -2 boron ion into the "15" part with an injector, the photoresist layer 25 was removed and again, an N + chipped doping pattern was formed by a photographic process to obtain an acceleration voltage of 130 kev 3 x 10 12 cm -2. After implanting phosphorus (P) ions into the "17" region, the photoresist layer 26 is removed and the oxide films in the "15" and "17" regions are etched with BHF.
이온 주입을 할때 P+, N+확산영역 및 게이트 영역에는 이온 주입이 안되도록 질화규소막(24)이 충분히 두꺼워야 하는데 너무 두꺼우면 산화시 규소기판에 결정결함을 많이 생기게 하므로 2000-3000Å이 적당하다.During ion implantation, the silicon nitride film 24 should be thick enough to prevent ion implantation in the P + , N + diffusion and gate regions. If too thick, the silicon substrate will have many crystal defects during oxidation. Do.
제8공정 제4(h)도는 산화막형성 3단계로서, 1000℃의 고온로에서 H2/O2/HCl 분위기로 산화시켜 소자와 소자를 분리시키는 휠드(Field) 산화막을 8000-10,000Å 두께로 기른다. 이때 질소규소막은 산화율이 규소기판에 비해 대단히 작으므로 선택적으로 산화가 되고 산화막 두께의 0.46배 정도가 규소기판 표면 밑으로 들어가게 된다. 이때 질화규소막과 규소기판의 열팽창계수가 다르기 때문에 스트레스(stress)에 의한 결정결함이 생길 수 있는데 이것을 줄이기 위해서 900-1000Å 정도의 산화막(23)을 길러준 것이다.Step 8 (h) of the eighth step is a three-step formation of an oxide film, in which a field oxide film which separates an element from an element by oxidizing in an H 2 / O 2 / HCl atmosphere in a high temperature furnace at 1000 ° C. has a thickness of 8000-10,000Å. Nourish At this time, since the silicon oxide film has a very small oxidation rate compared to that of the silicon substrate, it is selectively oxidized and about 0.46 times the thickness of the oxide film enters the surface of the silicon substrate. At this time, since the thermal expansion coefficients of the silicon nitride film and the silicon substrate are different, crystal defects may occur due to stress. To reduce this, an
제9공정 제4(i)도는 붕소확산단계로서, 사진 식각공정에 의해 게이트영역을 제외한 P+,N+확산 영역의 질화규소막(24)과 얇은 산화막(23)을 제거한 후 N+불순물원으로 사용할 PSG(phosphosilica glass)를 3000Å 정도입히고 순수한 CVD 실리콘 산화막(28)을 2000-3000Å 정도 입힌 다음 N+확산 영역만 남기고 그의 P+확산 영역을 사진 식각술에 의해 식각해낸 다음 970℃의 고온로에서 BN 웨이퍼를 사용하여 질소가스(N2) 분위기로 "3", "5", "12" 영역에 붕소를 확산시켜 쉬이트 레지스턴스(sheetresistance)(Rs)가 40Ω/ㅁ되게 한다. 이때 "4", "6"의 영역에도 PSG로 부터 인이 확산되어 쉬이트레지스턴스(Rs)가 20Ω/ㅁ정도된다.The fourth step (i) of the ninth process is a boron diffusion step, in which the silicon nitride film 24 and the
제10공정 제4(j)도는 산화막형성 4단계로서, PSG/CVD층인 "27", "28"을 BHF로 식각해내고, 1000℃의 고온로에서 H2/O2/HCl 분위기로 산화시켜 5000-6000Å의 산화막을 형성한다. 이때에도 산화막 형성 3단계(제8공정 : 아)에서와 마찬가지로 선택산화가 이루어지며 게이트 영역이 자동적으로 형성되어 소오스, 드레인, 게이트가 셀프얼라인이 되는 것이다.Step 4 (j) of the tenth step is an oxide film formation step 4, in which the PSG / CVD layers " 27 " and " 28 " are etched with BHF and oxidized to H 2 / O 2 / HCl in a high temperature furnace at 1000 ° C. An oxide film of 5000-6000 Pa is formed. At this time, as in the third step (8th step: a) of oxide film formation, selective oxidation is performed and gate regions are automatically formed so that the source, drain, and gate are self-aligned.
제11공정 제4(k)도는 완성단계로서, 질화규소(Si3N4) 막(24)과 그 밑에 있는 얇은 산화막을 제거한후 1000℃의 고온로에서 O2/HCl 분위기를 산화시켜 900Å 정도의 게이트 산화막(16)을 거른 후 FET의 동작개시 전압을 조정하기 위해 붕소이온을 40kev, 2-3×1011cm-2정도 주입하고 1000℃의 고온로에서 N2분위기로 열처리(annealing) 공정을 거친 다음 사진식각에 의해 콘택트 부분(10), (11)의 산화막을 제거하고 전면에 1㎛ 정도의 알루미늄막을 입힌 후 사진식각에 의해 알루미늄 패턴을 형성한다.Step 4 (k) of the eleventh step is a completion step, and after removing the silicon nitride (Si 3 N 4 ) film 24 and the thin oxide film under it, the O 2 / HCl atmosphere is oxidized in a high temperature furnace at 1000 ° C. After filtering the gate oxide layer 16, boron ions are injected at about 40 kev, 2-3 × 10 11 cm -2 to adjust the FET's starting voltage, and annealing is performed in an N 2 atmosphere in a 1000 ° C. high temperature furnace. After the rough, the oxide films of the contact portions 10 and 11 are removed by photolithography, an aluminum film having a thickness of about 1 μm is coated on the entire surface, and an aluminum pattern is formed by photolithography.
알루미늄과 콘택트 부분의 실리콘 사이에 충분한 알로이(alloy)가 형성되어 콘택트저항이 작아지도록 450℃ N2분위기에서 30분가량의 열처리 공정을 마지막으로 하여 복합 MOS 집적회로가 완성되는 것이다.Sufficient alloys are formed between the aluminum and the silicon of the contact portion, and the composite MOS integrated circuit is completed by performing a heat treatment process for about 30 minutes in a 450 ° C. N 2 atmosphere so as to reduce contact resistance.
이러한 공정을 거쳐서 제작된 본 발명은 휠드 도핑과 질화규소(Si3N4) 막을 이용한 선택산화법으로서 산화막단차의 감소에 기인하는 금속선의 스텝커버리지를 향상시켜 금속 연결선의 신뢰도를 높임은 물론 게이트의 셀프얼라인이 이루어지게 되므로서 동작 속도가 빠르게 되어 동작전압의 범위를 확대시킬 수 있는 매우 유익한 특징이 있다.The present invention produced through such a process is a selective oxidation method using wheeled doping and silicon nitride (Si 3 N 4 ) film to improve the step coverage of the metal wire resulting from the reduction of the oxide film step to increase the reliability of the metal connecting line as well as the self-aligning of the gate Since phosphorus is made, the operation speed becomes high, and thus, there is a very advantageous feature that can extend the range of the operating voltage.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR8204596A KR850000037B1 (en) | 1982-10-13 | 1982-10-13 | The method of mos with self alignment metal electroid |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR8204596A KR850000037B1 (en) | 1982-10-13 | 1982-10-13 | The method of mos with self alignment metal electroid |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR840002160A KR840002160A (en) | 1984-06-11 |
| KR850000037B1 true KR850000037B1 (en) | 1985-02-13 |
Family
ID=19225799
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR8204596A KR850000037B1 (en) | 1982-10-13 | 1982-10-13 | The method of mos with self alignment metal electroid |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR850000037B1 (en) |
-
1982
- 1982-10-13 KR KR8204596A patent/KR850000037B1/en active
Also Published As
| Publication number | Publication date |
|---|---|
| KR840002160A (en) | 1984-06-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR940008728B1 (en) | Semiconductor device and manufacturing method thereof | |
| US4149307A (en) | Process for fabricating insulated-gate field-effect transistors with self-aligned contacts | |
| JPH0343778B2 (en) | ||
| US4292156A (en) | Method of manufacturing semiconductor devices | |
| US3986896A (en) | Method of manufacturing semiconductor devices | |
| US3670403A (en) | Three masking step process for fabricating insulated gate field effect transistors | |
| US4621412A (en) | Manufacturing a complementary MOSFET | |
| JPS5843912B2 (en) | Method for manufacturing semiconductor integrated circuit device | |
| KR850000037B1 (en) | The method of mos with self alignment metal electroid | |
| JPS60193371A (en) | Manufacture of semiconductor device | |
| US3825455A (en) | Method of producing insulated-gate field-effect semiconductor device having a channel stopper region | |
| KR840002055B1 (en) | The method of mos with metalic electrode fabrication | |
| JPH08162523A (en) | Semiconductor device, and its manufacture | |
| JP2817226B2 (en) | Method for manufacturing semiconductor device | |
| KR970006255B1 (en) | Fabrication method of tft | |
| JPH05102181A (en) | Manufacture of high-breakdown-strength semiconductor device | |
| JPH0554263B2 (en) | ||
| KR0161844B1 (en) | Etching method for poly silicon with selective oxidation | |
| JPH0621094A (en) | Manufacture of semiconductor device | |
| JPS61251165A (en) | Manufacture of bi-mis integrated circuit | |
| KR100186513B1 (en) | Manufactrure of semiconductor device | |
| KR960011639B1 (en) | Formation of shallow-junction using titanium silicide | |
| KR940000986B1 (en) | Manufacturing method of stack type cmos | |
| JP2609222B2 (en) | Method for manufacturing semiconductor device | |
| JPH01125976A (en) | Semiconductor device |