JP2609222B2 - Method for manufacturing semiconductor device - Google Patents

Description

The present invention relates to a method for manufacturing a semiconductor. The present invention can be used for the manufacture of various semiconductors. In particular, for example, a semiconductor device having first and second conductive regions such as CMOS having both N-type and P-type diffusion regions. Used for manufacturing.

[Summary of the Invention] The present invention relates to a method of manufacturing a semiconductor device having first and second conductive regions, wherein after forming the first and second conductive regions,
First, in a first masking step, an electrode window is opened in one of the conductive regions using a photoresist as a mask, and the electrode window is formed in a portion at least a part of which is deviated from the conductive region, After the opening of the electrode window, ions of the same conductivity type as that of the conductive region are implanted into the electrode window using the same photoresist as a mask to form an auxiliary diffusion region continuously with the same photoresist remaining. To form an auxiliary diffusion region, and then remove the photoresist. Then, in a second mask step, an electrode window is opened in the other conductive region using the photoresist as a mask,
The electrode window is formed at least in a portion where the electrode window deviates from the conductive region. After the opening of the electrode window, an auxiliary diffusion region is formed continuously with the photoresist remaining. By using the same photoresist as a mask, an impurity of the same conductivity type as that of the conductive region is introduced into the electrode window by ion implantation to form an auxiliary diffusion region, and then the photoresist is removed. In the case where it is located outside the conductive region,
This is to make it possible to solve problems such as leak generation and poor withstand voltage by a simple means of reducing the number of mask steps required twice to one and repeating the same steps.

[Conventional technology]

In the semiconductor device manufacturing process, if the electrode window protrudes from the diffusion region due to misalignment of the mask in the process of opening the electrode window in the semiconductor device, failures such as a junction leak and a junction breakdown voltage failure occur. As a countermeasure, a diffusion region is expanded in the electrode window after the electrode window is opened.

This will be described with reference to FIGS. 2 and 3. When a diffusion region 3 of the opposite conductivity type to the substrate 1 is formed on the semiconductor substrate 1 and an electrode is taken out from the diffusion region 3, a commonly used process is as follows. As shown in FIG. 2, first, for example, a first insulating film 2 such as SiO ₂ is formed on the surface of a P-type semiconductor substrate 1.
Is selectively formed, and an N-type impurity is introduced using the insulating film 2 as a mask to form an N-type diffusion region 3. The N-type diffusion region 3 may be formed by, for example, arsenic (As) ion implantation. For example, in the case of a MOS FET, the diffusion region 3 corresponds to a source and a drain. Thereafter, CVD SiO ₂ or the like is grown as the second insulating film 4. Heat treatment in an oxidizing atmosphere when forming the diffusion region 3
SiO ₂ may be used as the second insulating film 4. Next, a part of the insulating film 4 is removed to form an electrode window 6, and Al is deposited and etched into a predetermined pattern to form an N-type diffusion region having an Al electrode 5 as shown in FIG. can do.

Incidentally, increasing the degree of integration is always required as a basic requirement. Based on this requirement, in order to improve the degree of integration, the diffusion region 3 is preferably as small as possible. In FIG. 3, it is desirable that w in the figure be small.
In order to increase the degree of integration in this way, the distance l (see FIG. 3) between the electrode window 6 and the end of the diffusion region 3 must be reduced. However, when this 1 is reduced, if there is a misalignment between the mask forming the diffusion region 3 and the mask forming the electrode window, the second insulating film 4 is etched to open the electrode window 6. Then, the first insulating film 2 is also etched, and as a result, the electrode window 6 may come off from the diffusion region as shown in FIG. 4, and if the electrode 5 is formed as it is, the symbol a in FIG. As shown, the electrode 5 comes into contact with the substrate 1. This is observed as leakage of the PN junction or poor junction breakdown voltage.

As a countermeasure against this problem, an impurity having the same conductivity type as that of the diffusion region 3 is introduced into the electrode window 6 after the electrode window 6 is opened.
As shown in FIG. 5, the diffusion region 3 is expanded to form an auxiliary diffusion region 3 '. The contact between the electrode 5 and the substrate 1 is prevented by the auxiliary diffusion region 3 '. In this case, the auxiliary diffusion region 3 'is formed by ion-implanting, for example, phosphorus (P).

The N-type diffusion region has been described above as an example, but the same applies to the case where an electrode window is opened in the P-type diffusion region. P-type impurities, for example, boron (B) are ion-implanted into the electrode window of the P-type diffusion region. .

[Problems to be solved by the invention]

When the above process is applied to a semiconductor device having both first and second conductive regions, for example, a structure such as a CMOS circuit having both N-type and P-type diffusion regions, the mask process is required at least three times. Become. That is, as schematically shown in FIG. 6 (a), first, electrode windows 61 and 62 are formed in a mask step (1), and then, as shown in FIG. ) Is implanted to form an auxiliary diffusion region 31 '(mask step (2)), and then boron or the like is implanted into the P-type diffusion region 32 to form an auxiliary diffusion region 32' (mask fixing (3)). FIG. 6 (c)). In the drawing, reference numeral 7 denotes a photoresist, and M denotes a mask.

As described above, in the prior art, at least three mask steps such as the electrode window mask step (1), the N-type impurity introduction mask step (2), and the P-type impurity introduction mask step (3) are required. A process was required.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor manufacturing technique in which the number of mask steps conventionally required at least three times in the manufacturing process of a semiconductor device having two conductive regions is reduced and the steps are shortened.

[Structure and operation of the invention]

In the method for manufacturing a semiconductor device according to the present invention, in the method for manufacturing a semiconductor device having first and second conductive regions, after forming the first and second conductive regions, first, in a first mask process, Using a resist as a mask, opening an electrode window in one of the conductive regions,
The electrode window is formed at least at a part where the electrode window deviates from the conductive region. After the opening of the electrode window, the photoresist is continuously formed with the photoresist remaining to form an auxiliary diffusion region. Using the same photoresist as a mask, an impurity of the same conductivity type as that of the conductive region is introduced into the electrode window by ion implantation to form an auxiliary diffusion region. Thereafter, the photoresist is removed. Next, in a second mask process, An electrode window is opened in the other conductive region using a photoresist as a mask, and the electrode window is formed at a portion where at least a part of the electrode window departs from the conductive region. In order to form an auxiliary diffusion region continuously with the resist remaining, an impurity of the same conductivity type as that of the conductive region is introduced into the electrode window by ion implantation using the same photoresist as a mask. An auxiliary diffusion region is formed, and then the photoresist is removed.

That is, for example, first, in the first mask step, an electrode window is opened only in the N-type diffusion region portion (the electrode window is at a position at least partly deviated from the region portion), and after the electrode window is opened. In the state where the photoresist remains, an N-type impurity is introduced by ion implantation into the electrode window using the same photoresist as a mask to form an auxiliary diffusion region continuously, and then the photoresist is removed. Subsequently, in the second mask step, an electrode window is opened only in the P-type diffusion portion (at least a part of the electrode window is at a position deviated from the region portion). In order to form an auxiliary diffusion region continuously with the photoresist remaining, a P-type impurity is introduced into the electrode window by ion implantation using the photoresist as a mask, and then the photoresist is removed. You can use.

When this method of the present invention is used, the number of mask steps may be two for each conductive region, and the number of mask steps can be reduced by one compared with the prior art. In addition, both the first and second mask steps can perform ion implantation. And the subsequent steps of removing the photoresist may be repeated, so that the problems of the prior art can be solved by a simple method.

Japanese Patent Application Laid-Open No. 58-10856 discloses a technique in which impurities are introduced into a CMOS semiconductor device by a two-step mask process for improving the contact property of a contact. The present invention is not related to the present invention because it is not a technique for assuming that the (contact) deviates from the conductive region. Further, in the first mask step, impurities are introduced using the contact as a mask after the photoresist is removed, and the second mask is formed. In the process, unlike this, a method of introducing impurities while leaving the photoresist is adopted, and a method different from that of the present invention is employed. In addition, JP
Japanese Patent No. -206074 discloses that an impurity is diffused into an n-channel portion by ion implantation using the phosphosilicate glass as a mask in an n-channel portion with respect to a contact opening already formed. Although a technique of forming a layer is disclosed, in this conventional technique, formation of a contact opening and formation of an impurity diffusion layer are not performed continuously, and an auxiliary diffusion region of both conductivity types is formed by ion implantation. Not only is the configuration different from the present invention to be formed, but also in practice, the mask step requires three or more steps.

(Example of the invention)

FIGS. 1 (a) and 1 (b) show the next embodiment of the present invention.
This will be described with reference to FIG.

In this embodiment, an N-type diffusion region 31 and a P-type diffusion region 32 are used.
The present invention is applied to the manufacture of a CMOS having two conductive regions. In the CMOS of this example, an N well 1 ′
To form an N-type diffusion region 31 in the P-type portion of the substrate 1 and a P-type diffusion region in the N well 1 '.

 This semiconductor device is manufactured as follows.

A first insulating film 2 is selectively formed on the substrate 1, and an N-type diffusion region 31 and a P-type diffusion region 32 are formed by ordinary means. Next, a second insulating film 4 is formed using PSG or the like as a material.

Next, electrode windows 61, 62 of the N-type and P-type diffusion regions 31, 32 are formed, and auxiliary diffusion regions 31 ', 32' for preventing contact between the electrodes and the substrate 1 are formed as described above. In the present embodiment, this is performed as follows.

As shown in FIG. 1 (a), a photoresist 7 is formed, which is exposed and removed in a first mask step to obtain an electrode window 61. Ion implantation of phosphorus (P ⁺ ) or the like (indicated by P ⁺ II in FIG. 1) through the electrode window 61 forms an N-type auxiliary diffusion region 31 ′. Thereafter, the photoresist 7 is removed.

Next, a photoresist 7 'is formed as shown in FIG. 1 (b), and this is exposed and removed in a second mask process to form an electrode window 62'.
(A mask is not shown). Ion implantation of boron (B ⁺ ) or the like through the electrode window 62 (indicated by B ⁺ II in FIG. 1)
As a result, a P-type auxiliary diffusion region 32 'is formed.
Thereafter, the photoresist 7 is removed.

As described above, according to this method, a desired CMOS structure can be obtained in two mask steps.

〔The invention's effect〕

According to the present invention, the mask process which was conventionally required three times is reduced to two.
The number of times can be reduced, and the process can be shortened. As a result, efficiency is increased, and the possibility of occurrence of trouble is reduced, so that cost reduction and yield improvement can be expected.

[Brief description of the drawings]

FIGS. 1A and 1B show an embodiment of the present invention in the order of steps. 2 to 5 show the prior art, and FIGS. 6 (a), (b) and (c) show the conventional example in the order of steps. 1 ... substrate, 31 ... first conductive region, 32 ... second conductive region, 61, 62 ... electrode window.

Claims (1)

(57) [Claims] In a method of manufacturing a semiconductor device having first and second conductive regions, after forming the first and second conductive regions, first, in a first masking step, one of the first and second conductive regions is formed using a photoresist as a mask. An electrode window was opened in one conductive region, and the electrode window was formed at a portion at least part of which departed from the conductive region, and after opening the electrode window, the photoresist was left. In the same state, an impurity having the same conductivity type as that of the conductive region is introduced into the electrode window by ion implantation using the same photoresist as a mask to form an auxiliary diffusion region, thereby forming an auxiliary diffusion region. Then, in a second masking step, an electrode window is opened in the other conductive region using the photoresist as a mask, and the electrode window is formed at a portion where at least a part thereof is deviated from the conductive region. After the opening of the electrode window, the same photoresist as the conductive region is formed in the electrode window using the photoresist as a mask in order to form an auxiliary diffusion region continuously with the photoresist remaining. Forming an auxiliary diffusion region by ion implantation of an impurity, and thereafter removing the photoresist.