JPH06163450A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH06163450A
JPH06163450A JP31543292A JP31543292A JPH06163450A JP H06163450 A JPH06163450 A JP H06163450A JP 31543292 A JP31543292 A JP 31543292A JP 31543292 A JP31543292 A JP 31543292A JP H06163450 A JPH06163450 A JP H06163450A
Authority
JP
Japan
Prior art keywords
insulating layer
diffusion layer
forming
layer
semiconductor substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP31543292A
Other languages
Japanese (ja)
Inventor
Masato Miyamoto
正人 宮本
Shigeo Akiyama
茂夫 秋山
Koichi Yamada
耕一 山田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to JP31543292A priority Critical patent/JPH06163450A/en
Publication of JPH06163450A publication Critical patent/JPH06163450A/en
Pending legal-status Critical Current

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  • Drying Of Semiconductors (AREA)

Abstract

PURPOSE:To provide a method of manufacturing a semiconductor device, wherein impurity doping processes can be lessened in number. CONSTITUTION:When a diffusion layer non-uniform in impurity concentration is formed on the surface of a semiconductor substrate 1, an insulating layer is formed on the surface of the semiconductor substrate first, then the insulating layer formed on a region where a diffusion layer of comparatively high impurity concentration is to be formed is partially removed, another insulating layer 5 is formed on the insulating layer-removed region and the residual insulating layer, a resist film is formed on the insulating layer 5 excluding a region where a diffusion layer is formed, the insulating layer 5 is subjected to an etching process, and then impurities 19 are diffused for doping for the formation of a diffusion layer.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】この発明は、半導体装置の製造方
法、特に、半導体基板に対し不純物濃度の異なる拡散層
を形成する工程を含む半導体装置の製造方法に関するも
のである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device including a step of forming diffusion layers having different impurity concentrations on a semiconductor substrate.

【0002】[0002]

【従来の技術】半導体基板の表面に不純物濃度の異なる
拡散層を形成する場合、まず半導体基板表面に絶縁層を
形成しておいて、ひとつの拡散層を形成する部分上の絶
縁層を除去して不純物をドープした後、この部分を絶縁
層で覆っておいて、別の拡散層を形成する部分にも同じ
工程を繰り返し行うようにするか、または、不純物濃度
の高い拡散層を形成する部分上の絶縁層を除去して不純
物をドープすることを順次行うことが一般的であった。
2. Description of the Related Art When forming a diffusion layer having different impurity concentrations on the surface of a semiconductor substrate, first, an insulating layer is formed on the surface of the semiconductor substrate, and then the insulating layer on the portion where one diffusion layer is formed is removed. After doping with impurities, cover this part with an insulating layer and repeat the same process for the part where another diffusion layer is formed, or the part where a diffusion layer with high impurity concentration is formed It was common to remove the upper insulating layer and dope impurities sequentially.

【0003】[0003]

【発明が解決しようとする課題】しかし、上述の方法
は、不純物濃度の異なる拡散層の数と同じ回数だけ不純
物ドープ工程が必要であるという欠点があった。この発
明は、上記問題点に鑑みて、その課題とするところは、
不純物ドープ工程の回数を減らすことが出来る半導体装
置の製造方法を提供することにある。
However, the above method has a drawback in that the impurity doping step is required as many times as the number of diffusion layers having different impurity concentrations. In view of the above-mentioned problems, the present invention has the following problems.
It is an object of the present invention to provide a method for manufacturing a semiconductor device that can reduce the number of impurity doping steps.

【0004】[0004]

【課題を解決するための手段】この発明にかかる半導体
装置の製造方法は、上記課題を解決するために、半導体
基板の表面に不純物濃度の異なる拡散層を形成する半導
体装置の製造方法において、前記半導体基板表面に絶縁
層を形成したのち、比較的不純物濃度の高い拡散層を形
成するための部分上の前記絶縁層を部分的に除去し、こ
の除去部分と残る絶縁層部分上にさらに絶縁層形成を行
ってから、この絶縁層上に拡散層を形成する部分を残し
てレジスト膜を形成して前記絶縁層に対しエッチング処
理を施したのち、拡散層を形成するための不純物ドープ
を行うことを特徴とするものである。
In order to solve the above-mentioned problems, a method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device, wherein diffusion layers having different impurity concentrations are formed on a surface of a semiconductor substrate. After forming the insulating layer on the surface of the semiconductor substrate, the insulating layer on the portion for forming the diffusion layer having a relatively high impurity concentration is partially removed, and the insulating layer is further formed on the removed portion and the remaining insulating layer portion. After the formation, a resist film is formed on the insulating layer while leaving a portion for forming the diffusion layer, and the insulating layer is etched, and then impurity doping for forming the diffusion layer is performed. It is characterized by.

【0005】この発明の半導体装置の製造方法では、普
通、エッチング処理を不純物濃度の高い拡散層を形成す
るための部分上の絶縁層が完全に除去されるまで行う。
勿論、エッチング処理終了段階では比較的不純物濃度の
低い拡散層を形成するための部分上の絶縁層は完全に除
去されず未だ残っている状態である。ただ、エッチング
処理を不純物濃度の高い拡散層を形成するための部分上
の絶縁層が完全に除去されるまでに停止してもよい。こ
の状態でも、不純物濃度の高い拡散層を形成する部分の
上に残る絶縁層と、不純物濃度の低い拡散層を形成する
部分の上に残る絶縁層との間に絶縁膜の厚み差があるか
らである。
In the method of manufacturing a semiconductor device of the present invention, the etching process is usually performed until the insulating layer on the portion for forming the diffusion layer having a high impurity concentration is completely removed.
Of course, at the stage of finishing the etching process, the insulating layer on the portion for forming the diffusion layer having a relatively low impurity concentration is not completely removed and is still left. However, the etching process may be stopped until the insulating layer on the portion for forming the diffusion layer having a high impurity concentration is completely removed. Even in this state, there is a difference in the thickness of the insulating film between the insulating layer remaining on the portion forming the diffusion layer having a high impurity concentration and the insulating layer remaining on the portion forming the diffusion layer having a low impurity concentration. Is.

【0006】[0006]

【作用】この発明では、不純物ドープを行うにあたっ
て、少なくとも不純物濃度の比較的低い拡散層を形成す
る部分では半導体基板上に薄い絶縁層が残るようにして
おいて、この残存する絶縁層の厚みで不純物の注入量
(ドーズ量)を制御するようにした。このため、同時の
注入であっても、絶縁層の残存厚み差に応じた不純物濃
度の差異が拡散部分間でつくようになる。半導体基板上
に残す絶縁層の厚み調節により、比較的低い濃度の拡散
層での不純物濃度が所望のものとなるように制御するこ
とができる。
According to the present invention, when impurities are doped, a thin insulating layer is left on the semiconductor substrate at least in the portion where the diffusion layer having a relatively low impurity concentration is formed. The impurity injection amount (dose amount) is controlled. Therefore, even if the implantation is performed at the same time, a difference in the impurity concentration according to the difference in the remaining thickness of the insulating layer is generated between the diffusion portions. By adjusting the thickness of the insulating layer left on the semiconductor substrate, it is possible to control the impurity concentration in the diffusion layer having a relatively low concentration to be a desired concentration.

【0007】[0007]

【実施例】以下、この発明の実施例を、製造工程を説明
する図1〜図6を参照しながら説明する。勿論、この発
明は、下記の実施例に限らない。まず、図2に示すよう
に、シリコンなどの半導体基板1の表面に第1の酸化シ
リコンなどの絶縁層2を形成しておいて、その上にフォ
トリソグラフィ技術を利用してレジスト膜3を形成す
る。そして、エッチング工程とレジスト膜除去工程を施
すことによって、図3に示すように、絶縁層2中の、比
較的不純物濃度の高い拡散層を形成する部分に開口部4
を形成したのち、半導体基板1表面全体を酸化する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of the present invention will be described below with reference to FIGS. Of course, the present invention is not limited to the following embodiments. First, as shown in FIG. 2, a first insulating layer 2 of silicon oxide or the like is formed on the surface of a semiconductor substrate 1 of silicon or the like, and a resist film 3 is formed thereon by using a photolithography technique. To do. Then, by performing the etching process and the resist film removing process, as shown in FIG. 3, the opening 4 is formed in the insulating layer 2 where a diffusion layer having a relatively high impurity concentration is formed.
After forming, the entire surface of the semiconductor substrate 1 is oxidized.

【0008】そうすると、図4に示すように、半導体基
板1表面の絶縁層5は、開口部4を覆う部分5aでは薄
く、その他の部分5bでは厚い。つぎに、図5に示すよ
うに、拡散層を形成する部分以外の部分にレジスト膜6
を形成しておいて、図1に示すように、絶縁層5におけ
る薄い部分5aが除去されて開口部7が再び現れるまで
エッチング処理を行い、その後で不純物の注入を行う。
このとき、開口部4以外の部分に存在する、比較的不純
物濃度の低い拡散層を形成するための部分の半導体基板
1上には、比較的薄い絶縁層8が残る。不純物19は、
図1に破線で示すように、開口部7のみでなく、薄い絶
縁層8が残っている部分にも注入される。しかし、図6
に示すように、薄い絶縁層8のある部分では、絶縁膜8
を通して不純物の注入が行われるので、得られた拡散層
10のドーズ量は、開口部7の部分の拡散層9のドーズ
量に比べて少なくなる。このように、一回の不純物ドー
プ工程で不純物濃度の異なる拡散層9,10の形成が実
現できているのである。
Then, as shown in FIG. 4, the insulating layer 5 on the surface of the semiconductor substrate 1 is thin in the portion 5a covering the opening 4 and thick in the other portions 5b. Next, as shown in FIG. 5, the resist film 6 is formed on the portion other than the portion where the diffusion layer is formed.
Then, as shown in FIG. 1, an etching process is performed until the thin portion 5a of the insulating layer 5 is removed and the opening portion 7 reappears, and then impurities are implanted.
At this time, the relatively thin insulating layer 8 remains on the semiconductor substrate 1 in the portion other than the opening 4 for forming the diffusion layer having a relatively low impurity concentration. Impurity 19 is
As shown by the broken line in FIG. 1, not only the opening 7 but also the portion where the thin insulating layer 8 remains is implanted. However, FIG.
As shown in FIG.
Since the impurity is implanted through the diffusion layer 10, the dose amount of the obtained diffusion layer 10 becomes smaller than the dose amount of the diffusion layer 9 in the opening portion 7. In this way, the formation of the diffusion layers 9 and 10 having different impurity concentrations can be realized in one impurity doping step.

【0009】[0009]

【発明の効果】この発明の製造方法によれば、上記のよ
うに、拡散層を形成する部分でも絶縁層が残るようにし
て、その厚みによって不純物濃度を制御するようにした
ので、不純物濃度の異なる複数の拡散層を少ない回数の
不純物ドープ工程で形成できるようになった。
According to the manufacturing method of the present invention, as described above, the insulating layer is left in the portion where the diffusion layer is formed, and the impurity concentration is controlled by the thickness of the insulating layer. It has become possible to form a plurality of different diffusion layers by a small number of impurity doping steps.

【図面の簡単な説明】[Brief description of drawings]

【図1】実施例での絶縁層エッチング・不純物注入工程
を示す断面図。
FIG. 1 is a cross-sectional view showing an insulating layer etching / impurity implantation process in an example.

【図2】実施例でのレジスト膜形成工程を示す断面図。FIG. 2 is a cross-sectional view showing a resist film forming process in an example.

【図3】実施例での開口部形成工程を示す断面図。FIG. 3 is a cross-sectional view showing an opening forming process in an example.

【図4】実施例での酸化処理工程を示す断面図。FIG. 4 is a sectional view showing an oxidation treatment step in the example.

【図5】実施例でのレジスト膜形成工程を示す断面図。FIG. 5 is a cross-sectional view showing a resist film forming process in an example.

【図6】実施例で形成された拡散層を示す断面図。FIG. 6 is a sectional view showing a diffusion layer formed in an example.

【符号の説明】[Explanation of symbols]

1 半導体基板 2,5,8 絶縁層 3,6 レジスト膜 9,10 拡散層 19 不純物 1 Semiconductor Substrate 2,5,8 Insulation Layer 3,6 Resist Film 9,10 Diffusion Layer 19 Impurity

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 半導体基板の表面に不純物濃度の異なる
拡散層を形成する半導体装置の製造方法において、前記
半導体基板表面に絶縁層を形成したのち、比較的不純物
濃度の高い拡散層を形成するための部分上の前記絶縁層
を部分的に除去し、この除去部分と残る絶縁層部分上に
さらに絶縁層形成を行ってから、この絶縁層上に拡散層
を形成する部分を残してレジスト膜を形成して前記絶縁
層に対しエッチング処理を施したのち、拡散層を形成す
るための不純物ドープを行うことを特徴とする半導体装
置の製造方法。
1. A method of manufacturing a semiconductor device, wherein a diffusion layer having different impurity concentrations is formed on a surface of a semiconductor substrate, for forming a diffusion layer having a relatively high impurity concentration after forming an insulating layer on the surface of the semiconductor substrate. Part of the insulating layer is removed, and an insulating layer is further formed on the removed part and the remaining insulating layer part, and then the resist film is formed on the insulating layer leaving a part to form a diffusion layer. A method for manufacturing a semiconductor device, which comprises forming and etching the insulating layer, and then performing impurity doping for forming a diffusion layer.
【請求項2】 エッチング処理を不純物濃度の高い拡散
層を形成するための部分上の絶縁層が完全に除去される
まで行う請求項1記載の半導体装置の製造方法。
2. The method of manufacturing a semiconductor device according to claim 1, wherein the etching process is performed until the insulating layer on the portion for forming the diffusion layer having a high impurity concentration is completely removed.
JP31543292A 1992-11-25 1992-11-25 Manufacture of semiconductor device Pending JPH06163450A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP31543292A JPH06163450A (en) 1992-11-25 1992-11-25 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP31543292A JPH06163450A (en) 1992-11-25 1992-11-25 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH06163450A true JPH06163450A (en) 1994-06-10

Family

ID=18065307

Family Applications (1)

Application Number Title Priority Date Filing Date
JP31543292A Pending JPH06163450A (en) 1992-11-25 1992-11-25 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH06163450A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017069455A (en) * 2015-09-30 2017-04-06 ラピスセミコンダクタ株式会社 Semiconductor device manufacturing method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017069455A (en) * 2015-09-30 2017-04-06 ラピスセミコンダクタ株式会社 Semiconductor device manufacturing method

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