JPH05335407A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH05335407A
JPH05335407A JP14061592A JP14061592A JPH05335407A JP H05335407 A JPH05335407 A JP H05335407A JP 14061592 A JP14061592 A JP 14061592A JP 14061592 A JP14061592 A JP 14061592A JP H05335407 A JPH05335407 A JP H05335407A
Authority
JP
Japan
Prior art keywords
element isolation
isolation region
oxide film
forming
diffusion layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14061592A
Other languages
Japanese (ja)
Inventor
Hiroaki Shibata
弘明 柴田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
MIYAGI OKI DENKI KK
Oki Electric Industry Co Ltd
Original Assignee
MIYAGI OKI DENKI KK
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by MIYAGI OKI DENKI KK, Oki Electric Industry Co Ltd filed Critical MIYAGI OKI DENKI KK
Priority to JP14061592A priority Critical patent/JPH05335407A/en
Publication of JPH05335407A publication Critical patent/JPH05335407A/en
Pending legal-status Critical Current

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  • Local Oxidation Of Silicon (AREA)
  • Element Separation (AREA)

Abstract

PURPOSE:To prevent the increase of junction leak between an adjacent diffusion layer (the source-drain of a transistor in general) and a substrate which leak is to be caused by crystal defect generated under bird's beaks in an element isolation region formed by an LOCOS method, in relation to a forming method of an element isolation region in a semiconductor device. CONSTITUTION:Firstly an element isolation region 15 is formed so as to be smaller than the final size. Next, thereon, an oxide film 19 is formed, and the oxide film 19 on the element forming regions 20, 21 are eliminated, thereby forming the element isolation region having the final size C.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】この発明は、半導体装置における
素子分離領域の形成方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming an element isolation region in a semiconductor device.

【0002】[0002]

【従来の技術】MIS(Metal Insulato
r Semiconductor)型半導体集積回路装
置における素子形成領域間の分離方法として、近年、局
部的酸化法が多用されている。この方法は、LOCOS
(Local Oxidation of Silic
on)法と呼ばれ、絶縁膜として選択的に厚い酸化シリ
コン膜を形成することで、半導体基板を複数部分に絶縁
分離し、分離された部分を素子形成領域として用いる。
さらに、分離領域に反転防止層として、不純物をドープ
する方法も併用され、素子分離が行われている。
2. Description of the Related Art MIS (Metal Insulator)
In recent years, the local oxidation method has been widely used as a method for separating element formation regions in an r Semiconductor (semiconductor) type semiconductor integrated circuit device. This method is called LOCOS
(Local Oxidation of Silic
On) method, by selectively forming a thick silicon oxide film as an insulating film, the semiconductor substrate is insulated and separated into a plurality of parts, and the separated parts are used as element formation regions.
Further, a method of doping impurities in the isolation region as an inversion prevention layer is also used in combination for element isolation.

【0003】図2は、この従来の素子分離領域の形成方
法の一例を示すものである。
FIG. 2 shows an example of this conventional method for forming an element isolation region.

【0004】まず、図2(a)に示すように、半導体基
板1上に酸化膜2および窒化膜3を形成する。次に、図
2(b)に示すように、素子分離領域となるべき部分の
窒化膜3をフォトリソグラフィ(以下フォトリソと略
す)・エッチング技術により除去し、その部分にのみ反
転防止用の不純物を所定の条件でインプラ(インプラン
テーション:イオン注入)技術により、反転防止用不純
物4を注入する。
First, as shown in FIG. 2A, an oxide film 2 and a nitride film 3 are formed on a semiconductor substrate 1. Next, as shown in FIG. 2B, the portion of the nitride film 3 to be the element isolation region is removed by photolithography (hereinafter abbreviated as photolithography) / etching technique, and only the portion is covered with an impurity for inversion prevention. The inversion preventing impurity 4 is implanted under a predetermined condition by an implantation (implantation: ion implantation) technique.

【0005】次に図2(b)のように、窒化膜3を除去
した部分を酸化し、図2(c)に示すように、素子分離
用酸化膜5を形成する。次に、図2(d)に示すよう
に、酸化膜2および窒化膜3を除去し、素子形成領域6
ならびに7の分離を完了する。
Next, as shown in FIG. 2B, the portion from which the nitride film 3 has been removed is oxidized to form an element isolation oxide film 5 as shown in FIG. 2C. Next, as shown in FIG. 2D, the oxide film 2 and the nitride film 3 are removed, and the element formation region 6 is formed.
And complete the separation of 7.

【0006】[0006]

【発明が解決しようとする課題】しかしながら、前記従
来技術では、図3(a)に示すように、素子分離領域5
のエッヂにあたるバーズビーク5aの下部には、素子分
離形成時のストレスにより結晶欠陥8が生じる。さら
に、一般的に素子分離形成後に形成される素子用電極
(MISトランジスタのソース.ドレイン電極)として
の不純物拡散層図3(b)の9のエッヂにおいて、先に
述べたバーズビーク5a下部の結晶欠陥が原因で、拡散
層9と基板1との接合リークを増大させるという素子動
作を妨げる問題が生じやすかった。
However, in the above-mentioned conventional technique, as shown in FIG.
In the lower part of the bird's beak 5a, which is the edge of the above, a crystal defect 8 occurs due to the stress at the time of element isolation formation. Further, in general, the impurity diffusion layer as an element electrode (source and drain electrodes of the MIS transistor) formed after element isolation formation, in the edge 9 of FIG. 3B, the crystal defect under the bird's beak 5a described above. Therefore, there is a tendency that a problem that increases the junction leak between the diffusion layer 9 and the substrate 1 and hinders the device operation occurs.

【0007】この発明は、以上述べた素子分離形成時に
発生する結晶欠陥を素子分離領域内に取り込み、つま
り、素子電極用拡散層のエッヂに位置しないように形成
し、拡散層と基板との接合リークをできるだけ低減する
ことを目的とする。
According to the present invention, the crystal defects generated during the element isolation formation described above are taken into the element isolation region, that is, they are formed so as not to be located at the edge of the element electrode diffusion layer, and the diffusion layer and the substrate are bonded together. The purpose is to reduce leakage as much as possible.

【0008】[0008]

【課題を解決するための手段】前記目的達成のためこの
発明では、従来からの素子分離技術LOCOS法によ
り、目標の素子分離幅より小さめの素子分離領域を形成
した後、全面にCVD(化学的気相成長)法により酸化
膜を形成し、フォトリソ技術およびウェットエッチング
技術によりCVD酸化膜を目標の素子分離幅になるよう
に、パターニングし、その後に素子領域(アクティブ領
域)に素子電極用の拡散層をインプラ技術および拡散技
術により形成するようにした。このことより、LOCO
S法で形成されたバーズビーク下部の結晶欠陥が、先に
述べた素子分離幅の目標寸法より小さくした分拡散層の
エッヂより分離領域内に取り込まれ、実質的に拡散層エ
ッヂでの基板に対する接合リークが低減される。
In order to achieve the above-mentioned object, according to the present invention, an element isolation region smaller than a target element isolation width is formed by a conventional element isolation technique LOCOS method, and then CVD (Chemical An oxide film is formed by the vapor phase epitaxy method, and the CVD oxide film is patterned by the photolithography technique and the wet etching technique so as to have the target element isolation width, and then diffused for the element electrode in the element region (active region). The layers were formed by the implantation technique and the diffusion technique. From this, LOCO
The crystal defects in the lower part of the bird's beak formed by the S method are taken into the isolation region from the edge of the diffusion layer, which is smaller than the target size of the element isolation width described above, and are substantially bonded to the substrate at the edge of the diffusion layer. Leakage is reduced.

【0009】[0009]

【作用】前述したように、本発明は、公知のLOCOS
法により形成されたバーズビーク下部の結晶欠陥を最終
的に形成した素子分離領域内に取り込むため、素子電極
用拡散層内又は、エッヂ部に結晶欠陥が存在せず結晶欠
陥が原因による素子電極用拡散層と半導体基板との接合
リークがなくなる。
As described above, the present invention is based on the known LOCOS.
Since the crystal defects under the bird's beak formed by the method are taken into the finally formed element isolation region, there is no crystal defect in the element electrode diffusion layer or the edge part, and the element electrode diffusion due to the crystal defect is caused. Junction leakage between the layer and the semiconductor substrate is eliminated.

【0010】[0010]

【実施例】以下この発明の一実施例を図1を参照して説
明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIG.

【0011】まず、図1(a)に示すように、半導体基
板11上に酸化膜12および窒化膜13を従来同様順次
形成した後、図1(b)に示すように、素子分離領域と
なるべき部分の窒化膜13を公知のフォトリソ(フォト
リソグラフィ)・エッチング技術により除去する。この
時、窒化膜13の除去幅Aは、仕上り素子分離幅が目標
寸法Cより小さくなるようにする。
First, as shown in FIG. 1A, an oxide film 12 and a nitride film 13 are sequentially formed on a semiconductor substrate 11 in the same manner as in the prior art, and then, as shown in FIG. 1B, an element isolation region is formed. The nitride film 13 at the desired portion is removed by a known photolithography (photolithography) etching technique. At this time, the removal width A of the nitride film 13 is such that the finished element isolation width is smaller than the target dimension C.

【0012】即ち除去幅A=目標寸法>A≧フォトリソ
技術での最小スリット寸法とする。次に、素子分離領域
に反転防止用の不純物14をイオン注入法を用いて注入
する。
That is, the removal width A = target dimension> A ≧ minimum slit dimension in the photolithography technique. Next, the inversion preventing impurity 14 is implanted into the element isolation region by an ion implantation method.

【0013】続いて、図1(c)に示すように、窒化膜
13を除去した部分の酸化膜12をさらに酸化して成長
させ、素子分離用酸化膜15を形成する。この時、素子
分離用酸化膜15のエッヂにあたるバーズビーク15a
の下部の半導体基板11には、結晶欠陥層16が形成さ
れる。
Subsequently, as shown in FIG. 1C, the oxide film 12 in the portion where the nitride film 13 has been removed is further oxidized and grown to form an element isolation oxide film 15. At this time, the bird's beak 15a corresponding to the edge of the element isolation oxide film 15 is formed.
A crystal defect layer 16 is formed on the semiconductor substrate 11 below the substrate.

【0014】次に、図1(d)に示すように、窒化膜1
3および酸化膜12をウェットエッチング技術により、
除去し、素子形成領域(アクティブ領域)17と18を
形成し、公知の技術LOCOS(Local Oxid
ation of Silicon)法による素子分離
が完了する。ただし、この時形成される素子分離領域幅
Bは、前述のパターンの幅Aにより、目標寸法Cより小
さく形成される。
Next, as shown in FIG. 1D, the nitride film 1
3 and oxide film 12 by wet etching technology
By removing, element formation regions (active regions) 17 and 18 are formed, and the well-known technique LOCOS (Local Oxid) is formed.
device isolation by the cation of silicon) method is completed. However, the element isolation region width B formed at this time is formed smaller than the target dimension C due to the above-described pattern width A.

【0015】次に、図1(e)に示すように、公知のC
VD法により酸化膜19を形成する。
Next, as shown in FIG. 1 (e), a known C
The oxide film 19 is formed by the VD method.

【0016】続いて、図1(f)に示すように、公知の
フォトリソ・ウェットエッチング技術により、CVD酸
化膜19の素子形成領域となる部分を除去する。これに
より、最終的な素子形成領域20,21が形成される。
Subsequently, as shown in FIG. 1F, a portion of the CVD oxide film 19 which will be an element forming region is removed by a known photolithography / wet etching technique. As a result, the final element formation regions 20 and 21 are formed.

【0017】この時、図1(g)に示すように、最終的
な素子分離領域の幅Cは目標寸法になるよう形成する。
ここで、本実施例による素子分離形成が終了する。
At this time, as shown in FIG. 1G, the width C of the final element isolation region is formed to have a target dimension.
Here, the element isolation formation according to the present embodiment is completed.

【0018】さらに、一般的に素子分離形成後に形成さ
れる素子用電極(MISトランジスタのソース.ドレイ
ン電極)としての不純物拡散層22をCVD酸化膜19
をマスクとして、インプラ技術および拡散アニール技術
により形成する。
Further, the CVD oxide film 19 is provided with an impurity diffusion layer 22 as an element electrode (source and drain electrodes of a MIS transistor) which is generally formed after element isolation is formed.
Is used as a mask by an implantation technique and a diffusion annealing technique.

【0019】この結果、先に形成されたバーズビーク1
5a下部の結晶欠陥16は、素子分離領域内に取り込ま
れており、素子電極用拡散層22内又は、エッヂ部に位
置しないため、従来技術で発生していた、結晶欠陥16
が原因による拡散層22と基板11との接合リークはな
くなる。
As a result, the previously formed bird's beak 1
The crystal defect 16 under 5a is taken into the element isolation region and is not located in the element electrode diffusion layer 22 or in the edge portion.
The junction leak between the diffusion layer 22 and the substrate 11 due to the phenomenon is eliminated.

【0020】[0020]

【発明の効果】以上詳細に説明したように、この発明に
よれば、公知のLOCOS法により形成されたバーズビ
ーク下部の結晶欠陥を最終的に形成した素子分離領域内
に取り込むようにしたので、素子電極用拡散層内又は、
エッヂ部に結晶欠陥が存在しない。従って、結晶欠陥が
原因による素子電極用拡散層と半導体基板との接合リー
クがなくなるので、安定した素子動作が得られる。
As described above in detail, according to the present invention, the crystal defects under the bird's beak formed by the known LOCOS method are taken into the finally formed element isolation region. In the electrode diffusion layer, or
There is no crystal defect in the edge part. Therefore, a junction leak between the element electrode diffusion layer and the semiconductor substrate due to the crystal defect is eliminated, and stable element operation can be obtained.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の実施例FIG. 1 Example of the present invention

【図2】従来例FIG. 2 Conventional example

【図3】問題点説明図[Figure 3] Problem explanatory diagram

【符号の説明】[Explanation of symbols]

11 半導体基板 12 酸化膜 13 窒化膜 15 素子分離用酸化膜 16 結晶欠陥 17,18 素子形成領域 19 CVD酸化膜 20,21 最終的な素子形成領域 11 semiconductor substrate 12 oxide film 13 nitride film 15 element isolation oxide film 16 crystal defect 17,18 element formation region 19 CVD oxide film 20, 21 final element formation region

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 (a)半導体基板上に、仕上がり目標寸
法より狭い幅の素子分離領域を形成する工程、 (b)前項で形成された構造の上に、絶縁膜を形成する
工程、 (c)素子形成領域となる部分の前記絶縁膜を除去し、
仕上がり寸法に成るよう素子分離領域を形成する工程、 (d)前記工程で残った前記絶縁膜をマスクにして、素
子形成領域に不純物を注入して拡散層を形成する工程、 以上の工程を含むことを特徴とする半導体装置の製造方
法。
1. A process of forming an element isolation region having a width narrower than a target finish dimension on a semiconductor substrate, a process of forming an insulating film on the structure formed in the preceding paragraph, and a process of forming an insulating film. ) Removing the insulating film in the portion to be the element formation region,
And (d) a step of forming a diffusion layer by injecting impurities into the element formation region using the insulating film remaining in the step as a mask, A method of manufacturing a semiconductor device, comprising:
JP14061592A 1992-06-01 1992-06-01 Manufacture of semiconductor device Pending JPH05335407A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14061592A JPH05335407A (en) 1992-06-01 1992-06-01 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14061592A JPH05335407A (en) 1992-06-01 1992-06-01 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH05335407A true JPH05335407A (en) 1993-12-17

Family

ID=15272832

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14061592A Pending JPH05335407A (en) 1992-06-01 1992-06-01 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH05335407A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6281533B1 (en) 1996-09-19 2001-08-28 Kabushiki Kaisha Toshiba Solid state imaging apparatus, and video system using such solid state imaging apparatus
JP2013247300A (en) * 2012-05-28 2013-12-09 Canon Inc Semiconductor device, semiconductor device manufacturing method and liquid discharge device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6281533B1 (en) 1996-09-19 2001-08-28 Kabushiki Kaisha Toshiba Solid state imaging apparatus, and video system using such solid state imaging apparatus
US6528342B2 (en) 1996-09-19 2003-03-04 Kabushiki Kaisha Toshiba Solid state imaging apparatus, method of manufacturing the same and video system using such solid state imaging apparatus
JP2013247300A (en) * 2012-05-28 2013-12-09 Canon Inc Semiconductor device, semiconductor device manufacturing method and liquid discharge device

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