JPH05211230A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH05211230A JPH05211230A JP31590291A JP31590291A JPH05211230A JP H05211230 A JPH05211230 A JP H05211230A JP 31590291 A JP31590291 A JP 31590291A JP 31590291 A JP31590291 A JP 31590291A JP H05211230 A JPH05211230 A JP H05211230A
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- resist
- film
- locos
- silicon substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 7
- 238000004519 manufacturing process Methods 0.000 title claims description 4
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 238000000034 method Methods 0.000 claims abstract description 8
- 238000002955 isolation Methods 0.000 claims description 10
- 238000005530 etching Methods 0.000 claims description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 11
- 229910052710 silicon Inorganic materials 0.000 abstract description 11
- 239000010703 silicon Substances 0.000 abstract description 11
- 239000013078 crystal Substances 0.000 abstract description 7
- 230000003647 oxidation Effects 0.000 abstract description 4
- 238000007254 oxidation reaction Methods 0.000 abstract description 4
- 230000007547 defect Effects 0.000 abstract description 3
- 210000003323 beak Anatomy 0.000 abstract 1
- 230000006866 deterioration Effects 0.000 abstract 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 241000293849 Cordylanthus Species 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
Landscapes
- Element Separation (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は半導体集積回路の素子間
分離構造の製造方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing an element isolation structure for a semiconductor integrated circuit.
【0002】[0002]
【従来の技術】従来の選択酸化法によるフィールド酸化
膜(LOCOS膜)を用いた素子間分離法について、図
2(a)〜(e)を参照して説明する。2. Description of the Related Art A conventional element isolation method using a field oxide film (LOCOS film) by a selective oxidation method will be described with reference to FIGS.
【0003】はじめに図2(a)に示すように、N型シ
リコン基板1を950℃で熱酸化して厚さ50nmの酸
化膜2を形成する。First, as shown in FIG. 2A, an N-type silicon substrate 1 is thermally oxidized at 950 ° C. to form an oxide film 2 having a thickness of 50 nm.
【0004】つぎに図2(b)に示すように、レジスト
4をマスクとして11B+ を100keVで1.0×10
13atoms/cm2 イオン注入してチャネルストッパ
3を形成する。Next, as shown in FIG. 2B, 11 B + is 1.0 × 10 at 100 keV using the resist 4 as a mask.
A channel stopper 3 is formed by ion implantation of 13 atoms / cm 2 .
【0005】つぎに図2(c)に示すように、厚さ12
0nmの窒化シリコン膜9を堆積したのちレジスト(図
示せず)をマスクとしてエッチングする。Next, as shown in FIG. 2C, the thickness 12
After depositing a 0 nm silicon nitride film 9, etching is performed using a resist (not shown) as a mask.
【0006】つぎに図2(d)に示すように、980℃
で熱酸化して厚さ100nmのLOCOS膜8を形成す
る。Next, as shown in FIG. 2D, 980 ° C.
Then, it is thermally oxidized to form a LOCOS film 8 having a thickness of 100 nm.
【0007】つぎに図2(e)に示すように、窒化シリ
コン膜9をエッチングすることにより、シリコン基板1
表面の活性領域がLOCOS膜8で分離される。Next, as shown in FIG. 2E, the silicon substrate 1 is etched by etching the silicon nitride film 9.
The active region on the surface is separated by the LOCOS film 8.
【0008】[0008]
【発明が解決しようとする課題】選択酸化法によって形
成したLOCOS膜による素子間分離法では、シリコン
基板表面に局所的に厚いLOCOS膜を形成する。LO
COS膜の端(以下バーズビークと記す)近傍のシリコ
ン基板に応力が加わり、結晶欠陥および結晶転位が発生
してリーク電流が増大するという問題があった。In the element isolation method using the LOCOS film formed by the selective oxidation method, a thick LOCOS film is locally formed on the surface of the silicon substrate. LO
There is a problem that stress is applied to the silicon substrate near the edge of the COS film (hereinafter referred to as bird's beak), crystal defects and crystal dislocations occur, and leak current increases.
【0009】また素子を形成する領域とLOCOS膜の
形成された分離帯との間に段差があるので、素子に接続
する金属配線のステップカバレッジが悪いという問題が
あった。Further, since there is a step between the region where the element is formed and the separation band where the LOCOS film is formed, there is a problem that the step coverage of the metal wiring connected to the element is poor.
【0010】[0010]
【課題を解決するための手段】本発明の半導体装置の製
造方法は、半導体基板の一主面に素子間分離用の絶縁膜
を形成してから選択エッチングする工程と、全面にエピ
タキシャル層を成長させる工程と、全面にレジストを塗
布してからエッチバックして平坦化する工程とを含むも
のである。According to a method of manufacturing a semiconductor device of the present invention, a step of forming an insulating film for element isolation on a main surface of a semiconductor substrate and then performing selective etching, and growing an epitaxial layer on the entire surface. And a step of applying a resist on the entire surface and then etching back to flatten it.
【0011】[0011]
【実施例】本発明の一実施例について、図1(a)〜
(g)を参照して説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to FIGS.
This will be described with reference to (g).
【0012】はじめに図1(a)に示すように、N型シ
リコン基板1を980℃で熱酸化して厚さ500nmの
酸化膜1を形成する。First, as shown in FIG. 1A, the N-type silicon substrate 1 is thermally oxidized at 980 ° C. to form an oxide film 1 having a thickness of 500 nm.
【0013】つぎに図1(b)に示すように、レジスト
(図示せず)をマスクとして酸化膜2をエッチングした
のち再び950℃で熱酸化して厚さ40nmの酸化膜2
aを形成する。この酸化膜2aはイオン注入によるシリ
コン基板1の表面損傷を抑えるものである。Next, as shown in FIG. 1B, the oxide film 2 is etched by using a resist (not shown) as a mask, and then thermally oxidized again at 950 ° C. to form the oxide film 2 having a thickness of 40 nm.
a is formed. The oxide film 2a suppresses surface damage of the silicon substrate 1 due to ion implantation.
【0014】つぎに酸化膜2をマスクとして11B+ を1
00keVで1.2×1013atoms/cm2 イオン
注入してP+ 型拡散層からなるチャネルストッパ3を形
成する。Next, using the oxide film 2 as a mask, 1 1 of 11 B + is added.
1.2 × 10 13 atoms / cm 2 ions are implanted at 00 keV to form a channel stopper 3 made of a P + type diffusion layer.
【0015】つぎに図1(c)に示すように、酸化膜2
を全面除去したのち980℃で熱酸化して厚さ1000
nmの酸化膜2bを形成する。Next, as shown in FIG. 1C, the oxide film 2
After removing the entire surface, it is thermally oxidized at 980 ° C to a thickness of 1000.
An oxide film 2b having a thickness of 2 nm is formed.
【0016】つぎに図1(d)に示すように、レジスト
4をマスクとして酸化膜2bをエッチングする。Next, as shown in FIG. 1D, the oxide film 2b is etched using the resist 4 as a mask.
【0017】つぎに図1(e)に示すように、レジスト
4を除去してCVD法により厚さ1.5μmのN型シリ
コンエピタキシャル層5を成長させたのちアニールして
単結晶化する。Next, as shown in FIG. 1 (e), the resist 4 is removed, and an N-type silicon epitaxial layer 5 having a thickness of 1.5 μm is grown by the CVD method and then annealed to single crystal.
【0018】つぎに図1(f)に示すように、レジスト
4aを塗布する。Next, as shown in FIG. 1F, a resist 4a is applied.
【0019】つぎに図1(g)に示すように、エッチバ
ック法により酸化膜2bからなる分離領域6で囲まれた
活性領域7が形成される。Next, as shown in FIG. 1G, the active region 7 surrounded by the isolation region 6 made of the oxide film 2b is formed by the etch back method.
【0020】本実施例で用いたN型シリコン基板の代り
に、N型エピタキシャル層、P型シリコン基板、P型エ
ピタキシャル層のいずれかを用いても同様の効果を得る
ことができる。The same effect can be obtained by using any one of an N type epitaxial layer, a P type silicon substrate and a P type epitaxial layer in place of the N type silicon substrate used in this embodiment.
【0021】[0021]
【発明の効果】素子間分離用の絶縁膜を形成し、エピタ
キシャル層を成長させたのちエッチバックして平坦化す
る。EFFECTS OF THE INVENTION An insulating film for element isolation is formed, an epitaxial layer is grown, and then etched back to be flattened.
【0022】その結果、LOCOS分離法に比べて、バ
ーズビークがなく半導体基板への応力がなくなる。従
来、応力によって生じていた結晶欠陥および結晶転位に
よるリーク電流の増大を防ぐことができる。As a result, compared to the LOCOS separation method, there is no bird's beak and stress on the semiconductor substrate is eliminated. It is possible to prevent an increase in leak current due to crystal defects and crystal dislocation, which has been conventionally caused by stress.
【0023】さらにエッチバック法により平坦化するの
で、素子形成用の活性領域と素子間分離用の絶縁膜との
段差が解消する。素子に接続する金属配線のステップカ
バレッジが従来に比べて著しく改善された。Further, since the surface is flattened by the etch back method, the step between the active region for element formation and the insulating film for element isolation is eliminated. The step coverage of the metal wiring connected to the device is significantly improved as compared with the conventional case.
【図1】本発明の一実施例を工程順に示す断面図であ
る。FIG. 1 is a sectional view showing an embodiment of the present invention in the order of steps.
【図2】従来の選択酸化法による素子間分離を示す断面
図である。FIG. 2 is a cross-sectional view showing isolation between elements by a conventional selective oxidation method.
1 N型シリコン基板 2,2a,2b 酸化膜 3 チャネルストッパ 4,4a レジスト 5 エピタキシャル層 6 分離領域 7 活性領域 8 LOCOS膜 9 窒化シリコン膜 1 N-type silicon substrate 2, 2a, 2b oxide film 3 channel stopper 4, 4a resist 5 epitaxial layer 6 isolation region 7 active region 8 LOCOS film 9 silicon nitride film
Claims (1)
縁膜を形成してから選択エッチングする工程と、全面に
エピタキシャル層を成長させる工程と、全面にレジスト
を塗布してからエッチバックして平坦化する工程とを含
む半導体装置の製造方法。1. A step of forming an insulating film for element isolation on a main surface of a semiconductor substrate and then performing selective etching, a step of growing an epitaxial layer on the entire surface, and a step of applying a resist on the entire surface and then etching back. And a method of manufacturing a semiconductor device, the method including the step of planarizing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31590291A JPH05211230A (en) | 1991-11-29 | 1991-11-29 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31590291A JPH05211230A (en) | 1991-11-29 | 1991-11-29 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05211230A true JPH05211230A (en) | 1993-08-20 |
Family
ID=18070986
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP31590291A Pending JPH05211230A (en) | 1991-11-29 | 1991-11-29 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05211230A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004266291A (en) * | 2004-05-06 | 2004-09-24 | Toshiba Corp | Semiconductor device |
| US6989316B2 (en) | 1999-06-30 | 2006-01-24 | Kabushiki Kaisha Toshiba | Semiconductor device and method for manufacturing |
-
1991
- 1991-11-29 JP JP31590291A patent/JPH05211230A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6989316B2 (en) | 1999-06-30 | 2006-01-24 | Kabushiki Kaisha Toshiba | Semiconductor device and method for manufacturing |
| US7772671B2 (en) | 1999-06-30 | 2010-08-10 | Kabushiki Kaisha Toshiba | Semiconductor device having an element isolating insulating film |
| JP2004266291A (en) * | 2004-05-06 | 2004-09-24 | Toshiba Corp | Semiconductor device |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 19991109 |