JPH04269848A - Formation method of element isolation region at semiconductor device - Google Patents
Formation method of element isolation region at semiconductor deviceInfo
- Publication number
- JPH04269848A JPH04269848A JP3257216A JP25721691A JPH04269848A JP H04269848 A JPH04269848 A JP H04269848A JP 3257216 A JP3257216 A JP 3257216A JP 25721691 A JP25721691 A JP 25721691A JP H04269848 A JPH04269848 A JP H04269848A
- Authority
- JP
- Japan
- Prior art keywords
- isolation region
- element isolation
- forming
- insulating film
- polycrystalline silicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 41
- 238000002955 isolation Methods 0.000 title claims description 69
- 239000004065 semiconductor Substances 0.000 title claims description 23
- 230000015572 biosynthetic process Effects 0.000 title abstract description 4
- 150000004767 nitrides Chemical class 0.000 claims abstract description 43
- 239000000758 substrate Substances 0.000 claims abstract description 43
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 15
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 15
- 239000010703 silicon Substances 0.000 claims abstract description 15
- 230000001590 oxidative effect Effects 0.000 claims abstract description 11
- 238000005498 polishing Methods 0.000 claims abstract description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 39
- 239000012535 impurity Substances 0.000 claims description 5
- 241000293849 Cordylanthus Species 0.000 abstract description 8
- 230000007547 defect Effects 0.000 abstract description 6
- 210000003323 beak Anatomy 0.000 abstract 1
- 238000004519 manufacturing process Methods 0.000 description 13
- 238000010586 diagram Methods 0.000 description 12
- 230000003647 oxidation Effects 0.000 description 9
- 238000007254 oxidation reaction Methods 0.000 description 9
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 238000009279 wet oxidation reaction Methods 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76227—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials the dielectric materials being obtained by full chemical transformation of non-dielectric materials, such as polycristalline silicon, metals
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/32—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers using masks
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
- Local Oxidation Of Silicon (AREA)
Abstract
Description
【０００１】0001
【産業上の利用分野】本発明は半導体装置の製造方法に
関するもので、特に素子間の分離領域を形成する方法に
関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming isolation regions between elements.
【０００２】0002
【従来の技術】半導体装置の適切な動作のために、半導
体基板に形成された各素子領域を絶縁分離する必要があ
る。現在、一般的な素子分離領域の形成方法としては、
選択酸化法（ＬＯＣＯＳ）によってフィールド酸化膜を
形成する方法がある。2. Description of the Related Art For proper operation of a semiconductor device, it is necessary to insulate and separate each element region formed on a semiconductor substrate. Currently, the common method for forming element isolation regions is as follows:
There is a method of forming a field oxide film by a selective oxidation method (LOCOS).
【０００３】図１３は従来技術による素子分離領域の断
面図であって、選択酸化法によって素子分離領域にフィ
ールド酸化膜８を形成した後の断面図である。通常の選
択酸化法は、第１導電形のシリコン基板２の上に窒化膜
６を形成した後に、素子分離領域を形成する所定の領域
上にある窒化膜６を除去する。その後に酸化工程を実施
して基板が露出した領域にのみ局部的に厚いフィールド
酸化膜８を形成することによって素子分離領域を完成す
る。即ち、基板２の窒化膜６で被覆された部分は酸化膜
が形成されずに、窒化膜６で被覆されていない部分のみ
、基板２を消耗しながらフィールド酸化膜８が形成され
る。FIG. 13 is a sectional view of an element isolation region according to the prior art, and is a sectional view after a field oxide film 8 is formed in the element isolation region by selective oxidation. In the usual selective oxidation method, after a nitride film 6 is formed on a silicon substrate 2 of the first conductivity type, the nitride film 6 on a predetermined region where an element isolation region is to be formed is removed. Thereafter, an oxidation process is performed to locally form a thick field oxide film 8 only in the exposed area of the substrate, thereby completing the element isolation region. That is, no oxide film is formed on the portions of the substrate 2 covered with the nitride film 6, and the field oxide film 8 is formed only on the portions not covered with the nitride film 6, while the substrate 2 is consumed.
【０００４】このとき、酸化膜の成長による嵩の膨脹に
因って窒化膜とシリコン基板との境界面で大幅にストレ
スが生じ、これに因る欠陥（ｄｅｆｅｃｔ）１２が発生
する。
このような欠陥は素子分離の特性を低下させる要因にな
る。[0004] At this time, due to the bulk expansion due to the growth of the oxide film, significant stress is generated at the interface between the nitride film and the silicon substrate, resulting in defects 12. Such defects become a factor that deteriorates element isolation characteristics.
【０００５】そこで、上記の欠陥を減少させるために、
窒化膜６を形成する前に基板２の上面にバッファー酸化
膜４を形成する方法がとられている。このようにすると
、バッファー酸化膜４が、フィールド酸化膜８の形成時
に窒化膜６と基板２との間で緩衝役を果たし、基板２に
発生するストレスを減少させることができる。しかし、
このバッファー酸化膜４は選択酸化時に横方向にも酸化
が生じてしまい、素子領域にフィールド酸化膜８が伸張
されて形成されてしまうことによって素子分離領域が大
きくなるバーズビーク（ｂｉｒｄ’ｓ ｂｅａｋ）１０
を発生する。即ち、選択酸化時に酸素元素がバッファー
酸化膜４を通じて窒化膜６の下面にも侵入して行き、窒
化膜６の下面においても、窒化膜６を持ち上げるように
バーズビーク（ｂｉｒｄ’ｓｂｅａｋ）形態で酸化膜が
形成される。その結果、素子分離領域の面積が増加し、
窒化膜６の下面におけるバッファー酸化膜４の嵩の膨脹
に因って大きなストレスが発生して大幅に欠陥を誘発さ
せてしまい、サブミクロンでのトランジスタの微細化に
大きな支障を与える。[0005] Therefore, in order to reduce the above defects,
A method is used in which a buffer oxide film 4 is formed on the upper surface of the substrate 2 before forming the nitride film 6. In this way, the buffer oxide film 4 acts as a buffer between the nitride film 6 and the substrate 2 during the formation of the field oxide film 8, and the stress generated in the substrate 2 can be reduced. but,
This buffer oxide film 4 is also oxidized in the lateral direction during selective oxidation, and the field oxide film 8 is extended and formed in the element region, resulting in a bird's beak 10 in which the element isolation region becomes larger.
occurs. That is, during selective oxidation, the oxygen element also enters the lower surface of the nitride film 6 through the buffer oxide film 4, and the oxide film forms a bird's beak shape on the lower surface of the nitride film 6 so as to lift the nitride film 6. is formed. As a result, the area of the element isolation region increases,
Due to the expansion of the buffer oxide film 4 on the lower surface of the nitride film 6, a large stress is generated, which significantly induces defects, which greatly hinders the miniaturization of transistors at submicron scale.
【０００６】このような問題点を改善するために、バッ
ファー酸化膜と窒化膜との間に多結晶シリコン層を挿入
して多結晶シリコン層を酸化させる方法がさらに提案さ
れた。即ち、基板の代りに多結晶シリコン層を酸化させ
ることによって、基板のストレスとバーズビークが減少
するようにした。しかし、この方法でもやはり多結晶シ
リコン層の酸化によるバーズビークを防げないという問
題点があった。In order to solve these problems, a method has been proposed in which a polycrystalline silicon layer is inserted between a buffer oxide film and a nitride film to oxidize the polycrystalline silicon layer. That is, by oxidizing the polycrystalline silicon layer instead of the substrate, stress and bird's beak on the substrate are reduced. However, this method still has the problem that bird's beaks due to oxidation of the polycrystalline silicon layer cannot be prevented.
【０００７】[0007]
【発明が解決しようとする課題】したがって、本発明の
目的は半導体装置の素子分離領域の形成時におけるバー
ズビークおよび基板へのストレスが抑制された素子分離
領域の形成方法を提供することにある。SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a method for forming an isolation region of a semiconductor device in which bird's beaks and stress on a substrate are suppressed when forming an isolation region.
【０００８】[0008]
【課題を解決するための手段】上記のような目的を達成
するために本発明は、第１導電形のシリコン基板上にバ
ッファー酸化膜と窒化膜を順次に形成した後、素子分離
領域の窒化膜だけを選択的に除去してから、基板の全面
に多結晶シリコン層を窒化膜より厚膜となるように形成
した後に、ポリッシング（ｐｏｌｉｓｈｉｎｇ）によっ
て窒化膜の表面と多結晶シリコンの表面を平坦化し、そ
の後に窒化膜間に残った多結晶シリコンを酸化させて素
子分離領域を形成したことを特徴とする。[Means for Solving the Problems] In order to achieve the above objects, the present invention sequentially forms a buffer oxide film and a nitride film on a silicon substrate of a first conductivity type, and then nitrides an element isolation region. After selectively removing only the film, a polycrystalline silicon layer is formed on the entire surface of the substrate so that it is thicker than the nitride film, and then the surface of the nitride film and the surface of the polycrystalline silicon are flattened by polishing. The device isolation region is formed by oxidizing the polycrystalline silicon remaining between the nitride films.
【０００９】[0009]
【作用】このようにすることで、基板内のシリコンの消
耗がなくなり、即ち基板が酸化されずにすみ、バーズビ
ークの発生を抑制することができる。[Operation] By doing this, the silicon in the substrate is not consumed, that is, the substrate is not oxidized, and the occurrence of bird's beak can be suppressed.
【００１０】0010
【実施例】以下、本発明を添付の図面を参照して詳細に
説明する。図１は本発明による素子分離領域の断面図で
あって、所定の領域に第１導電形のチャネルストッパ（
Ｃｈａｎｎｅｌ Ｓｔｏｐｅｒ）２６が形成された第１
導電形のシリコン基板１４と、基板１４の上面に形成さ
れたバッファー酸化膜１６と、多結晶シリコンを酸化さ
せて嵩を膨脹させ、チャネルストッパ２６の上面に形成
した素子分離酸化膜２４とが示されている。DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will now be described in detail with reference to the accompanying drawings. FIG. 1 is a cross-sectional view of an element isolation region according to the present invention, in which a channel stopper of a first conductivity type (
Channel Stoper) 26 was formed.
A conductive silicon substrate 14, a buffer oxide film 16 formed on the upper surface of the substrate 14, and an element isolation oxide film 24 formed on the upper surface of a channel stopper 26 by oxidizing polycrystalline silicon to expand its volume are shown. has been done.
【００１１】図２〜図６は、図１のような素子分離領域
の製造工程図であって、図１と同じ名称に該当するもの
は同じ番号を使用している。FIGS. 2 to 6 are manufacturing process diagrams of the element isolation region as shown in FIG. 1, and the same numbers are used for the same names as in FIG. 1.
【００１２】図２で第１導電形のシリコン基板１４の上
面に１００Å〜５００Åの厚さのバッファー酸化膜１６
と１０００Å〜３０００Åの厚さの窒化膜１８を各々通
常の酸化法と化学気相蒸着法によって形成する。In FIG. 2, a buffer oxide film 16 with a thickness of 100 Å to 500 Å is formed on the upper surface of a silicon substrate 14 of the first conductivity type.
and a nitride film 18 having a thickness of 1000 Å to 3000 Å are formed by a conventional oxidation method and a chemical vapor deposition method, respectively.
【００１３】その後に、図３で光食刻工程を実施して素
子分離領域の窒化膜１８のみを選択的に除去する。そし
て、そこからチャネルストッパとして第１導電形の不純
物をイオン注入する。Thereafter, as shown in FIG. 3, a photoetching process is performed to selectively remove only the nitride film 18 in the element isolation region. From there, impurity ions of the first conductivity type are implanted as a channel stopper.
【００１４】その後に、図４で基板１４の上面に窒化膜
１８より厚い第１多結晶シリコン層２０を化学気相蒸着
法によって形成する。Thereafter, as shown in FIG. 4, a first polycrystalline silicon layer 20, which is thicker than the nitride film 18, is formed on the upper surface of the substrate 14 by chemical vapor deposition.
【００１５】その後に、図５においてのように機械的な
ポリッシング（Ｐｏｌｉｓｈｉｎｇ）方法によって窒化
膜１８の表面が露出するまで平坦化工程を実施する。Thereafter, as shown in FIG. 5, a planarization process is performed using a mechanical polishing method until the surface of the nitride film 18 is exposed.
【００１６】その後に、図６で窒化膜１８の間に残留す
る第１多結晶シリコン２２を湿式酸化法によって完全に
酸化させて素子分離酸化膜２４を形成する。Thereafter, as shown in FIG. 6, the first polycrystalline silicon 22 remaining between the nitride films 18 is completely oxidized by a wet oxidation method to form an element isolation oxide film 24.
【００１７】このとき、図３の工程でイオン注入された
不純物が基板１４内に所定の深さ拡散されることによっ
て素子分離酸化膜２４の下面には基板１４より高濃度の
チャネルストッパ２６が形成される。At this time, the impurities ion-implanted in the step of FIG. 3 are diffused to a predetermined depth into the substrate 14, so that a channel stopper 26 with a higher concentration than the substrate 14 is formed on the lower surface of the element isolation oxide film 24. be done.
【００１８】その後に、窒化膜１８を湿式食刻によって
除去することによって素子分離領域のための工程を仕上
げる。Thereafter, the nitride film 18 is removed by wet etching to complete the process for forming the isolation region.
【００１９】本発明によると、基板のシリコンを消耗せ
ずに窒化膜間の多結晶シリコンの酸化のみで素子分離酸
化膜を形成することができる。According to the present invention, an element isolation oxide film can be formed only by oxidizing the polycrystalline silicon between the nitride films without consuming the silicon of the substrate.
【００２０】図７は本発明の他の実施例による素子分離
領域の断面図であって、所定の領域に第１導電形のチャ
ネルストッパ４６が形成された第１導電形のシリコン基
板２８と、基板２８の上面に形成されたバッファー酸化
膜３０と、チャネルストッパ４６の上面に、多結晶シリ
コンを酸化させて嵩を膨脹させ、チャネルストッパ４６
の幅と略同じ第１幅及びこの第１幅より狭い第２幅で形
成された素子分離酸化膜４４とが示されている。FIG. 7 is a sectional view of an element isolation region according to another embodiment of the present invention, which includes a silicon substrate 28 of a first conductivity type in which a channel stopper 46 of a first conductivity type is formed in a predetermined region; The buffer oxide film 30 formed on the upper surface of the substrate 28 and the upper surface of the channel stopper 46 are formed by oxidizing the polycrystalline silicon to expand the volume.
An element isolation oxide film 44 is shown having a first width that is approximately the same as the width of the element isolation oxide film 44 and a second width that is narrower than the first width.
【００２１】図８〜図１２は図７のような素子分離領域
の製造工程図であって、図７と同じ名称に該当するもの
は同じ番号を使用している。FIGS. 8 to 12 are manufacturing process diagrams of the element isolation region as shown in FIG. 7, and the same numbers are used for the same names as in FIG. 7.
【００２２】図８においては第１導電形のシリコン基板
２８の上面に通常の酸化法による１００Å〜５００Åの
厚さのバッファー酸化膜３０と、化学気相蒸着法による
５００Å〜２０００Åの厚さの第２多結晶シリコン層３
２および１０００Å〜３０００Åの厚さの窒化膜３６を
順次に形成する。In FIG. 8, a buffer oxide film 30 with a thickness of 100 Å to 500 Å is formed on the upper surface of a silicon substrate 28 of the first conductivity type by a conventional oxidation method, and a buffer oxide film 30 with a thickness of 500 Å to 2000 Å is formed by a chemical vapor deposition method. 2 polycrystalline silicon layer 3
2 and a nitride film 36 having a thickness of 1000 Å to 3000 Å are sequentially formed.
【００２３】その後に、図９で光蝕刻工程を実施して素
子分離領域の窒化膜３６を選択的に除去する。そして、
そこからチャネルストッパとして第１導電形の不純物を
イオン注入する。Thereafter, as shown in FIG. 9, a photoetching process is performed to selectively remove the nitride film 36 in the device isolation region. and,
From there, impurity ions of the first conductivity type are implanted as a channel stopper.
【００２４】その後に、図１０で基板２８の上面に窒化
膜３６より厚い第１多結晶シリコン層４０を化学気相蒸
着法によって形成する。Thereafter, as shown in FIG. 10, a first polycrystalline silicon layer 40, which is thicker than the nitride film 36, is formed on the upper surface of the substrate 28 by chemical vapor deposition.
【００２５】その後に、図１１においてのように機械的
なポリッシング方法によって窒化膜３６の表面が露出す
るまで平坦化工程を実施する。Thereafter, as shown in FIG. 11, a planarization process is performed by a mechanical polishing method until the surface of the nitride film 36 is exposed.
【００２６】その後に、図１２で窒化膜３６の間に残留
した第１多結晶シリコン４２を湿式酸化法によって完全
に酸化させて素子分離酸化膜４４を形成する。Thereafter, as shown in FIG. 12, the first polycrystalline silicon 42 remaining between the nitride films 36 is completely oxidized by wet oxidation to form an element isolation oxide film 44.
【００２７】このとき、図９の工程でイオン注入された
不純物が基板２８内に所定の深さ拡散されることによっ
て素子分離酸化膜４４の下面には基板１４より高濃度の
チャネルストッパ４６が形成される。At this time, the impurities ion-implanted in the step of FIG. 9 are diffused into the substrate 28 to a predetermined depth, so that a channel stopper 46 having a higher concentration than the substrate 14 is formed on the lower surface of the element isolation oxide film 44. be done.
【００２８】その後に、窒化膜３６と第２多結晶シリコ
ン層３２を順次に除去することによって素子分離領域の
ための工程を仕上げる。Thereafter, the nitride film 36 and the second polycrystalline silicon layer 32 are sequentially removed to complete the process for forming the element isolation region.
【００２９】図８〜図１２によって説明した本発明の他
の実施例においては、窒化膜の下面に多結晶シリコン層
を挿入することによって素子分離酸化膜の形成時の基板
のストレスが抑制されるようになっている。In another embodiment of the present invention described with reference to FIGS. 8 to 12, stress on the substrate during formation of the element isolation oxide film is suppressed by inserting a polycrystalline silicon layer on the lower surface of the nitride film. It looks like this.
【００３０】また、この実施例においては図９の工程後
に化学気相蒸着法によって第１多結晶シリコン層４０を
形成した後に平坦化工程を実施しているが、露出した第
２多結晶シリコン３２の上面のみに選択的に多第１結晶
シリコン層４２を形成することも可能である。この場合
、窒化膜の表面との平坦化工程は必要ない。Further, in this embodiment, after the step of FIG. 9, the first polycrystalline silicon layer 40 is formed by chemical vapor deposition, and then the planarization step is carried out. It is also possible to selectively form the polycrystalline silicon layer 42 only on the upper surface. In this case, a planarization step with respect to the surface of the nitride film is not necessary.
【００３１】[0031]
【発明の効果】上述のように本発明は、窒化膜の間に残
った多結晶シリコンを酸化することによって、基板内の
シリコンを消耗することなしに素子分離酸化膜を形成す
ることができる。その結果、バーズビークが最大限に抑
制された素子分離領域を形成することができる効果があ
る。また、基板が酸化されないので、基板のストレスお
よびこれに因る欠陥も大幅に抑制することができる効果
がある。As described above, according to the present invention, by oxidizing the polycrystalline silicon remaining between the nitride films, an element isolation oxide film can be formed without consuming the silicon in the substrate. As a result, it is possible to form an element isolation region in which bird's beak is suppressed to the maximum extent possible. Furthermore, since the substrate is not oxidized, stress on the substrate and defects caused by this can be significantly suppressed.
【図１】本発明の実施例による素子分離領域の断面図で
ある。FIG. 1 is a cross-sectional view of an element isolation region according to an embodiment of the present invention.
【図２】本発明の実施例による素子分離領域のバッファ
ー酸化膜と窒化膜を形成する製造工程図である。FIG. 2 is a manufacturing process diagram for forming a buffer oxide film and a nitride film in an element isolation region according to an embodiment of the present invention.
【図３】本発明の実施例による素子分離領域のチャネル
ストッパを形成する製造工程図である。FIG. 3 is a manufacturing process diagram for forming a channel stopper in an isolation region according to an embodiment of the present invention.
【図４】本発明の実施例による素子分離領域の多結晶シ
リコンを形成する製造工程図である。FIG. 4 is a manufacturing process diagram for forming polycrystalline silicon of an element isolation region according to an embodiment of the present invention.
【図５】本発明の実施例による素子分離領域の多結晶シ
リコンと窒化膜との平坦化を実施する製造工程図である
。FIG. 5 is a manufacturing process diagram for planarizing polycrystalline silicon and a nitride film in an element isolation region according to an embodiment of the present invention.
【図６】本発明の実施例による素子分離領域の素子分離
酸化膜を湿式酸化法により形成する製造工程図である。FIG. 6 is a manufacturing process diagram for forming an element isolation oxide film in an element isolation region by a wet oxidation method according to an embodiment of the present invention.
【図７】本発明の他の実施例による素子分離領域の断面
図である。FIG. 7 is a cross-sectional view of an isolation region according to another embodiment of the present invention.
【図８】本発明の他の実施例による素子分離領域のバッ
ファー酸化膜と第１多結晶シリコンと窒化膜とを形成す
る製造工程図である。FIG. 8 is a manufacturing process diagram for forming a buffer oxide film, a first polycrystalline silicon film, and a nitride film in an element isolation region according to another embodiment of the present invention.
【図９】本発明の他の実施例による素子分離領域のチャ
ネルストッパを形成する製造工程図である。FIG. 9 is a manufacturing process diagram for forming a channel stopper in an isolation region according to another embodiment of the present invention.
【図１０】本発明の他の実施例による素子分離領域の第
２多結晶シリコンを形成する製造工程図である。FIG. 10 is a manufacturing process diagram for forming a second polycrystalline silicon layer in an isolation region according to another embodiment of the present invention.
【図１１】本発明の他の実施例による素子分離領域の第
２多結晶シリコンと窒化膜との平坦化を実施する製造工
程図である。FIG. 11 is a manufacturing process diagram for planarizing the second polycrystalline silicon and nitride film in the element isolation region according to another embodiment of the present invention.
【図１２】本発明の他の実施例による素子分離領域の素
子分離酸化膜を湿式酸化法により形成する製造工程図で
ある。FIG. 12 is a manufacturing process diagram for forming an element isolation oxide film in an element isolation region by a wet oxidation method according to another embodiment of the present invention.
【図１３】従来の技術による素子分離領域の断面図であ
る。FIG. 13 is a cross-sectional view of an element isolation region according to a conventional technique.
１４……半導体基板 １６……バッファー酸化膜 ２４……素子分離酸化膜 ２６……チャネルストッパ 14...Semiconductor substrate 16...Buffer oxide film 24...Element isolation oxide film 26...Channel stopper
Claims (11)
において、第１導電形の半導体基板の上面に第１絶縁膜
と第２絶縁膜を順次に形成する第１工程と、所定の領域
上にある第２絶縁膜を除去する第２工程と、基板の全面
に第１多結晶シリコン層を形成した後に、第１多結晶シ
リコン層の表面が第２絶縁膜の表面と一致するまで平坦
化を行う第３工程と、第２絶縁膜の間に残った第１多結
晶シリコンを酸化させて素子分離酸化膜を形成する第４
工程と、第２絶縁膜を除去する第５工程とが連続的に行
なわれることを特徴とする半導体装置の素子分離領域の
形成方法。1. A method for forming an element isolation region of a semiconductor device, comprising: a first step of sequentially forming a first insulating film and a second insulating film on an upper surface of a semiconductor substrate of a first conductivity type; A second step of removing a certain second insulating film, and after forming a first polycrystalline silicon layer on the entire surface of the substrate, planarization is performed until the surface of the first polycrystalline silicon layer coincides with the surface of the second insulating film. and a fourth step of oxidizing the first polycrystalline silicon remaining between the second insulating film to form an element isolation oxide film.
1. A method for forming an element isolation region of a semiconductor device, characterized in that the step and the fifth step of removing the second insulating film are performed continuously.
載の半導体装置の素子分離領域の形成方法。2. The method of forming an element isolation region of a semiconductor device according to claim 1, wherein the first insulating film is an oxide film.
さで形成される請求項２記載の半導体装置の素子分離領
域の形成方法。3. The method for forming an isolation region of a semiconductor device according to claim 2, wherein the first insulating film is formed to have a thickness of 100 Å to 500 Å.
載の半導体装置の素子分離領域の形成方法。4. The method of forming an element isolation region of a semiconductor device according to claim 1, wherein the second insulating film is a nitride film.
の厚さで形成される請求項４記載の半導体装置の素子分
離領域の形成方法。5. The second insulating film has a thickness of 1000 Å to 3000 Å.
5. The method for forming an element isolation region of a semiconductor device according to claim 4, wherein the isolation region is formed to have a thickness of .
化膜の厚さが調節される請求項１記載の半導体装置の素
子分離領域の形成方法。6. The method of forming an element isolation region of a semiconductor device according to claim 1, wherein the thickness of the element isolation oxide film is adjusted depending on the thickness of the second insulating film.
ングによって実施される請求項１記載の半導体装置の素
子分離領域の形成方法。7. The method of forming an isolation region of a semiconductor device according to claim 1, wherein the third step of planarization is performed by mechanical polishing.
形の不純物をイオン注入してチャネルストッパを形成す
る工程をさらに実施する請求項１記載の半導体装置の素
子分離領域の形成方法。8. The method for forming an isolation region of a semiconductor device according to claim 1, further comprising performing a step of ion-implanting impurities of the first conductivity type into the entire surface of the substrate to form a channel stopper after the second step.
において、第１導電形の半導体基板の上面に第１絶縁膜
と第２多結晶シリコン層と第２絶縁膜とを順次に形成す
る第１工程と、所定の領域上にある第２絶縁膜を除去す
る第２工程と、基板の全面に第１多結晶シリコン層を形
成した後に、第１多結晶シリコン層の表面が第２絶縁膜
の表面と一致するまで平坦化を行う第３工程と、第２絶
縁膜の間に残った第１多結晶シリコンを酸化させて素子
分離酸化膜を形成する第４工程と、第２絶縁膜及び第２
多結晶シリコンを除去する第５工程とが連続的に行なわ
れることを特徴とする半導体装置の素子分離領域の形成
方法。9. A method for forming an element isolation region of a semiconductor device, wherein a first insulating film, a second polycrystalline silicon layer, and a second insulating film are sequentially formed on an upper surface of a semiconductor substrate of a first conductivity type. a second step of removing the second insulating film on a predetermined region; and a second step of removing the second insulating film on a predetermined region; and after forming the first polycrystalline silicon layer on the entire surface of the substrate, the surface of the first polycrystalline silicon layer is covered with the second insulating film. A third step of planarizing the silicon until it matches the surface; a fourth step of oxidizing the first polycrystalline silicon remaining between the second insulating film to form an element isolation oxide film; 2
1. A method for forming an isolation region of a semiconductor device, characterized in that a fifth step of removing polycrystalline silicon is performed continuously.
法において、第１導電形の半導体基板の上面に第１絶縁
膜と第２多結晶シリコン層と第２絶縁膜とを順次に形成
する第１工程と、所定の領域上にある第２絶縁膜を除去
する第２工程と、第２工程後に露出した第２多結晶シリ
コン層の上面のみに第１多結晶シリコン層を形成する第
３工程と、この第１多結晶シリコンを酸化させて素子分
離酸化膜を形成する第４工程と、第２絶縁膜及び第２多
結晶シリコンを除去する第５工程とが連続的に行なわれ
ることを特徴とする半導体装置の素子分離領域の形成方
法。10. A method for forming an element isolation region of a semiconductor device, wherein a first insulating film, a second polycrystalline silicon layer, and a second insulating film are sequentially formed on an upper surface of a semiconductor substrate of a first conductivity type. a second step of removing the second insulating film on a predetermined region; and a third step of forming a first polycrystalline silicon layer only on the upper surface of the second polycrystalline silicon layer exposed after the second step. , characterized in that a fourth step of oxidizing the first polycrystalline silicon to form an element isolation oxide film and a fifth step of removing the second insulating film and the second polycrystalline silicon are performed continuously. A method for forming an element isolation region in a semiconductor device.
２０００Åの厚さで形成される請求項９乃至１０記載の
半導体装置の素子分離領域の形成方法。11. The second polycrystalline silicon layer has a thickness of 500 Å or more.
11. The method for forming an isolation region of a semiconductor device according to claim 9, wherein the isolation region is formed to have a thickness of 2000 Å.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019910001029A KR930011460B1 (en) | 1991-01-22 | 1991-01-22 | Isolation forming method of semiconductor |
| KR1029/1991 | 1991-01-22 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04269848A true JPH04269848A (en) | 1992-09-25 |
Family
ID=19310149
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3257216A Pending JPH04269848A (en) | 1991-01-22 | 1991-09-10 | Formation method of element isolation region at semiconductor device |
Country Status (6)
| Country | Link |
|---|---|
| JP (1) | JPH04269848A (en) |
| KR (1) | KR930011460B1 (en) |
| DE (1) | DE4129665A1 (en) |
| FR (1) | FR2671910A1 (en) |
| GB (1) | GB2252201A (en) |
| IT (1) | IT1251564B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2012142560A (en) * | 2010-12-15 | 2012-07-26 | Canon Inc | Solid-state imaging device, method for manufacturing the same, and camera |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0067738A3 (en) * | 1981-05-26 | 1986-06-11 | FAIRCHILD CAMERA & INSTRUMENT CORPORATION | Method of reducing encroachment in a semiconductor device |
| US4407696A (en) * | 1982-12-27 | 1983-10-04 | Mostek Corporation | Fabrication of isolation oxidation for MOS circuit |
| US4570325A (en) * | 1983-12-16 | 1986-02-18 | Kabushiki Kaisha Toshiba | Manufacturing a field oxide region for a semiconductor device |
| JPS62290146A (en) * | 1986-06-09 | 1987-12-17 | Toshiba Corp | Manufacture of semiconductor device |
| KR880008448A (en) * | 1986-12-17 | 1988-08-31 | 강진구 | How to remove the side isolation device |
| US4818235A (en) * | 1987-02-10 | 1989-04-04 | Industry Technology Research Institute | Isolation structures for integrated circuits |
| DD268336A1 (en) * | 1987-12-30 | 1989-05-24 | Dresden Forschzentr Mikroelek | PROCESS FOR PRODUCING INSULATION AREAS |
| US4962064A (en) * | 1988-05-12 | 1990-10-09 | Advanced Micro Devices, Inc. | Method of planarization of topologies in integrated circuit structures |
-
1991
- 1991-01-22 KR KR1019910001029A patent/KR930011460B1/en not_active IP Right Cessation
- 1991-08-28 FR FR9110684A patent/FR2671910A1/en not_active Withdrawn
- 1991-09-06 DE DE4129665A patent/DE4129665A1/en not_active Ceased
- 1991-09-09 IT ITMI912383A patent/IT1251564B/en active IP Right Grant
- 1991-09-10 JP JP3257216A patent/JPH04269848A/en active Pending
- 1991-09-10 GB GB9119303A patent/GB2252201A/en not_active Withdrawn
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2012142560A (en) * | 2010-12-15 | 2012-07-26 | Canon Inc | Solid-state imaging device, method for manufacturing the same, and camera |
Also Published As
| Publication number | Publication date |
|---|---|
| ITMI912383A1 (en) | 1993-03-09 |
| FR2671910A1 (en) | 1992-07-24 |
| ITMI912383A0 (en) | 1991-09-09 |
| GB9119303D0 (en) | 1991-10-23 |
| KR930011460B1 (en) | 1993-12-08 |
| DE4129665A1 (en) | 1992-07-30 |
| IT1251564B (en) | 1995-05-17 |
| GB2252201A (en) | 1992-07-29 |
| KR920015512A (en) | 1992-08-27 |
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