GB2252201A - Method of forming an insulating region in a semiconductor device - Google Patents
Method of forming an insulating region in a semiconductor device Download PDFInfo
- Publication number
- GB2252201A GB2252201A GB9119303A GB9119303A GB2252201A GB 2252201 A GB2252201 A GB 2252201A GB 9119303 A GB9119303 A GB 9119303A GB 9119303 A GB9119303 A GB 9119303A GB 2252201 A GB2252201 A GB 2252201A
- Authority
- GB
- United Kingdom
- Prior art keywords
- layer
- insulating layer
- insulating
- process according
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 238000000034 method Methods 0.000 title claims abstract description 57
- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- 150000004767 nitrides Chemical class 0.000 claims abstract description 42
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 42
- 239000000758 substrate Substances 0.000 claims abstract description 42
- 229920005591 polysilicon Polymers 0.000 claims abstract description 29
- 238000005498 polishing Methods 0.000 claims description 5
- 230000001590 oxidative effect Effects 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 3
- 239000012535 impurity Substances 0.000 claims description 3
- 241000293849 Cordylanthus Species 0.000 abstract description 7
- 238000007254 oxidation reaction Methods 0.000 description 10
- 230000007547 defect Effects 0.000 description 9
- 230000003647 oxidation Effects 0.000 description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 238000005468 ion implantation Methods 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 238000009279 wet oxidation reaction Methods 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76227—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials the dielectric materials being obtained by full chemical transformation of non-dielectric materials, such as polycristalline silicon, metals
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/32—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers using masks
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
- Local Oxidation Of Silicon (AREA)
Abstract
In a process for forming an element insulating region 44 in a semiconductor device, a buffer oxide layer 30 is formed on a semiconductor substrate 28 of a first conductive type, and polysilicon and nitride layers 32, 36 are sequentially formed on the buffer oxide layer 30. Then, part of the nitride layer 36 formed on a predetermined element insulating region is selectively removed, and a polysilicon layer 42, of which the thickness is similar to that of the nitride layer 36, is formed between the inner side walls of the remaining nitride layer portions 36. Thereafter, the polysilicon layer 42 is oxidized, and then the remaining nitride layer 36 and polysilicon layer 32 are removed, to thereby form an insulating oxide layer 44 without affecting the substrate. Consequently, there is provided an insulating region in which bird's beak phenomenon and stress on the substrate 28 are reduced. <IMAGE>
Description
METHOD OF FORMING AN INSULATING REGION
IN A SEMICONDUCTOR DEVICE
The present invention relates to methods for fabricating semiconductor devices, and particularly to a method for forming an insulating region in a semiconductor device.
When fabricating a semiconductor device, a process for electrically insulating respective elements provided within the semiconductor device is necessarily required to allow error-free operation of the semiconductor device.
To this end, a known art of forming a field oxide layer between the elements by a local oxidation has been proposed as a way to form such an element insulating region in a semiconductor device.
Figure 1 of the accompanying diagrammatic drawings is a crosssectional view showing a known element insulating region, wherein a field oxide layer 8 is formed as an element insulating region by using a known process of local oxidation of silicon (LOCOS).
With the LOCOS technique, a nitride layer 6 is formed on a substrate 2 of a first conductive type, and thereafter, the nitride layer portion formed on a desired element insulating region is removed. Then, by performing an oxidation process, the field oxide layer 8 is locally formed to a certain thickness, only on the region where a part of the substrate 2 is exposed, so as to form the element insulating region, as shown.
By use of such an insulating process as mentioned above, the field oxide layer 8 is formed only on the region where the substrate is not covered with the nitride layer, and the field oxide layer 8 is not formed on the other region where the substrate is covered with the nitride layer, thereby causing the field oxide layer to grow in some depth on the substrate. However, such excessive expansion of the field oxide layer 8 can cause too much stress in a boundary area between the nitride layer 6 and the silicon substrate 2 so that defects 12 of the elements may be brought about. Such defects inevitably lead to degraded insulation in a semiconductor device.
As a process for improving the above defect, a buffer oxide layer 4 is formed on the substrate 2 prior to the nitride deposition. Thus, the buffer oxide layer 4 serves as a buffer between the nitride layer 6 and the silicon substrate 2 when the field oxide layer 8 is formed, so that stress of the substrate may be considerably reduced. However, since the buffer oxide layer 4 is adapted to expand from the insulating region into the element region during the local oxidation, the size of the insulating region is increased to thereby generate a so-called bird's beak phenomenon. That is, oxygen particles reach underneath the nitride layer 6 through the buffer oxide layer 4, so that the oxide layer grows in the form of a bird's beak, holding up the nitride layer 6.As a result, stress still exists due to the area expansion of the insulating region and the volume expansion of the oxide layer underneath the nitride layer, which causes defects of the device. Not only may this generate many defects, but it may give rise to problems in reducing the size of semiconductor devices in sub-micron units.
In another process to solve the foregoing problems, it has been proposed that a polycrystalline silicon layer (hereinafter referred to as polysilicon layer) is inserted between the buffer oxide layer and the nitride layer and then oxidized. In this way, the stress on the substrate and the bird's beak phenomenon can be considerably reduced by oxidizing the polysilicon layer without raising direct defects onto the substrate area. However, in such a process it is still not possible to avoid the bird's beak phenomenon, due to the oxidation of the polysilicon layer.
Preferred embodiments of the present invention aim to provide a method for forming an improved element insulating region capable of reducing occurrence of bird's beak phenomenon and an excessive stress on a substrate.
According to a first aspect of the present invention, there is provided a process for forming an inter-element insulating region in a semiconductor device, comprising the steps of:
(a) forming a first insulating layer on a surface of a semiconductor substrate of a first conductive type, and a second insulating layer on said first insulating layer;
(b) removing a part of said second insulating layer formed on said first insulating layer;
(c) depositing a first polycrystalline silicon layer over said first and second insulating layers, and thereafter performing a planation process until the surface of said second insulating layer is exposed;
(d) oxidizing the first polycrystalline silicon in between the exposed second insulating layer to thereby produce said inter-element insulating region; and
(e) removing the remaining second insulating layer.
Preferably, said first insulating layer is an oxide layer.
Preferably, said first insulating layer is of lO0 -500A thickness.
Preferably, said second insulating layer is a nitride layer.
Preferably, said second insulating layer is of 1000A-3000A thickness.
Preferably, the thickness of said inter-element insulating region is substantially controlled in dependence upon the thickness of said second insulating layer.
Preferably, said planation process is performed by mechanical polishing.
A process as above may further comprise a step of implanting ionimpurities of the first conductive type into said substrate subsequent to said step (b), to thereby form a channel stop region.
A process as above may further comprise a step of forming a second polycrystalline silicon layer between said first insulating layer and said second insulating layer.
Preferably, said second polycrystalline silicon layer is of 500A-2000A thickness.
Preferably, said first polycrystalline silicon layer is selectively deposited on said second polycrystalline silicon layer exposed after removing said part of said second insulating layer.
According to another aspect of the present invention, there is provided a process for (or method of) forming an insulating region in a semiconductor device, comprising the steps of forming an insulating layer on a substrate, forming a polysilicon layer in a window formed in said insulating layer, oxidising said polysilicon layer to form said insulating region, and removing said insulating layer.
Such a process may further comprise any one or more of the features disclosed in the accompanying specification, claims, abstract and/or drawings, in any combination.
The invention extends also to a semiconductor device provided with an insulating region formed by a process according to any of the preceding aspects of the invention.
According to another aspect of the present invention, a buffer oxide layer and a nitride layer are sequentially formed on a substrate, and a nitride layer portion formed only on a predetermined element insulating region is selectively removed. Then, a polysilicon layer which is thicker than the nitride layer is formed over the substrate, and the surfaces of the nitride and polysilicon layers are planated by polishing. Thereafter, the polysilicon formed on the element insulating region lying between the nitride layers is oxidized, so as to form the element insulating region.
For a better understanding of the invention and to show how the same may be carried into effect, reference will now be made, by way of example, to Figures 2 to 5 of the accompanying diagrammatic drawings, in which:
Figure 2 is a cross-sectional view showing one example of an element insulating region of a semiconductor device, according to an embodiment of the present invention;
Figures 3A to 3E illustrate a process for forming an element insulating region as shown in Figure 2;
Figure 4 is a cross-sectional view showing one example of an element insulating region according to another embodiment of the present invention; and
Figure 5A to SE illustrate a process for forming an element insulating region as shown in Figure 4.
Referring to Figure 2, a buffer oxide layer 16 is formed on a silicon substrate 14 of a first conductive type in which a channel stop ionimplantation region 26 of the first conductive type is formed. An insulating oxide layer 24, being expanded by oxidization of polysilicon, is formed on the surface of the channel stop ion-implantation region 26.
In Figure 3A, the buffer oxide layer 16 of 100A-500A and a nitride layer 18 of 1000A-3000A are formed on the silicon substrate 14 by an oxidation and a chemical vapor deposition, respectively.
In Figure 3B, the nitride layer formed on a predetermined insulating region is selectively removed by a photolithography step, and then ionimpurities of the first conductive type are implanted into the substrate 14 in order to improve an insulating effect.
In Figure 3C, a polysilicon 20 which is thicker than the nitride layer
18 is formed over the substrate 14 by chemical vapor deposition.
In Figure 3D, a planation process is performed by a chemical polishing step until the surface of the nitride layer 18 is exposed out.
In Figure 3E, the polysilicon 22 remained between the inner side walls of the nitride layers 18 is oxidized by a wet-oxidation step so as to form the insulating oxide layer 24. In this case, the channel stop ion-implantation region 26 of which the concentration is higher than that of the substrate 14, is formed under the insulating oxide layer 24, by diffusing the ion-impurities of a predetermined depth implanted during the process of Figure 3B into the substrate 14. Then, the nitride layer 18 is removed by a wet-etching step so as to end the process for forming the element insulating region.
According to the above-described embodiment of the present invention, the insulating layer is formed by the oxide layer 24 which is formed between the inner side walls of the nitride layers 18 without raising direct defects onto the substrate area.
Referring now to Figure 4, a buffer oxide layer 30 is formed on a silicon substrate 28 of a first conductive type in which a channel stop ionimplantation region 46 of the first conductive type is formed. An insulating oxide layer 44 is formed on the surface of the channel stop ion-implantation region 46 by the oxidation of a polysilicon, the insulating oxide layer 44 having a first width similar to a width of the channel stop ion-implantation region 46 and a second width smaller than the first width.
In Figure 5A, the buffer oxide layer 30 of 100A-500A thick is formed on the silicon substrate 28 of the first conductive type by oxidation, and then a first polysilicon layer 32 of 500A-2000A and the nitride layer 36 of 1000A3000A are sequentially formed on the buffer oxide layer 30 by chemical vapor deposition.
In Figure SB, the nitride layer 36 formed on a predetermined insulating region is selectively removed by a photolithography step, and then ionimpurities of the first conductive type are implanted into the substrate 28 in order to improve the insulating effect.
In Figure SC, a second polysilicon layer 40 which is thicker than the nitride layer 36 is formed over the substrate 28 by chemical vapor deposition.
In Figure SD, a planation process is performed by chemical polishing until the surface of the nitride layer 36 is exposed out.
In Figure SE, the polysilicon 42 remained between the inner side walls of the nitride layers 36 is oxidized by a wet-oxidation step so as to form the insulating oxide layer 44. In this case, the channel stop ion-implantation region 46, of which the concentration is higher than that of the substrate 28, is formed under the insulating oxide layer 44, by diffusing the ion-impurities of a predetermined depth implanted during the process of Figure SB into the substrate 28. Then the nitride layer 36 and the polysilicon 32 are sequentially removed, so as to end the process for forming the element insulating region 44.
In the embodiment of the invention described with reference to Figure
SA to SE, the stress on the substrate may be considerably reduced by inserting the polysilicon 32 between the buffer oxide layer 30 and the nitride layer 36 when the insulating oxide layer 44 is formed.
Furthermore, the second polysilicon layer 40 is formed over the substrate 28 after the process of Figure SB, and then the planation process is performed, in the above embodiment. An alternate second polysilicon layer 42, however, may be selectively deposited on the surface of the first polysilicon layer 32 formed on the insulating region so that the planation process may be unnecessary.
As described above, the buffer oxide layer 30 is formed on the surface of the semiconductor substrate 28, and then the polysilicon and nitride layers 32, 36 are sequentially formed. Alternatively, the nitride layer 36 alone may be formed. Then, the nitride layer 36 formed on the element insulating region is selectively removed, and the polysilicon layer 32, of which the thickness is similar to that of the nitride layer, is formed between the inner side walls of the nitride layers 36. Thereafter, the insulating oxide layer 44 can be formed by oxidizing the polysilicon layer without raising direct defects onto the substrate area.
Consequently, the above described embodiments of the invention may provide the advantage that the bird's beak phenomenon of the insulating region is minimized.
Another advantage may be that the stress on substrate and defects of the device are minimized, because of avoiding oxidation of the substrate.
While preferred embodiments of the invention have been particularly shown and described, it will be understood by those skilled in the art that modifications in detail may be made without departing from the spirit and scope of the invention.
The reader's attention is directed to all papers and documents which are filed concurrently with or previous to this specification in connection with this application and which are open to public inspection with this specification, and the contents of all such papers and documents are incorporated herein by reference.
All of the features disclosed in this specification (including any accompanying claims, abstract and drawings), and/or all of the steps of any method or process so disclosed, may be combined in any combination, except combinations where at least some of such features and/or steps are mutually exclusive.
Each feature disclosed in this specification (including any accompanying claims, abstract and drawings), may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise. Thus, unless expressly stated otherwise, each feature disclosed is one example only of a generic series of equivalent or similar features.
The invention is not restricted to the details of the foregoing embodiment(s). The invention extends to any novel one, or any novel combination, of the features disclosed in this specification (including any accompanying claims, abstract and drawings), or to any novel one, or any novel combination, of the steps of any method or process so disclosed.
Claims (15)
1. A process for forming an inter-element insulating region in a semiconductor device, comprising the steps of:
(a) forming a first insulating layer on a surface of a semiconductor substrate of a first conductive type, and a second insulating layer on said first insulating layer;
(b) removing a part of said second insulating layer formed on said first insulating layer;
(c) depositing a first polycrystalline silicon layer over said first and second insulating layers, and thereafter performing a planation process until the surface of said second insulating layer is exposed;
(d) oxidizing the first polycrystalline silicon in between the exposed second insulating layer to thereby produce said inter-element insulating region; and
(e) removing the remaining second insulating layer.
2. A process according to claim 1, wherein said first insulating layer is an oxide layer.
3. A process according to claim 1 or 2, wherein said first insulating layer is of 100A-500A thickness.
4. A process according to claim 1, 2 or 3, wherein said second insulating layer is a nitride layer.
5. A process according to any of the preceding claims, wherein said second insulating layer is of 1()()OA-3000A thickness.
6. A process according to any of the preceding claims, wherein the thickness of said inter-element insulating region is substantially controlled in dependence upon the thickness of said second insulating layer.
7. A process according to any of the preceding claims, wherein said planation process is performed by a mechanical polishing.
8. A process according to any of the preceding claims, further comprising a step of implanting ion-impurities of the first conductive type into said substrate subsequent to said step (b), to thereby form a channel stop region.
9. A process according to any of the preceding claims, further comprising a step of forming a second polycrystalline silicon layer between said first insulating layer and said second insulating layer.
10. A process according to claim 9, wherein said second polycrystalline silicon layer is of SOOA-2000A thickness.
11. A process according to claim 9 or 10, wherein said first polycrystalline silicon layer is selectively deposited on said second polycrystalline silicon layer exposed after removing said part of said second insulating layer.
12. A process for (or method of) forming an insulating region in a semiconductor device, comprising the steps of forming an insulating layer on a substrate, forming a polysilicon layer in a window formed in said insulating layer, oxidising said polysilicon layer to form said insulating region, and removing said insulating layer.
13. A process according to claim 12, further comprising any one or more of the features disclosed in the accompanying specification, claims, abstract and/or drawings, in any combination.
14. A process for forming an insulating region in a semiconductor device, the process being substantially as hereinbefore described with reference to
Figures 2 to 3, or 4 to 5, of the accompanying drawings.
15. A semiconductor device provided with an insulating region formed by a process according to any of the preceding claims.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019910001029A KR930011460B1 (en) | 1991-01-22 | 1991-01-22 | Isolation forming method of semiconductor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| GB9119303D0 GB9119303D0 (en) | 1991-10-23 |
| GB2252201A true GB2252201A (en) | 1992-07-29 |
Family
ID=19310149
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB9119303A Withdrawn GB2252201A (en) | 1991-01-22 | 1991-09-10 | Method of forming an insulating region in a semiconductor device |
Country Status (6)
| Country | Link |
|---|---|
| JP (1) | JPH04269848A (en) |
| KR (1) | KR930011460B1 (en) |
| DE (1) | DE4129665A1 (en) |
| FR (1) | FR2671910A1 (en) |
| GB (1) | GB2252201A (en) |
| IT (1) | IT1251564B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2012142560A (en) * | 2010-12-15 | 2012-07-26 | Canon Inc | Solid-state imaging device, method for manufacturing the same, and camera |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0067738A2 (en) * | 1981-05-26 | 1982-12-22 | FAIRCHILD CAMERA & INSTRUMENT CORPORATION | Method of reducing encroachment in a semiconductor device |
| US4407696A (en) * | 1982-12-27 | 1983-10-04 | Mostek Corporation | Fabrication of isolation oxidation for MOS circuit |
| GB2198882A (en) * | 1986-12-17 | 1988-06-22 | Samsung Semiconductor Tele | A method of semiconductor device isolation by lateral separation |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4570325A (en) * | 1983-12-16 | 1986-02-18 | Kabushiki Kaisha Toshiba | Manufacturing a field oxide region for a semiconductor device |
| JPS62290146A (en) * | 1986-06-09 | 1987-12-17 | Toshiba Corp | Manufacture of semiconductor device |
| US4818235A (en) * | 1987-02-10 | 1989-04-04 | Industry Technology Research Institute | Isolation structures for integrated circuits |
| DD268336A1 (en) * | 1987-12-30 | 1989-05-24 | Dresden Forschzentr Mikroelek | PROCESS FOR PRODUCING INSULATION AREAS |
| US4962064A (en) * | 1988-05-12 | 1990-10-09 | Advanced Micro Devices, Inc. | Method of planarization of topologies in integrated circuit structures |
-
1991
- 1991-01-22 KR KR1019910001029A patent/KR930011460B1/en not_active IP Right Cessation
- 1991-08-28 FR FR9110684A patent/FR2671910A1/en not_active Withdrawn
- 1991-09-06 DE DE4129665A patent/DE4129665A1/en not_active Ceased
- 1991-09-09 IT ITMI912383A patent/IT1251564B/en active IP Right Grant
- 1991-09-10 GB GB9119303A patent/GB2252201A/en not_active Withdrawn
- 1991-09-10 JP JP3257216A patent/JPH04269848A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0067738A2 (en) * | 1981-05-26 | 1982-12-22 | FAIRCHILD CAMERA & INSTRUMENT CORPORATION | Method of reducing encroachment in a semiconductor device |
| US4407696A (en) * | 1982-12-27 | 1983-10-04 | Mostek Corporation | Fabrication of isolation oxidation for MOS circuit |
| GB2198882A (en) * | 1986-12-17 | 1988-06-22 | Samsung Semiconductor Tele | A method of semiconductor device isolation by lateral separation |
Also Published As
| Publication number | Publication date |
|---|---|
| KR930011460B1 (en) | 1993-12-08 |
| FR2671910A1 (en) | 1992-07-24 |
| ITMI912383A1 (en) | 1993-03-09 |
| GB9119303D0 (en) | 1991-10-23 |
| ITMI912383A0 (en) | 1991-09-09 |
| IT1251564B (en) | 1995-05-17 |
| JPH04269848A (en) | 1992-09-25 |
| KR920015512A (en) | 1992-08-27 |
| DE4129665A1 (en) | 1992-07-30 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| WAP | Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1) |