JPS62248222A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS62248222A
JPS62248222A JP61092560A JP9256086A JPS62248222A JP S62248222 A JPS62248222 A JP S62248222A JP 61092560 A JP61092560 A JP 61092560A JP 9256086 A JP9256086 A JP 9256086A JP S62248222 A JPS62248222 A JP S62248222A
Authority
JP
Japan
Prior art keywords
impurity
region
mask layer
thickness
regions
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61092560A
Other languages
Japanese (ja)
Inventor
Nobukuni Hara
原 信邦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
Original Assignee
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Priority to JP61092560A priority Critical patent/JPS62248222A/en
Publication of JPS62248222A publication Critical patent/JPS62248222A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To form a plural number of impurity regions, in which respective impurities are different with each other in their implanted amounts, by one-time ion implantation, by covering a plural number of the impurity regions with a mask layer and decreasing the thickness of the mask layer in conformity with the impurity concentration. CONSTITUTION:A given patterning photo resist 17 is attached to a nitriding Si film 13 on an element formation region Y, to perform allover etching. Thickness of the nitriding Si film 13 serving as a mask layer is properly controlled, in this process, in conformity with the respective regions. Then, the photo resist 17 is removed, to leave only a nitriding Si film in a given thickness on the upper surface of the Y region. Impurities definite in ion concentration are concurrently implanted under constant implanting conditions from element-formation regions X and Y surfaces. Resultantly, the region Y becomes larger in an implanting amount of impurities than the region X, because it is covered with the SiO2 films 12 and 13, finally enabling two transistors different in their threshold values to be formed on a single substrate.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は、半導体装置の製造方法、詳しくはしきい値電
圧の異なる複数のデプレッション型MO5FETを単一
の半導体基板に有する半導体装置の製造方法に関する。
Detailed Description of the Invention (Industrial Application Field) The present invention relates to a method for manufacturing a semiconductor device, and more particularly, a method for manufacturing a semiconductor device having a plurality of depletion type MO5FETs with different threshold voltages on a single semiconductor substrate. Regarding.

(従来の技術) 従来のこの種の半導体装置の製造方法としては、例えば
、第2図A乃至Fに示すようなものが知られている。
(Prior Art) As a conventional method for manufacturing this type of semiconductor device, for example, the method shown in FIGS. 2A to 2F is known.

まず、半導体基板1上に二酸化シリコン膜2を被着し、
さらに、その上に窒化シリコン膜3を被着する(同図A
)。
First, a silicon dioxide film 2 is deposited on a semiconductor substrate 1,
Furthermore, a silicon nitride film 3 is deposited thereon (FIG. A
).

次いで、所定のバターニングにより窒化シリコン膜3に
開口部を形成する(同図B)。
Next, an opening is formed in the silicon nitride film 3 by predetermined patterning (FIG. 3B).

そして、熱酸化法によりフィールド酸化膜4を形成する
(同図C)。
Then, a field oxide film 4 is formed by a thermal oxidation method (C in the same figure).

さらに、窒化シリコン膜3を、例えばエツチングにより
二酸化シリコン膜2上より取り除く(同図D)。
Furthermore, the silicon nitride film 3 is removed from the silicon dioxide film 2 by, for example, etching (FIG. 3D).

次いて、一方側の素子形成領域Xをホトレジスト5によ
りマスクし、他方側の素子形成領域Yの表面を露出した
状態でイオン注入法により低濃度の不純物を半導体基板
10表面に導入する(同図E)。
Next, the element formation region X on one side is masked with a photoresist 5, and with the surface of the element formation region Y on the other side exposed, a low concentration impurity is introduced into the surface of the semiconductor substrate 10 by ion implantation (the same figure). E).

そしてこの後、他方側の素子形成領域Yをホトレジスト
6によりマスクし、−刃側の素子形成領域Xの表面を露
出した状態でイオン注入法により高濃度の不純物を半導
体基板1の表面に導入する(同図F)。
After that, the element formation region Y on the other side is masked with a photoresist 6, and with the surface of the element formation region X on the -blade side exposed, high concentration impurities are introduced into the surface of the semiconductor substrate 1 by ion implantation. (Figure F).

このようにして単一の半導体基板上にしきい値の互いに
異なるデプレッション型MOSFETを有する半導体装
置を形成することができる。
In this way, a semiconductor device having depletion type MOSFETs having different threshold values can be formed on a single semiconductor substrate.

(発明が解決しようとする問題点) このような従来の半導体装置の製造方法にあっては、同
じ不純物を三鷹の別工程で注入しなければならず、その
工程毎にホトレジストの塗布及びその剥離が必要となる
。また、低濃度不純物のイオン注入工程と高濃度不純物
のイオン注入工程との三鷹の工程では、その注入条件を
それぞれ異ならせる必要があり、制御作業上極めて面倒
で、特に10”cm−2程度の低濃度注入時には注入イ
オン数の制御電流が〔μA〕オーダーとなり制御の安定
性に欠け、注入イオン数が少ないためウェハ基板の表面
状態に大きく影響されて濃度分布にばらつきが生じろ。
(Problems to be Solved by the Invention) In such a conventional semiconductor device manufacturing method, the same impurity must be implanted in a separate process at Mitaka, and photoresist coating and peeling are required for each process. Is required. In addition, in the Mitaka process of ion implantation of low concentration impurities and ion implantation of high concentration impurities, it is necessary to make the implantation conditions different for each, which is extremely troublesome in terms of control work. During low-concentration implantation, the control current for the number of implanted ions is on the order of [μA], resulting in lack of control stability, and since the number of implanted ions is small, it is greatly influenced by the surface condition of the wafer substrate, resulting in variations in the concentration distribution.

(問題点を解決するための手段) そこで、本発明は、不純物濃度がそれぞれ異なる複数の
不純物領域を有する半導体装置の製造にあたって、これ
らの複数の不純物領域をマスク層で被う工程と、その不
純物領域のマスク層の厚さを不純物の濃度に対応させて
減少させる工程と、各不純物領域に不純物を一定注入条
件下で同時に注入する工程とを備えた。
(Means for Solving the Problems) Therefore, the present invention provides a step of covering the plurality of impurity regions with a mask layer and a step of covering the plurality of impurity regions with a mask layer in manufacturing a semiconductor device having a plurality of impurity regions each having a different impurity concentration. The method includes a step of reducing the thickness of a mask layer in a region in accordance with the impurity concentration, and a step of simultaneously implanting impurities into each impurity region under constant implantation conditions.

(作用) 複数の不純物領域をマスク層で被い、そして、このマス
ク層の厚さをその不純物の濃度に応じて減少させるので
、各不純物領域のマスク層の厚さはその不純物の濃度に
応じた厚さとなる。したがって一度のイオン注入で、そ
れぞれの不純物の注入量が異なる複数の不純物領域が形
成される。
(Operation) A plurality of impurity regions are covered with a mask layer, and the thickness of this mask layer is decreased according to the concentration of the impurity, so the thickness of the mask layer for each impurity region is adjusted according to the concentration of the impurity. The thickness will be increased. Therefore, a plurality of impurity regions each having a different amount of impurity implanted are formed by one ion implantation.

(実施例) 以下、本発明の実施例を図面に基づいて説明する。(Example) Embodiments of the present invention will be described below based on the drawings.

第1図A乃至第1図Eは、本発明の一実施例に係るその
各工程を示す半導体装置の部分断面図である。
FIGS. 1A to 1E are partial cross-sectional views of a semiconductor device showing each process according to an embodiment of the present invention.

まず、半導体基板11上に二酸化シリコン膜12を被着
し、さらにその上に窒化シリコン膜13を所定の厚さに
、例えば3000人程度0厚さに形成する(第1図A)
First, a silicon dioxide film 12 is deposited on a semiconductor substrate 11, and a silicon nitride film 13 is further formed thereon to a predetermined thickness, for example, to a thickness of about 3000 (FIG. 1A).
.

次に、この窒化シリコン膜13の複数の素子形成領域に
対応して、所定のバターニングにより、複数の間口部1
3Aを形成する(第1図B)。
Next, a plurality of frontage portions 1 are formed by predetermined patterning in correspondence to a plurality of element forming regions of the silicon nitride film 13.
3A (Figure 1B).

次に、熱酸化法を用いてその間口部13Aに所定厚さの
フィールド酸化膜15を同時に形成し、この酸化膜15
によって素子形成領域X、Yを公社する。なお、この場
合、これらの素子形成領域X、Yの二酸化シリコン膜1
2上には窒化シリコン膜13が残存している(第1図C
)。
Next, a field oxide film 15 of a predetermined thickness is simultaneously formed on the opening portion 13A using a thermal oxidation method, and this oxide film 15
The element formation areas X and Y are defined by the public corporation. In this case, the silicon dioxide film 1 in these element formation regions X and Y
A silicon nitride film 13 remains on 2 (FIG. 1C)
).

次に、この素子形成領域Y上の窒化シリコン膜13上に
所定のパターニング用ホトレジスト17を被着し、さら
にこの後全面エツチングを施す。
Next, a predetermined patterning photoresist 17 is deposited on the silicon nitride film 13 on the element forming region Y, and then the entire surface is etched.

その結果、素子形成領域X上の窒化シリコン膜13は除
去され、領域Xでは二酸化シリコン膜120表面が露出
する一方、素子形成領域Yでは所定厚さの窒化シリコン
膜13がなお残存している(第1図D)。すなわち、こ
の工程、においてはマスク層である窒化シリコン膜13
の厚さが各領域に対応して適宜制御されるのである。
As a result, the silicon nitride film 13 on the element formation region X is removed, and the surface of the silicon dioxide film 120 is exposed in the region X, while the silicon nitride film 13 of a predetermined thickness still remains in the element formation region Y ( Figure 1 D). That is, in this step, the silicon nitride film 13 serving as a mask layer is
The thickness of the area is controlled as appropriate for each area.

次いで、このホトレジスト17を除去し、領域Yの上面
には所定厚さの窒化シリコン膜13のみを残す。
Next, this photoresist 17 is removed, leaving only the silicon nitride film 13 of a predetermined thickness on the upper surface of the region Y.

ここで、これらの素子形成領域X、Yの表面から同時に
所定イオン濃度の不純物を一定の注入条件下にイオン注
入法を用いてその素子形成領域X。
Here, impurities with a predetermined ion concentration are simultaneously implanted from the surfaces of these element forming regions X and Y using an ion implantation method under certain conditions.

Yに導入する。この注入条件としては例えばその打ち込
みエネルギー、注入量等を領域Xての所望の不純物濃度
が得られるように設定しである。その゛結果、素子形成
領域Yはその上面が二酸化シリコン膜12及び窒化シリ
コン膜13(マスク層)に被覆されているため、素子形
成領域Xに比べてイオンの基板11への到達量が少なく
なる。すなわち、これらの素子形成領域X、Yにあって
は、領域Xの方が領域Yよりもその不純物の注入量が少
なくなって濃度が低くなる。
Introduce it to Y. The implantation conditions include, for example, the implantation energy, implantation amount, etc., which are set so as to obtain a desired impurity concentration in the region X. As a result, since the upper surface of the element formation region Y is covered with the silicon dioxide film 12 and the silicon nitride film 13 (mask layer), the amount of ions reaching the substrate 11 is smaller than that in the element formation region X. . That is, in these element formation regions X and Y, the amount of impurity implanted in region X is smaller than in region Y, resulting in a lower concentration.

そして、以後、ソース・ドレイン領域を形成する等の所
定のプロセスを経て、しきい値の互いに異なる二つのト
ランジスタを単一の半導体基板11上に形成することが
できるのである(第1図E)なお、上記実施例にあって
は二つの不純物領域X、Yについて、マスク層である窒
化シリコン膜13の厚さを異ならせ、それぞれに互いに
注入量の異なる不純物領域を形成したものである。しか
し、本発明はこれに限られることなく、例えば三つのそ
れぞれ濃度(注入量)の異なる不純物領域を単一の半導
体基板に形成する場合についても適用できる。この場合
は、それぞれの領域のマスク層の厚さを異ならせればよ
いのであり、上述と同様に一度のイオン注入によりこれ
は達成することができる。
Thereafter, through predetermined processes such as forming source and drain regions, two transistors with different threshold values can be formed on a single semiconductor substrate 11 (Fig. 1E). In the above embodiment, the thickness of the silicon nitride film 13 serving as a mask layer is made different for the two impurity regions X and Y, and impurity regions having different implantation amounts are formed in each of the two impurity regions X and Y. However, the present invention is not limited thereto, and can also be applied, for example, to a case where three impurity regions having different concentrations (implanted amounts) are formed on a single semiconductor substrate. In this case, it is sufficient to vary the thickness of the mask layer in each region, and this can be achieved by one ion implantation as described above.

(効果) 以上説明してきたように、本発明によれば、半導体装置
の製造方法において、その製造工程を減少することがで
きる。その結果、例えばマスクを一枚で済ますことがで
きる等、その作業を極めて容易にすることができる。と
ともに、一定の濃度の不純物を一度に注入することでそ
れぞれ濃度の異なる不純物領域を単一の半導体基板上に
容易に形成することができ、さらに製品装置の性能等を
も安定化させることができるという効果を奏する。
(Effects) As described above, according to the present invention, the number of manufacturing steps can be reduced in the method of manufacturing a semiconductor device. As a result, the work can be made extremely easy, for example by requiring only one mask. In addition, by implanting impurities at a fixed concentration all at once, impurity regions with different concentrations can be easily formed on a single semiconductor substrate, and the performance of product devices can also be stabilized. This effect is achieved.

【図面の簡単な説明】[Brief explanation of drawings]

第1図A乃至Eは本発明に係る半導体装置の製造方法の
一実施例を示す各工程における該装置一部断面図、第2
図A乃至Fは従来の製造方法を示すその各工程における
半導体装置の一部断面図である。 11・・・・・半導体基板
1A to 1E are partial sectional views of the device in each step showing an embodiment of the method for manufacturing a semiconductor device according to the present invention, and FIG.
Figures A to F are partial cross-sectional views of a semiconductor device at each step showing a conventional manufacturing method. 11...Semiconductor substrate

Claims (1)

【特許請求の範囲】[Claims] 不純物濃度がそれぞれ異なる複数の不純物領域を有する
半導体装置の製造方法において、これらの複数の不純物
領域をマスク層で被う工程と、これらの不純物領域の各
マスク層の厚さをその不純物濃度に対応させて減少させ
る工程と、各不純物領域に不純物を一定注入条件下で同
時に注入する工程と、を備えたことを特徴とする半導体
装置の製造方法。
In a method for manufacturing a semiconductor device having a plurality of impurity regions each having a different impurity concentration, there is a step of covering the plurality of impurity regions with a mask layer, and adjusting the thickness of each mask layer of these impurity regions according to the impurity concentration. 1. A method of manufacturing a semiconductor device, comprising: a step of reducing the impurity by reducing the impurity, and a step of simultaneously implanting impurities into each impurity region under constant implantation conditions.
JP61092560A 1986-04-21 1986-04-21 Manufacture of semiconductor device Pending JPS62248222A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61092560A JPS62248222A (en) 1986-04-21 1986-04-21 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61092560A JPS62248222A (en) 1986-04-21 1986-04-21 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS62248222A true JPS62248222A (en) 1987-10-29

Family

ID=14057806

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61092560A Pending JPS62248222A (en) 1986-04-21 1986-04-21 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS62248222A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5739058A (en) * 1995-12-14 1998-04-14 Micron Technology, Inc. Method to control threshold voltage by modifying implant dosage using variable aperture dopant implants

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5739058A (en) * 1995-12-14 1998-04-14 Micron Technology, Inc. Method to control threshold voltage by modifying implant dosage using variable aperture dopant implants

Similar Documents

Publication Publication Date Title
JPH06112483A (en) Manufacture of semiconductor device using soi substrate
JPH08148649A (en) Method of manufacturing semiconductor device
JPH02219253A (en) Manufacture of semiconductor integrated circuit device
JPH09289323A (en) Manufacture of semiconductor device
JPS6143477A (en) Manufacture of mos transistor
JPS62248222A (en) Manufacture of semiconductor device
EP0453070B1 (en) Method of manufacturing an intelligent power semiconductor device
JP2754202B2 (en) Method for manufacturing semiconductor device
JP2817226B2 (en) Method for manufacturing semiconductor device
JPS59964A (en) Manufacture of semiconductor device
JPH0328833B2 (en)
JPH027558A (en) Semiconductor device and manufacture thereof
JPS60240131A (en) Manufacture of semiconductor device
JPH065562A (en) Formation of semiconductor thin film
KR100225383B1 (en) Method of manufacturing semiconductor device
JP3260311B2 (en) Method for manufacturing semiconductor device
KR100249150B1 (en) Method for manufacturing field oxidation film
KR850000037B1 (en) The method of mos with self alignment metal electroid
JPH0214788B2 (en)
JPS63144543A (en) Formation of semiconductor interelement isolation region
JPH04180647A (en) Manufacture of semiconductor integrated circuit
JPS6197974A (en) Manufacture of semiconductor device
JPH09289313A (en) Threshold voltage setting method for semiconductor device
KR960009204A (en) How to prepare pyrom
JPH06204240A (en) Manufacturing method of semiconductor device