JPH10289947A - Semiconductor and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which can be formed in a short period of time by a simple process without giving an adverse influence on element characteristics when an element isolation region, on which a substrate is divided into a plurality of element forming regions, is formed, and to provide the manufacturing method of the above-mentioned semiconductor device. SOLUTION: Boric ions are selectively implanted into the prescribed region of a P-type silicon substrate 12 where an element isolation region is formed, and after a thermally oxidized film 14 in prescribed thickness and an oxide film 26 have been formed on the silicon substrate 12 by a high temperature CVD(chemical vapor deposition) method, element isolation regions 28a and 28b are removed by etching using a fluoric acid solution. An element isolation diffusion layer 22 is formed on the boric ion implanted region when the thermally oxidized film 14 and the oxide film 26 are formed by a high temperature CVD method. As a result, the element isolation region, having a small element area and inflicting no adverse effect on element characteristics, can be formed in a short period of time by a simple process.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device in which a semiconductor substrate is divided into a plurality of element formation regions by element isolation regions, and a method of manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, a plurality of devices formed on the same semiconductor substrate are arranged at least two-dimensionally (there is also a three-dimensional structure in which two-dimensional structures are stacked). In this case, the elements are separated from each other by an element isolation region so as not to exert an electric influence on each other.

As a technique for forming this kind of element isolation region, for example, a so-called LOCOS (LOCOS) is formed by selectively thermally oxidizing a part of a silicon substrate to form a thick element isolation insulating film (SiO ₂ ). Local Oxidation of
Silicon) method is generally used. When an element isolation insulating film is formed by the LOCOS method, a nitride film (for example, Si ₃ N ₄ ) serving as an oxidation-resistant mask is formed and patterned on a silicon substrate when performing selective oxidation. The exposed portion of the substrate is oxidized to form an element isolation insulating film, and the portion covered with the nitride film remains without being oxidized.

Therefore, a conventional complementary MOS (CMOS: Complementar MOS) in which a P-channel transistor and an N-channel transistor are separated using the above-mentioned LOCOS method.
y Metal Oxide Semiconductor) A manufacturing process of the transistor 50 will be briefly described with reference to FIGS.

As shown in FIG. 6, phosphorus is thermally diffused into a P-channel transistor forming region of a P-type silicon substrate (P-sub) 52 to form an N-well layer 54,
The P well layer 56 is formed by thermally diffusing boron in the region where the N-channel transistor is formed. Then, as shown in FIG. 7, after the surface of the silicon substrate 52 is thermally oxidized to form an oxide film 58 over the entire surface, a nitride film 60 serving as an oxidation-resistant mask is formed thereon by chemical vapor deposition (CVD). Vapor
Deposition). Next, as shown in FIG. 8, the resist 62 is patterned so that the nitride film 60 in the element formation region on the N well layer 54 and the P well layer 56 remains, and the nitride film 60 is etched using the resist 62 as an etching mask. Thereafter, as shown in FIG. 9, in order to form an element isolation diffusion layer, a resist 64 is selectively formed so as to open an element isolation region between a P-channel transistor and an N-channel transistor. (The crosses in the figure indicate the implantation positions of boron ions in the P-well layer 56). Then, after the resists 62 and 64 are removed, an oxidation process is performed in high-temperature (1000 ° C. or higher) steam to obtain a nitride film 60 as shown in FIG.
Portions not covered with a thick element isolation insulating film (SiO 2
₂ ) A P + element isolation diffusion layer (field dope) 68 is formed where the 66a, 66b, and 66c are formed, and where boron ions have been implanted first. Then, nitride film 6
By removing 0, as shown in FIG. 11, element formation regions 70a and 70b are formed by element isolation insulating films 66a, 66b and 66c.

[0006]

However, such a conventional semiconductor device uses an element isolation method based on LOCOS oxidation. Therefore, when a selective oxidation process is performed using a nitride film, a silicon substrate cannot be used. The element isolation regions (element isolation insulating films 66a, 66b, 66c) are formed through complicated steps such as formation of a nitride film, etching of a nitride film, thermal oxidation treatment, and removal of a nitride film. There was an inconvenience of becoming longer.

In the LOCOS method, since the nitride film 60 is used as an oxidation-resistant mask, when the nitride film 60 is removed (the above-described process), a residue is generated by a so-called white ribbon. When crystal defects occur in the oxide film and the like due to the stress at the edge of the nitride film in the above step),
There are inconveniences that the breakdown voltage of the gate oxide film at the edge of the field oxide film is deteriorated and a junction leak occurs.

Further, in the LOCOS method, a thick oxide film is selectively formed in an element isolation region.
As the nitride film 60 spreads in the direction of the substrate surface so as to lift the nitride film 60 (see FIG. 10), the element area tends to increase.
In addition, the element isolation diffusion layer 68 formed under the element isolation insulating film 66b has a disadvantage that the heat treatment time by the selective oxidation process is long, and the diffusion proceeds and spreads, and the element area increases. there were. This increase in the element area decreases the degree of integration.

Further, as a conventional example related to the element isolation technique other than the above, for example, Japanese Patent Laid-Open No. 7-115125
JP-A-7-115126 or JP-A-7-115126
No. 76605 and the like.

In view of the above, according to the first aspect of the present invention, a first conductivity type impurity ion is implanted into a semiconductor substrate for forming an element isolation region to form an element isolation diffusion layer, and a thermal oxide film is formed on the semiconductor substrate. By depositing an oxide film formed by high-temperature chemical vapor deposition and high-temperature chemical vapor deposition, and selectively removing the thermal oxide film and the oxide film formed by high-temperature chemical vapor deposition in the element formation region, the element isolation region is easily formed in a short time. It is an object of the present invention to provide a semiconductor device which can prevent a breakdown voltage of an oxide film and a junction leak from occurring and can reduce the area of each element.

According to a second aspect of the present invention, the invention according to the first aspect is applied to a complementary MOS transistor.
It is an object of the present invention to provide a semiconductor device capable of reliably performing element isolation between transistors having different conductivity types and reducing the element area to improve the degree of integration.

According to a third aspect of the present invention, a thermal oxide film is formed on a semiconductor substrate, and an oxide film formed by high-temperature chemical vapor deposition is deposited on the thermal oxide film. By selectively removing the oxide film by vapor phase growth, the element isolation region can be easily formed in a short time, the breakdown voltage of the oxide film can be prevented, and the occurrence of junction leak can be prevented. It is an object of the present invention to provide a method of manufacturing a semiconductor device which can be performed.

According to a fourth aspect of the present invention, before the oxide film is deposited by the high temperature chemical vapor deposition according to the third aspect of the present invention, an element isolation diffusion layer is formed at a position where an element isolation region is formed in the semiconductor substrate. By implanting impurity ions of the first conductivity type to form a diffusion layer for element isolation having a small spread by heat treatment by high-temperature chemical vapor deposition, a method for manufacturing a semiconductor device capable of reducing the element area can be provided. It is intended to provide.

According to a fifth aspect of the present invention, the invention according to the fourth aspect is applied to a complementary MOS transistor.
It is an object of the present invention to provide a method of manufacturing a semiconductor device capable of reliably performing element isolation between transistors of different conductivity types and reducing the element area to improve the degree of integration.

[0015]

According to a first aspect of the present invention, there is provided a semiconductor device in which a semiconductor substrate is divided into a plurality of element formation regions by an element isolation region, wherein the element isolation region is formed. A first conductivity type impurity ion for forming a device isolation diffusion layer is implanted into a predetermined region, a thermal oxide film having a predetermined thickness is formed on the semiconductor substrate, and an oxide film formed by high-temperature chemical vapor deposition is formed. The above object is achieved by depositing a predetermined film thickness and selectively removing the thermal oxide film and the oxide film formed by the high-temperature chemical vapor deposition in the element formation region excluding at least the element isolation region.

According to the above configuration, the first conductivity type impurity ions are implanted into the region where the element isolation diffusion layer is formed in the semiconductor substrate where the element isolation region is formed, and the thermal oxide film and the semiconductor substrate are formed on the semiconductor substrate. An oxide film formed by high-temperature chemical vapor deposition is formed thereon to a predetermined thickness, and the thermal oxide film in the element formation region and the oxide film formed by high-temperature chemical vapor deposition are selectively removed. As a result, the element isolation region can be formed in a short time and with a simple manufacturing process, and at the same time, the breakdown voltage of the oxide film and the occurrence of junction leak can be prevented. Can be raised.

According to a second aspect of the present invention, in each of the element formation regions of the semiconductor substrate according to the first aspect of the present invention, a pair of MOS transistors each including a first conductivity type channel and a second conductivity type channel are provided. The configured complementary MOS transistor may be formed.

According to the above configuration, it is possible to reliably perform element isolation between complementary MOS transistors having different conductivity types, and to reduce the complementary MOS transistor having a relatively large element area as much as possible to reduce the degree of integration. Can be raised.

According to a third aspect of the present invention, in the method of manufacturing a semiconductor device, the semiconductor substrate is divided into a plurality of element formation regions by element isolation regions. Forming a film, depositing a predetermined thickness of an oxide film by high-temperature chemical vapor deposition on the thermal oxide film, and forming the thermal oxide film and the high-temperature chemical gas in the element formation region excluding at least the element isolation region. The above object is achieved by including a step of selectively removing an oxide film by vapor phase growth.

According to the above method, a thermal oxide film having a predetermined thickness is formed on a semiconductor substrate, and an oxide film formed by high-temperature chemical vapor deposition is deposited on the thermal oxide film to form an element forming region. By selectively removing the thermal oxide film and the oxide film formed by high-temperature chemical vapor deposition, an element isolation region can be easily formed in a short time, and it is possible to prevent the breakdown voltage of the oxide film and the occurrence of junction leak, The degree of integration can be increased by reducing the element area.

In the method of manufacturing a semiconductor device according to a fourth aspect of the present invention, an element isolation region is formed before the step of depositing a predetermined thickness of an oxide film by high temperature chemical vapor deposition according to the third aspect of the present invention. A first conductivity type impurity ion for forming an element isolation diffusion layer may be implanted in a semiconductor substrate.

According to the above method, before depositing an oxide film by high temperature chemical vapor deposition, impurity ions of the first conductivity type for forming an element isolation diffusion layer in an element isolation region in a semiconductor substrate are implanted. By doing so, it becomes possible to form a diffusion layer for element isolation having a small spread by heat treatment of high-temperature chemical vapor deposition, so that the element area can be reduced, and the degree of integration can be increased.

According to a fifth aspect of the invention, there is provided a method of manufacturing a semiconductor device, wherein each element forming region of the semiconductor substrate according to the third or fourth aspect has a first conductivity type channel and a second conductivity type channel, respectively. A complementary MOS transistor composed of a pair of MOS transistors formed of channels may be used.

According to the above-described method, element isolation between transistors of different conductivity types of the complementary MOS transistors is ensured, and complementary MOS transistors having a relatively large element area are reduced as much as possible to reduce the degree of integration. Can be raised.

[0025]

Preferred embodiments of the present invention will be described below in detail with reference to the accompanying drawings. It should be noted that the embodiments described below are preferred embodiments of the present invention, and therefore, various technically preferable limitations are added. However, the scope of the present invention is not limited to the following description. The embodiments are not limited to these embodiments unless otherwise specified.

FIGS. 1 to 5 are process sectional views illustrating an embodiment of a method of manufacturing a semiconductor device according to the present invention. In the present embodiment, a complementary MOS (CMOS) transistor is formed by forming an element isolation region on a silicon substrate and dividing it into a plurality of element isolation regions, and forming a P-channel transistor and an N-channel transistor in each element isolation region. 10 is formed.

Hereinafter, the manufacturing process of the CMOS transistor 10 will be described with reference to FIGS.

First, as shown in FIG. 1, on a P-type silicon substrate (P-sub) 12, phosphorus is thermally diffused into a region for forming a P-channel transistor to form an N-well layer 14, and then an N-well layer 14 is formed. The P well layer 16 is formed by thermally diffusing boron in a region where a channel transistor is to be formed.

As shown in FIG. 2, an opening is formed on the silicon substrate 12 near the boundary between the N-well layer 14 and the P-well layer 16 to form a later-described element isolation diffusion layer 22. The resist 18 is patterned and formed by photolithography so that the part comes, and using this as an ion implantation mask, boron ions are accelerated at an accelerating voltage of 30K.
It is selectively implanted into the silicon substrate 12 under the conditions of eV and a dose amount (1 × 10 ¹³ / cm ² ).
The boron ion implantation position in the well layer 16 is shown).

Next, as shown in FIG. 3, after removing the resist 18, at a processing temperature of 920 ° C. for 15 minutes.
By subjecting the surface of the silicon substrate 12 to wet oxidation in water vapor, a thermal oxide film 24 having a thickness of about 250 Å is formed on the silicon substrate 12. At the same time, due to the heat treatment during the wet oxidation, the boron ion implantation region 20 is partially thermally diffused to form a P + element isolation diffusion layer (field dope) 22.

In FIG. 4, the oxide film 26 is formed by high-temperature CVD using a low-pressure CVD apparatus in which a silicon substrate is accommodated in a chamber (not shown) and a chemical reaction is performed in a state where the pressure in the chamber is reduced. It is formed by depositing on the formed thermal oxide film 24. This oxide film 26 has a processing temperature of 900 ° C.
Oxide film 26 having a film thickness of about 6000 Å is obtained by forming the film by processing for 0 minutes. At the same time,
By the heat treatment by the high-temperature CVD, the thermal diffusion of the element isolation diffusion layer 22 formed earlier advances, and the region of the P + element isolation diffusion layer 22 is enlarged.

In the case of FIG. 10 of the conventional example, the element isolation insulating film 66b having an increased film thickness due to thermal oxidation pushes the element isolation diffusion layer 68 in the direction of the substrate surface and heat treatment time by selective oxidation. Is long, the diffusion layer 6 for element isolation
8, the heat diffusion was advanced, and the element area was increased. on the other hand,
In the case of the present embodiment, as shown in FIG. 5, although the diffusion layer 22 for element isolation is diffused by heat treatment for depositing the oxide film 26b as the element isolation region, the processing temperature and the processing time are the same as those of the prior art. Since it is lower and shorter than in the selective oxidation, the oxide film 26
b stays in the element isolation region, and does not lead to an increase in the element area. Rather, in this embodiment, since the oxide film 26b in the element isolation region is formed by an etching step described later, the element isolation insulating film 66b does not spread in the direction of the substrate surface as in the bird's beak in the selective oxidation of the conventional example, so that the element area is small. Can be reduced.

Next, as shown in FIG. 5, the thermal oxide film 24 and the oxide film 26 formed in the steps up to FIG.
Photolithography is performed on a resist (not shown) applied on the oxide film 26 so as to selectively etch away only the element forming regions 28a and 28b where the P-channel transistor and the N-channel transistor forming the OS transistor 10 are formed. Patterning by technology. Then, using the patterned resist as an etching mask, the thermal oxide film 24 and the oxide film 26 are etched down to the surface of the silicon substrate 12 with a hydrofluoric acid (HF) solution to form a pattern having a shape as shown in FIG. You.

The CMOS transistor 10 shown in FIG.
Since the manufacturing process is the same as the conventional manufacturing process, detailed description is omitted. However, the surface of the silicon substrate 12 in each of the element formation regions 28a and 28b is thermally oxidized to form a gate oxide film having a predetermined thickness. The gate electrode is patterned thereon, and the formed gate electrode is used as an ion implantation mask to implant impurity ions according to the conductivity type of the channel of each transistor by self-alignment (self-alignment). By forming the source / drain regions, a P-channel transistor is formed in the element formation region 28a and an N-channel transistor is formed in the element formation region 28b.

As described above, according to the present embodiment, the device isolation region for dividing the same silicon substrate into a plurality of device formation regions is formed in the silicon substrate without using the LOCOS method. Impurity ions for forming a layer are implanted, and a thermal oxide film and an oxide film formed by high-temperature CVD are formed and patterned on the silicon substrate, so that the device area is small and reliable device isolation can be performed. An element isolation region can be formed. The manufacturing process is not as complicated as the Locos method, and the manufacturing time can be reduced.

Further, according to the present embodiment, since the nitride film used by the LOCOS method or the like is not used during the manufacturing process, deterioration of the withstand voltage of the gate oxide film due to the remaining nitride film and occurrence of junction leak are prevented. Can be prevented.

Further, according to this embodiment, the implantation of impurity ions (boron) for forming the element isolation diffusion layer is performed before the heat treatment step of forming an oxide film by high-temperature CVD. The above-described impurity ions are thermally diffused by heat treatment when forming an oxide film by CVD, and at the same time, a diffusion layer for element isolation is formed. Therefore, the manufacturing process is simplified. In addition, since the element isolation diffusion layer to be formed has a small spread in the substrate surface direction, there is an advantage that the element area can be small and the degree of integration can be improved.

The element isolation region formed according to the present embodiment has a structure particularly effective for a low breakdown voltage device.

Although the invention made by the present inventors has been specifically described based on the preferred embodiments, the present invention is not limited to the above-described embodiments, and various modifications may be made without departing from the gist of the invention. It goes without saying that it is possible.

For example, in the above embodiment, the CM
Although an example in which an OS transistor is formed has been described, it is needless to say that the present invention is not limited to this. The present invention can be applied to all cases where element isolation is required when a plurality of elements are formed on the same substrate. .

Further, in the above-described embodiment, an example has been given of the implantation conditions and types of impurity ions when forming the element isolation diffusion layer, and the processing conditions (temperature, time, etc.) in various film forming steps. Therefore, the present invention is not limited to these conditions, and can be appropriately changed depending on the type of element to be formed, element characteristics, and the like.

[0042]

According to the semiconductor device of the present invention, a first conductivity type impurity ion is implanted into a semiconductor substrate for forming an element isolation region to form an element isolation diffusion layer.
A thermal oxide film and an oxide film formed by high-temperature chemical vapor deposition are deposited on a semiconductor substrate, and the thermal oxide film in the element formation region and the oxide film formed by high-temperature chemical vapor deposition are selectively removed. Thus, it is possible to prevent the deterioration of the breakdown voltage of the oxide film and the occurrence of the junction leak, and to reduce the area of each element.

According to the method of manufacturing a semiconductor device according to the second aspect of the present invention, since the first aspect of the present invention is applied to a complementary MOS transistor, it is possible to reliably perform element isolation between transistors of different conductivity types. In addition, the device area can be reduced and the degree of integration can be improved.

According to the third aspect of the present invention, a thermal oxide film is formed on a semiconductor substrate, and an oxide film formed by high-temperature chemical vapor deposition is deposited on the thermal oxide film.
Since the thermal oxide film in the element formation region and the oxide film formed by high-temperature chemical vapor deposition are selectively removed, the element isolation region can be easily formed in a short time, and the breakdown voltage of the oxide film and the occurrence of junction leak can be prevented. The area of each element can be reduced.

According to the method of manufacturing a semiconductor device of the present invention, before the oxide film is deposited by the high-temperature chemical vapor deposition of the present invention, the formation position of the element isolation region in the semiconductor substrate is formed. To form a diffusion layer for element isolation in
Since the impurity ions of the conductivity type are implanted, a diffusion layer for element isolation having a small spread is formed by heat treatment by high-temperature chemical vapor deposition, so that the element area can be reduced.

According to the method of manufacturing a semiconductor device of the fifth aspect of the present invention, since the invention of the fourth aspect is applied to a complementary MOS transistor, it is possible to reliably perform element isolation between transistors of different conductivity types. And the degree of integration can be improved by reducing the element area.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating an N-well / P-well layer diffusion step according to a method for manufacturing a semiconductor device of the present invention.

FIG. 2 is a cross-sectional view illustrating a step of implanting impurity ions for forming an element isolation diffusion layer according to the method for manufacturing a semiconductor device of the present invention.

FIG. 3 is a cross-sectional view illustrating a step of forming a thermal oxide film on a silicon substrate according to the method for manufacturing a semiconductor device of the present invention.

FIG. 4 is a high-temperature CV according to the method for manufacturing a semiconductor device of the present invention.
Sectional drawing explaining the formation process of a D oxide film.

FIG. 5 is a cross-sectional view illustrating a completed pattern of an element isolation region according to the method for manufacturing a semiconductor device of the present invention.

FIG. 6 is a cross-sectional view illustrating an N-well / P-well layer diffusion step according to a conventional method of manufacturing a semiconductor device.

FIG. 7 is a cross-sectional view illustrating a step of forming a thermal oxide film and a nitride film according to a conventional method of manufacturing a semiconductor device.

FIG. 8 is a cross-sectional view illustrating a step of patterning a thermal oxide film and a nitride film according to a conventional method of manufacturing a semiconductor device.

FIG. 9 is a cross-sectional view illustrating a step of implanting impurity ions for forming a diffusion layer for element isolation according to a conventional method for manufacturing a semiconductor device.

FIG. 10 is a cross-sectional view illustrating a selective oxidation step of forming an element isolation insulating film according to a conventional method of manufacturing a semiconductor device.

FIG. 11 is a cross-sectional view illustrating a completed pattern of an element isolation insulating film according to a conventional method of manufacturing a semiconductor device.

[Explanation of symbols]

Reference Signs List 10 CMOS transistor (complementary MOS transistor) 12 P-type silicon substrate (semiconductor substrate) 26 oxide film (part of element isolation region) 14 thermal oxide film (part of element isolation region) 22 diffusion layer for element isolation (element isolation) Part of the area)

Claims (5)

[Claims] 1. A semiconductor device in which a semiconductor substrate is divided into a plurality of element formation regions by element isolation regions, wherein a first conductivity type diffusion layer is formed in the semiconductor substrate on which the element isolation regions are formed. Impurity ions are implanted into a predetermined region, a thermal oxide film having a predetermined thickness is formed on the semiconductor substrate, and an oxide film formed by high-temperature chemical vapor deposition is deposited to a predetermined thickness to remove at least the element isolation region. A semiconductor device, wherein the thermal oxide film and the oxide film formed by the high-temperature chemical vapor deposition in an element formation region are selectively removed. 2. A complementary MOS transistor comprising a pair of MOS transistors each having a first conductivity type channel and a second conductivity type channel is formed in each element formation region of the semiconductor substrate. Claim 1
3. The semiconductor device according to claim 1. 3. A method of manufacturing a semiconductor device, comprising dividing a semiconductor substrate into a plurality of element formation regions by element isolation regions.
Forming a thermal oxide film of a predetermined thickness on the semiconductor substrate; depositing an oxide film of a predetermined thickness on the thermal oxide film by high-temperature chemical vapor deposition; and Selectively removing the thermal oxide film and the oxide film formed by the high-temperature chemical vapor deposition in the formation region;
A method for manufacturing a semiconductor device, comprising: 4. A first conductivity type forming an element isolation diffusion layer in the semiconductor substrate on which the element isolation region is formed before depositing an oxide film of a predetermined thickness by the high temperature chemical vapor deposition. 4. The method according to claim 3, wherein the impurity ions are implanted. 5. A complementary MOS transistor comprising a pair of MOS transistors each having a first conductivity type channel and a second conductivity type channel is formed in each element formation region of the semiconductor substrate. Claim 3
A method for manufacturing a semiconductor device according to claim 4.