JP2597424B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device.

[0002]

2. Description of the Related Art When a resist pattern is formed on a substrate having a high step, there is a step of processing a deposited film having an overhang structure. FIG. 10 to FIG. 12 are schematic cross-sectional views showing a process of forming an overhang structure.
A thermal oxide film 2 is formed on the surface of the substrate 1, and polycrystalline silicon 4 is further deposited on the thermal oxide film 2 (FIG. 10).

Next, after forming a resist (not shown) pattern, a predetermined portion of the polycrystalline silicon 4 is removed, and a pattern of the polycrystalline silicon 4 having a vertical shape is obtained (FIG. 11). Next, CVD oxide film 3 is deposited on remaining polycrystalline silicon 4 and thermal oxide film 2. In this case, a film having poor step coverage is deposited, resulting in an overhang structure. FIGS. 13 to 16 are schematic cross-sectional views showing a conventional example of the step of patterning a substrate having the above-described overhang structure by using a single-layer resist process.
FIGS. 13 and 17 to 21 show schematic cross-sectional views of a step of forming a pattern using a three-layer process. This will be described below with reference to the drawings.

[0004] A thermal oxide film 2 is formed on the surface of a substrate 1, and a CVD oxide film 3 is further deposited on the thermal oxide film 2. After forming a resist (not shown) pattern on the CVD oxide film 3, a predetermined portion of the CVD oxide film 3 is removed to form a groove 11. Thereafter, polycrystalline silicon 4 is deposited on CVD oxide film 3 and in trench 11 (FIG. 13). Next, a resist 6 is applied on the polycrystalline silicon 4 (FIG. 14). Thereafter, a mask pattern is formed and exposure is performed (FIG. 15). Next, a desired pattern is obtained by developing the substrate (FIG. 16).

On the other hand, in the step of forming a pattern using a three-layer process, first, a lower resist 7 is applied on the substrate shown in FIG. 13 described above, and then an intermediate layer 8 is formed on the lower resist 7. For this intermediate layer 8, for example, coated glass or the like is used. Next, an upper resist 9 is formed on the intermediate layer 8.
Is applied (FIG. 17). Next, an upper resist pattern (not shown) is formed, and the upper resist 9 immediately above the groove 11 is removed (FIG. 18). Thereafter, the intermediate layer 8 immediately below the removed upper layer resist 9 is removed by dry developing the substrate (FIG. 19).

Next, the lower resist 7 is removed by anisotropic etching (FIG. 20). Thereafter, the polycrystalline silicon 4 is etched (FIG. 21).

[0007]

As described above, in the single-layer resist process, it is difficult to remove the resist in a narrow slit shape as shown in FIG. 16 and process the resist to a desired line width. It is. In the three-layer process, when processing the lower layer resist, a technique such as anisotropic dry development is used. Therefore, as shown in FIG. 20, it is difficult to remove the resist under the overhang, that is, the lower layer resist 7a. In addition, as shown in FIG. 21, there is a problem that polycrystalline silicon 4a is partially left as polycrystalline silicon.

SUMMARY OF THE INVENTION The present invention has been made in view of these points, and it is an object of the present invention to provide a method of manufacturing a semiconductor device which can easily form a resist pattern on a high step and can easily process even an overhang shape. With the goal.

[0009]

According to a method of manufacturing a semiconductor device of the present invention, a thermal oxide film is formed on a substrate,
After forming the oxide film, a groove is formed by removing a predetermined portion of the CVD oxide film, and then polycrystalline silicon is deposited on the CVD oxide film and in the groove.
After applying the spin-on glass on the polycrystalline silicon and in the groove, a photoresist is formed on the spin-on glass not including the groove, and then the spin-on glass in the groove is removed by etching, and then the groove is formed in the groove. After the remaining polycrystalline polysilicon is removed by etching, the photoresist is removed, and then the spin-on glass remaining on the CVD oxide film is removed.

[0010]

Before the photoresist is formed, the substrate is planarized by depositing spin-on glass on the substrate and in the groove having the overhang structure.

[0011]

1 to 9 are schematic sectional views showing an embodiment of the present invention over time. Hereinafter, embodiments of the present invention will be described with reference to the drawings. Forming a thermal oxide film 2 on the surface of the substrate 1;
Further, a CVD oxide film 3 is deposited on the thermal oxide film 2.
After forming a resist (not shown) pattern on the CVD oxide film 3, a predetermined portion of the CVD oxide film 3 is removed to form a groove 10 in the CVD oxide film 3. Thereafter, polycrystalline silicon 4 is formed on CVD oxide film 3 and in trench 10.
Is deposited (FIG. 1).

Next, the spin-on glass 5 (Spin On Glass) is formed on the substrate and in the groove 10 having the overhang structure.
Glass) is applied and embedded (FIG. 2). Thereafter, a photoresist 6 is formed on the spin-on glass 5 (FIG. 3). Next, the spin-on glass 5 is removed in a thin slit shape by anisotropic etching (FIG. 4), and further, the spin-on glass 5 in the groove 10 is removed isotropically by isotropic etching (FIG. 5). . Next, the polycrystalline silicon 4 is removed by anisotropic etching (FIG. 6), and the polycrystalline silicon 4 in the groove 10 is further isotropically removed by isotropic etching.

Next, the photoresist 6 is removed (FIG. 8).
The spin-on glass 5 remaining on the polycrystalline silicon 4 is
It is removed with an HF aqueous solution or the like (FIG. 9). Through the above steps, the photoresist 6 under the overhang can be removed, and the polycrystalline silicon 4 does not remain in the trench 11.

[0014]

As described above, according to the present invention, since the planarization is performed before the formation of the photoresist pattern, the formation of the resist pattern can be performed even on a substrate having a high step and an overhang structure. It becomes easy, and highly accurate patterning can be realized. As a result, high integration is easily realized.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view showing an embodiment of the present invention over time.

FIG. 2 is a schematic sectional view showing an embodiment of the present invention over time.

FIG. 3 is a schematic sectional view showing an embodiment of the present invention over time.

FIG. 4 is a schematic sectional view showing an embodiment of the present invention over time.

FIG. 5 is a schematic sectional view showing an embodiment of the present invention over time.

FIG. 6 is a schematic sectional view showing an embodiment of the present invention over time.

FIG. 7 is a schematic sectional view showing an embodiment of the present invention over time.

FIG. 8 is a schematic sectional view showing an embodiment of the present invention over time.

FIG. 9 is a schematic sectional view showing an embodiment of the present invention over time.

FIG. 10 is a schematic cross-sectional view showing a process of forming an overhang structure over time.

FIG. 11 is a schematic cross-sectional view showing a process of forming an overhang structure over time.

FIG. 12 is a schematic cross-sectional view showing a process of forming an overhang structure over time.

FIG. 13 is a schematic sectional view showing a conventional example over time.

FIG. 14 is a schematic cross-sectional view showing a conventional example over time.

FIG. 15 is a schematic cross-sectional view showing a conventional example over time.

FIG. 16 is a schematic sectional view showing a conventional example over time.

FIG. 17 is a schematic sectional view showing another conventional example over time.

FIG. 18 is a schematic cross-sectional view showing another conventional example over time.

FIG. 19 is a schematic sectional view showing another conventional example over time.

FIG. 20 is a schematic sectional view showing another conventional example over time.

FIG. 21 is a schematic sectional view showing another conventional example over time.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Single crystal silicon 2 ... Thermal oxide film 3 ... CVD oxide film 4 ... Polycrystalline silicon 5 ... Spin-on glass 6 ... Photoresist 10 ... ·groove

Claims (1)

(57) [Claims] 1. A method of forming a thermal oxide film on a substrate,
After forming the D oxide film, a groove is formed by removing a predetermined portion of the CVD oxide film, and then polycrystalline silicon is deposited on the CVD oxide film and in the groove. After applying the spin-on glass in the groove, a photoresist is formed on the spin-on glass not including the groove, and then the spin-on glass in the groove is removed by etching, and then the polycrystalline poly remaining in the groove is formed. After removing the silicon by etching, the photoresist is removed, and then the CV is removed.
A method for manufacturing a semiconductor device for removing the spin-on glass remaining on a D oxide film.