JPH05114713A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To increase the capacity of a capacitor without increasing its plane area, and to strictly control the increment of capacity. CONSTITUTION:A lower electrode 19 is formed in such a manner that its side end is extended toward a substrate 11. An SiO2 film 17 is patterned using a silicon nitride film 16 as the end part of etching, and the lower electrode 19 is formed in such a manner that its side end is extended toward the substrate 11 leaving a polycrystalline silicon film 23 on the above-mentioned side wall. The extended part, i.e., the increment of capacitance. can be controlled strictly.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a capacitor on a substrate such as a dynamic random access memory (hereinafter referred to as DRAM) and a method of manufacturing the same.

[0002]

2. Description of the Related Art FIG. 4 is a plan view and a sectional view of a memory cell of a conventional DRAM disclosed in Japanese Patent Laid-Open No. 1-117354. The sectional view of (b) is a sectional view taken along the line AA ′ in the plan view of (a). In this figure, the hatched portion is a capacitor, which is composed of a lower electrode 1, a dielectric film 2, and an upper electrode 3. The characteristic of this capacitor is that the back surface of the lower electrode is exposed at the side edge of the lower electrode 1, and the back surface portion is also covered to cover the dielectric film 2 and the upper electrode 3.
This is because the back surface of the lower electrode 1 is also used as a part of the capacitor due to the formation of, and the capacitance of the capacitor is increased.

Such a capacitor is manufactured as shown in FIG. First, as shown in FIG. 5A, an insulating film 8 is formed on a semiconductor substrate 7 on which a field insulating film 4, a MOS transistor 5 as a transfer gate, and an electrode wiring 6 are formed, and a contact hole 9 is partially formed. .. Then, a lower electrode 1 is formed on the insulating film 8 using a polycrystalline silicon film as shown in FIG. 5B. afterwards,
The insulating film 8 is isotropically etched using the lower electrode 1 as a mask, so that the lower electrode 1 is removed as shown in FIG.
Expose the back of the side edge of. Thereafter, the lower electrode 1 including the exposed back surface portion of the side end is covered with the dielectric film 2 and further with the upper electrode 3 as shown in FIG. 5D to complete the capacitor.

[0004]

However, in the prior art as described above, as a method of exposing a part of the back surface of the lower electrode 1, the insulating film 8 between the lower electrode 1 and the substrate 7 is used.
Is isotropically etched, it is difficult to strictly control the exposed area of the back surface. That is, the isotropic etching must be stopped midway so that the underlying gate electrode and electrode wiring are not exposed, so the amount of etching, that is, the exposed area of the back surface is adjusted by the etching time. For this reason, the exposed area changes due to variations in the etching rate of the insulating film 8 between processing batches, changes in the etching rate during etching with time, and the like. As a result, the conventional method has a problem that the increased capacity varies depending on the capacitor, and there is a problem that a DRAM memory cell in which a necessary capacity cannot be ensured occurs in a specific processing batch.

The present invention has been made in view of the above points, and a semiconductor device in which the capacitance of a capacitor can be increased without increasing the planar area and the increment of the capacitance can be strictly controlled, and It is intended to provide a manufacturing method thereof.

[0006]

According to the present invention, the shape of the lower electrode is such that its side end extends in the substrate direction.
Further, such a lower electrode is manufactured as follows.
After forming a three-layer structure of the first insulating film, the second insulating film, and the third insulating film on the substrate, the lower electrode of the capacitor is formed on the third insulating film, and the second insulating film is further formed. The third insulating film is patterned in the same pattern as the lower electrode by anisotropic etching with the etching end point as the etching end, and then the electrode material is subjected to the entire surface deposition and etch back to form the patterned third insulating film. By leaving only on the side wall of the membrane,
A side end of the lower electrode is extended in the substrate direction.

[0007]

In the present invention described above, since the side end of the lower electrode has a shape extended in the substrate direction, the capacitance of the capacitor can be increased at that portion without increasing the planar area. In addition, by patterning the third insulating film by using the second insulating film as the end point of etching and leaving the electrode material on the side wall of the third insulating film, the side end of the lower electrode is extended in the substrate direction. So that
The length of the extended portion can be accurately controlled by the film thickness of the third insulating film, and the amount of increase in capacitance due to the extended portion is strictly controlled.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing a DRAM memory cell as an embodiment of a semiconductor device of the present invention, (b) is a plan view,
(A) is a BB 'sectional view taken on the line of (b). In this figure, 11 is a silicon substrate, and a field insulating film 12,
MOS transistor 13 as a transfer gate,
The electrode wiring 14 is formed. The entire surface of the substrate 11 is covered with a SiO ₂ film 15 as a first insulating film, and a silicon nitride film 16 as a _second insulating film and a SiO ₂ film as a third insulating film are further formed thereon. 17 is patterned and overlaps. A contact hole 18 is formed on the drain region 13a of the transfer gate MOS transistor 13 in the insulating film having the three-layer structure. A lower electrode 19 of the capacitor connected to the drain region 13a through the contact hole 18 is formed on the SiO ₂ film 17, and a side end of the lower electrode 19 is formed on the SiO ₂ film 1.
7 extends in the direction of the substrate 11 along the side wall.
A capacitor dielectric film 20 is formed on the surface of the lower electrode 19 including the extended portion, and the lower electrode 1 is sandwiched by the dielectric film 20 including the extended portion.
The surface of 9 is covered with the upper electrode 21 of the capacitor.

In the DRAM memory cell as described above, the lower electrode 19, the dielectric film 20 and the upper electrode 21 constitute a capacitor, and the side end of the lower electrode 19 is extended in the direction of the substrate 11. Therefore, the capacitance of the capacitor can be increased in this portion without increasing the planar area. The memory cell as described above is manufactured as shown in FIGS. 2 and 3 (one embodiment of the manufacturing method of the present invention).

First, as shown in FIG. 2A, a field insulating film 12 is selectively formed on the surface of a silicon substrate 11 by LOC.
After being formed by the OS method, the MOS transistor 13 as a transfer gate is formed in the element region of the substrate 11 by a usual method.
And the electrode wiring 1 extending from the gate electrode of the MOS transistor 13 on the field insulating film 12.
4 is formed.

Next, as shown in FIG. 2B, a SiO ₂ film 15 as a first insulating film, a silicon nitride film 16 as a second insulating film, and a third insulating film are formed on the entire surface of the substrate 11. As
The SiO ₂ film 17 is sequentially formed by the CVD method. At this time, the SiO ₂ films 15 and 17 as the first and third layers are at normal pressure CV.
Each is formed to a film thickness of 2000 Å by the D method. Further, the intermediate second silicon nitride film 16 is formed to a film thickness of 100 Å by the LPCVD method. Total 4 as above
After forming an insulating film having a three-layer structure of 100 Å, a contact hole 18 for making contact between the capacitor lower electrode and the drain region 13a is formed in this insulating film. At this time, dry etching using a mixed gas of CHF ₃ / CF ₄ is used for etching the contact hole 18, so that the SiO ₂ film 17, the silicon nitride film 16, and the SiO ₂ film 15 are successively etched in this order. Thus, the contact hole 18 can be formed.

Next, as shown in FIG. 2C, a polycrystalline silicon film 22 for forming a lower electrode of the capacitor is deposited on the entire surface of the SiO ₂ film 17 including the contact hole 18 portion. The formed film thickness is about 1500Å.

Next, the polycrystalline silicon film 22 is formed as shown in FIG.
The lower electrode 19 of the capacitor is formed by patterning as shown in (a), and the SiO ₂ film 17 is subsequently etched in the same pattern as the lower electrode 19. At this time, the lower electrode 19 is formed by dry etching with SF ₆ / CH ₂ F ₂ mixed gas using a photosensitive resin (resist) pattern as a mask, and the subsequent etching of the SiO ₂ film 17 is performed by the lower electrode. 19 is performed by using anisotropic dry etching with a parallel plate type etching apparatus using a CHF ₃ / CF ₄ mixed gas while leaving the resist pattern mask used for forming 19. At this time, etching is performed until the silicon nitride film 16, which is an intermediate layer of the three-layer insulating film, is exposed. Whether or not the silicon nitride film 16 is exposed can be easily detected by a change in emission intensity from plasma. Therefore, the etching (patterning) of the SiO ₂ film 17 can be accurately performed by the etching whose end point is the exposure of the silicon nitride film 16. Next, additional etching is performed until the silicon nitride film 16 exposed on the surface is removed so that the silicon nitride film 16 does not remain on the surface as shown in FIG. After the above is completed, the resist pattern used as the mask pattern is removed.

Next, the polycrystalline silicon film 2 for forming the extension portion
3 is deposited on the entire surface as shown in FIG. afterwards,
The entire surface of the polycrystalline silicon film 23 is etched back to obtain the structure shown in FIG.
As shown in (c), the polycrystalline silicon film 23 is left only on the side wall of the SiO ₂ film 17 so that the side end of the lower electrode 19 is extended in the direction of the substrate 11. At this time, the SF ₆
/ CH ₂ F ₂ mixed gas is used, pressure is 0.2 Torr, and RF power is 100 W.

After that, as shown in FIG. 3D, the dielectric film 20 of the capacitor, and further the upper electrode 21 of the capacitor, so as to cover the surface of the lower electrode 19 including the extended portion of the side end toward the substrate. To complete the capacitor and at the same time complete the memory cell of FIG.

Although the above is the memory cell of the DRAM, the present invention can of course be used for forming a capacitor of another semiconductor device.

[0017]

As described in detail above, according to the present invention, the shape of the lower electrode is such that the side end thereof is extended in the substrate direction, so that the capacitor can be formed without increasing the planar area. Capacity can be increased. Further, by patterning the third insulating film by using the second insulating film as an etching end point and leaving the electrode material on the side wall of the third insulating film, the side end of the lower electrode is extended to the substrate direction. The length of the extension is set to the third
The thickness of the insulating film can be accurately controlled, and the increase in capacitance can be strictly controlled. By this,
For example, the effect of reducing the variation in the capacity of the DRAM memory cell and making it difficult for the memory cell having the insufficient capacity to occur can be expected. Further, according to the present invention, by increasing the thickness of the third insulating film and lengthening the extension portion of the lower electrode in the substrate direction, the amount of increase in capacitance can be easily increased. It can be said that the structure and the manufacturing method are very suitable for large capacity and high integration.

[Brief description of drawings]

FIG. 1 is a plan view and a sectional view showing an embodiment of a semiconductor device of the present invention.

FIG. 2 is a process sectional view showing a part of an embodiment of a method for manufacturing a semiconductor device of the present invention.

FIG. 3 is a process sectional view showing a part of an embodiment of a method for manufacturing a semiconductor device of the present invention.

FIG. 4 is a plan view and a cross-sectional view showing a conventional DRAM memory cell.

5A to 5D are process cross-sectional views showing a conventional method for manufacturing a capacitor.

[Explanation of symbols]

11 Silicon Substrate 15 SiO ₂ Film 16 Silicon Nitride Film 17 SiO ₂ Film 19 Lower Electrode 20 Capacitor Dielectric Film 21 Upper Electrode 22 Polycrystalline Silicon Film 23 Polycrystalline Silicon Film

Claims (2)

[Claims] 1. A semiconductor device having a capacitor including a lower electrode, a dielectric film, and an upper electrode on a substrate, wherein the lower electrode formed on the insulating film on the substrate has a side edge extending in the substrate direction. And a dielectric film is provided so as to cover the surface of the lower electrode including the extended portion thereof, and an upper electrode is similarly provided so as to cover the lower electrode. 2. A first insulating film, a second insulating film, and
After forming the three-layer structure of the third insulating film, the lower electrode of the capacitor is formed on the third insulating film, and the third insulating film is anisotropically etched to end the third insulating film. The film is patterned in the same pattern as the lower electrode, and then the electrode material is left only on the side wall of the patterned third insulating film by the overall deposition of the electrode material and the etch back. A method of manufacturing a semiconductor device, wherein the structure has a structure extending in the substrate direction.