DE4340226C2 - Component with isolation region structure and method for producing the same - Google Patents

Description

The invention relates to a semiconductor device with the front Partly high integrability, more specifically a semiconductor construction element with isolation area structure and a method to make it both using an iso lation technique with a buried oxide as well as one Technology with local silicon oxidation.

Techniques with local silicon oxidation (LOCOS = Local Oxidation of Silicon) have been used adjacent active areas in the LSI and VLSI production of MOS Isolate transistors from each other. According to one LOCOS technology becomes a thin oxide cushion film between one Silicon substrate and a nitride film as an oxidation mask arranged to relieve voltages due to the difference thermal properties of the silicon substrate and Ni dismantle tridfilms.  

However, such LOCOS techniques do not only include ver tical growth of a field oxide film during field oxidation, son cross-diffusion of an oxidizing agent the stress-relieving oxide cushion film. As a result the field oxide film under an edge of the nitride film as oxi dation mask grew up in the transverse direction.

Because of such cross growth, there is an encroachment of the field oxide film on an active area, which the active area reduced.

The phenomenon that the field oxide film on the active area spills over, is known as the bird's beak phenomenon. On such bird's beak has a length that is up to 1/2 of Makes up the thickness of the field oxide film.

To shorten the length of the bird's beak, which ver the thickness of the active area of the field oxide film can be reduced. However, a ver decrease in the thickness of the field oxide film to an increase in Capacity between the substrate and each of the connections lines on a chip. As a result, deteriorate IC characteristics.

In addition, the threshold voltage V _{T of} a parasitic field transistor decreases, which leads to an increase in the leakage current in an area under the field oxide film. As a result, the insulating property between adjacent active areas deteriorates.

Currently the method of reducing the length of the Vo gel bill by reducing the thickness of the field oxide film unsuitable as a practical insulation process.  

As a result, research was carried out into the growth of the Vo to prevent gel beak and thus the length of the bird to shorten beaks without increasing the thickness of the field oxide film out.

One of the methods of preventing bird growth beak without reducing the thickness of the field oxide film a field oxidation process in which an oxide cushion film through a nitride formed over the oxide cushion film film as an oxidation mask and one in the form of side walls formed on the side surfaces of the oxide cushion film Nitride film is included.

As next generation insulation techniques, one Polysilicon buffering LOCOS isolation technology, the poly silicon used as a voltage buffering layer, a wall masking insulation (SWAMI) technology and a LOCOS Insulation technology with an enclosed interface (SILO = Sealed interface LOCOS). In addition, Isola tion with a buried oxide (BOX) known.

Isolation techniques that require high integration density Modifying components are applicable, the following Er requirements are sufficient.

First, the isolation area should be a flat surface exhibit. This is to overcome a difficulty that with an aspect ratio due to a decrease in Transverse dimension of a finally manufactured component has to do, thereby creating excellent pattern limitation properties to maintain.

Second, there should be no crystalline defect in the volume of one Field area next to an edge section of an active Be occur empire.  

Third, no bird's beak should be created to maxi male active areas.

The BOX insulation technology is the insulation technology which is capable of meeting the above requirement nits are enough.

In general, the BOX insulation technology has fol steps: growing up a stress-reducing Oxide film on a silicon substrate, depositing a Ni trid film over the oxide film, patterns of the nitride film and the Oxide film around an active area and a field area determine, etching away part of the silicon substrate ent speaking the field area using photolitho graphic to form a trench, filling the trench with a CVD oxide film, coating a photoresist film over the resulting structure and etch back of the photoresist films and the CVD oxide film around the surface of the oxide film flatten.

The reason why the photoresist film is applied and then etched back is that the surface of the CVD oxide films should be leveled, which fills the trench.

In other words, is the CVD oxide film that fills the trench len is supposed to lie in its over a wide trench deepened the section, causing its surface is uneven. The surface of the CVD oxide film is under Ver leveled using the photoresist film.

Although the BOX insulation process has the advantages that there is no bird's beak and that the surface of the isolation area, the following are with it Problems connected.  

First of all, it requires complicated manufacturing steps because the Photolithography process is carried out twice, namely in the step of forming the trench and also in the step flattening the CVD oxide film.

Second, the surface-leveling photoresist film with an uneven thickness, depending on the pattern density. As a result, the photoresist film in an area of high density smaller thickness. This is necessary changes a critical resist etching process step. Different said, the surface of the CVD oxide film cannot be full be constantly leveled because the CVD oxide film and the Pho resist film are uneven. After the etching, the Surface of the active area may be fairly damaged.

As insulation technology with which a flat surface is obtained can be used without spilling over the active area, and in which a single photolithography process step ver an isolation procedure has been proposed where neighboring active areas using the LOCOS isolation technology can be isolated from each other, whereby a large space between adjacent active areas is determined, as well as using the BOX-Isola tion technology in which a small space (a narrow trench) between adjacent active areas. This process, the LOCOS insulation technology and the BOX isolation technology used together is in the US patent No. 4,892,614, which corresponds to EP 0252450 A2.

FIGS. 2A through 2H are that illustrate veran a conventional method of producing isolation regions in a semiconductor device using both the LOCOS Iso lationstechnik and the BOX isolation technique cross-sections.

According to this method, a thermal oxide film 12 is grown on a silicon substrate 10 as shown in FIG. 2A. Then, a nitride film 14 is deposited on the thermal oxide film 12 using chemical vapor deposition at low pressure (LPCVD). A photoresist film 16 is applied to the nitride film 14 and then patterned to define active areas 18 . Using the patterned photoresist film 16 as a mask, the nitride film 14 and the oxide film 12 are etched, and the silicon substrate 10 is etched so that a trench structure with a plurality of trenches 20 a to 20 d is formed. The two trenches 20 a and 20 b have a relatively small width, as a result of which they define a narrow isolation space between adjacent active regions 18 . On the other hand, the two trenches 20 c and 20 d have a relatively large width, as a result of which they define a wide isolation space between adjacent active regions 18 . In Fig. 2A be the reference numeral 21 draws the edges of each trench.

Thereafter, the photoresist film 16 remaining over the active areas 18 is completely removed, as shown in FIG. 2B. Thereafter, a second thermal oxide film 22 is grown over those portions of the silicon substrate 20 which are exposed due to the formation of the trench structure. This thermal oxide film 22 serves to slightly round off the edges 21 of each trench in comparison with the course in the structure of FIG. 2A.

A second nitride film 24 is deposited on the entire free surface of the resulting structure, as shown in FIG. 2C. An oxide film 26 of large thickness is deposited on the second nitride film 24 using a CVD process. The oxide film 26 is applied with such a thickness that it fills the narrow trenches 20 a and 20 b sufficiently, but only insufficiently fills the wide trenches 20 c and 20 d. As a result, small depressions 27 a form in the surface portion of the oxide film 26 over the narrow trenches 20 a and 20 b. On the other hand, large depressions 27 b form in the surface section of the oxide film over the wide trenches 20 c and 20 d.

An anisotropic etching step is then performed to form sidewalls on each trench, as shown in FIG. 2D. In the anisotropic etching step, respective sections of the CVD oxide film 26 , the nitride film 24 and the thermal oxide film 22 are etched away, which are arranged under the large depressions 27 b in the wide trenches 20 c and 20 d. As a result, the silicon substrate 10 is exposed in its sections lying in the trenches 20 c and 20 d, respectively. Each of the trenches 20 c and 20 d sides has wall oxide films 28. Each of the narrow trenches 20 a and 20 b also has sidewall oxide films 28 . In this case, however, the sidewall oxide films 20 are formed to completely fill the trench. As a result, the nitride film 24 is not etched.

Thereafter, a field oxidation step is carried out to produce a field oxide film as shown in Fig. 2E. In the field oxidation step, the sidewall oxide films 28 of the trench structure are removed. Formation of a field oxide film 30 is achieved using a LOCOS process. At this time, no field oxide film 30 grows in the narrow trenches 20 a and 20 b, since there the silicon substrate 10 is covered with the nitride film 24 . However, the field oxide film 30 grows in the wide trenches 20 c and 20 d over the silicon substrate 10 . In the wide trenches 20 c and 20 d, the field oxide film 30 also grows over the edge portions of the nitride film 24 , whereby bird beaks 31 are formed. Despite such bird beaks 31 , however, the dimensions of the active areas 18 are not reduced. This is because the bird's beaks 31 do not grow to the areas over the active areas 18 .

Thereafter, the nitride films 14 and 24 are completely removed by immersing them in hot phosphoric acid solution, as shown in Fig. 2F. A CVD oxide film 32 is applied thickly over the entire free surface of the resulting structure to fill up all of the trenches so that there is a flat surface.

Thereafter, the CVD oxide film 32 is etched back to create a flat surface as shown in Fig. 2G.

A third thermal oxide film 24 is then formed as a gate oxide film on the entire free surface of the resulting structure in order to obtain isolation regions for mutually active regions 18 , as shown in FIG. 2H. The isolation regions have the BOX structure, the CVD oxide film 32 formed in each of the narrow trenches 20 a and 20 b, the LOCOS structure 30 formed by the field oxide film 30 formed over the wide trenches 20 c and 20 d, and the CVD -Oxide film 32 is formed, which extends over the edge regions of the field oxide film 30 .

In other words, the isolation between the active areas 18 is achieved at each of the narrow trenches 20 a and 20 b according to the BOX isolation technique. At each of the wide trenches 20 c and 20 d, the isolation between the active areas 18 is achieved by a combination of the BOX and LOCOS isolation technology.

From this it can be seen that the method for producing Isolation areas on a semiconductor device using  both LOCOS insulation technology and BOX Isolation technology is able to meet the requirements meet those for high integration in semiconductor devices ten are set up, d. H. a flat surface, none Bird's beak and easy leveling using a single photolithography process step for trench education dung.

In the above-mentioned method, however, when the CVD oxide film 32 fills the trenches 20 formed in the silicon substrate 10 , this filling in the case of narrow and deep trenches can be achieved incompletely, thereby forming voids. In order to avoid such void formation, it is necessary to deposit the CVD oxide film 32 at a high temperature of 750 to 800 ° C. However, such a high temperature manufacturing cycle has a problem that crystal defects are formed in the lower edge portion 21 of the trench structure.

Since the CVD oxide film 32 fills the trench structure, due to the difference in thermal expansion coefficients for the silicon substrate 10 and the CVD oxide film 32 in a heat cycle process step following the manufacture of the insulation regions, stresses can be exerted on the silicon substrate 10 . As a result, a crystal may be defective.

Furthermore, the CVD oxide film 32 filling the trench structure shows a high etching rate in an HF solution. As a result, the CVD oxide film 22 can be severely damaged in a cleaning process step following the manufacture of the isolation regions.

From US-Z: Motorola Technical Developments, Vol. 18, March 1993, pages 18-21 Another semiconductor component is already known, in which on a p-type Substrate n-type epitaxial layers are formed. The semiconductor device has narrow and wide trenches that extend through the epitaxial layers extend into the substrate, which is lined with a dielectric layer and are filled with polysilicon. This trench technique can isolate between Form transistors, create minimal sidewall capacitance, and allow egg NEN contact from the top of the device to the p-type substrate create.

JP 4-336 447 (abstract) describes another semiconductor component, in which in one Trenches provided with the substrate are lined with an insulation film and with a Polysilicon film are filled. For isolation of the individual circuit elements an insulation film formed on the surface of the substrate is provided, which is also extends over the trenches.

JP 4-225 259 (abstract) describes yet another component in which a layer structure provided on a substrate and serving as a substrate for individual circuit elements is provided with an element isolation trench, the side walls of which are covered with a CVD-SiO ₂ film and an im In relation to this, very thin CVD-SiN film is lined and filled with a polysilicon layer. A thermal oxide film is provided on the polysilicon layer.

The invention has for its object a semiconductor device with Isolationsbe empire structure as well as a process for producing the same, with or with which reliably fills trenches.

The invention is by the semiconductor device according to claim 1 and by the Method according to claim 8 solved. Advantageous further education and training the invention is described in the respective subordinate claims ben.

The invention will now be described, for example, with reference to the drawing explained in more detail. Show it:

Fig. 1 is a cross-sectional view showing an isolation region structure in a non-inventive semiconductor device;

Figs. 2A to 2H are cross sections illustrating a conventional method of manufacturing a conventional semiconductor device isolation region structure;

Fig. 3 is a cross section showing an isolation region structure in a semiconductor device according to an embodiment of the invention;

FIGS. 4A to 4I are cross sections a method for manufacturing the insulation area structure shown in Figure 1 illustrate. and

Fig. 5A to 5I are cross sections illustrating a method of fabricating the isolation region structure of the invention of FIG. 3.

The illustrated in Fig. 1, not isolation region structure according to the invention, which, however, does not belong to the prior art, has a plurality of trenches, both narrow 51a and 51b as well as wide 51c and 51d, the strat in a Siliziumsub 41st An oxide film 53 is present on the bottom surface and opposite side surfaces of the narrow trenches 51 a and 51 b and on opposite side surfaces of the wide trenches 51 c and 51 d. A field oxide film 59 is c and on the bottom surface of the wide grooves 51 formed 51d. The isolation region structure also has a polysilicon film 61 which fills the narrow trenches 51 a and 51 b and the wide trenches 51 c and 51 d. An oxide film 43 is formed over active areas 49 , and a thin oxide film 63 is formed over the polysilicon film 61 to protect it.

In this structure, the narrow trenches 51 a and 51 b are only filled with the polysilicon film 61, while the wide trenches 51 c and 51 d are filled with the field oxide film 59 and the polysilicon film 61 in order to isolate adjacent active areas from one another.

In the exemplary embodiment according to the invention according to FIG. 3, elements which correspond to those of FIG. 1 are identified by the same reference numerals.

As shown in FIG. 3, the isolation region structure has a trench structure with a plurality of trenches, namely narrow 51a and 51b and wide 51c, 51d, which are formed in the silicon substrate 41 . An oxide film 53 is formed on the bottom surface and ge opposite side surfaces of each of the narrow trenches 51 a and 51 b and on opposite side surfaces of each of the wide trenches 51 c and 51 d. A field oxide film 59 is formed on the bottom surface of each of the wide trenches 51 c and 51 d. The isolation region structure further has a nitride film 55 for covering the entire area of the portion of the oxide film 53 which is arranged in each of the narrow trenches 51 a and 51 b, the opposite side surfaces of the portion of the oxide film 53 which is in each of the wide trenches 51 c and d 51 is formed, and opposite edges of the portion of the oxide film 59, in each of the wide grooves 51 c and d is present 51st A polysilicon film 61 fills the narrow trenches 51 a and 51 b and the wide trenches 51 c and 51 d. An oxide film 43 is formed over the active areas 49 and a field oxide film 65 is formed over the polysilicon film 61 to protect it.

In this structure of the second embodiment, the field oxide film 65 is formed on the polysilicon film 61 with a large thickness compared to the thin oxide film 63 in the first embodiment, for example.

With this structure, the nitride film 55 is formed for an oxidation mask in the trenches to serve as a stress-relieving layer.

According to the method for producing the semiconductor component according to FIG. 1 shown in FIGS . 4A to 4I, an oxide cushion film 43 with a thickness of 10 nm is formed over a silicon substrate 41 , as shown in FIG. 4A. The oxide cushion film 43 serves as a stress-relieving layer in a subsequent field oxidation step. A nitride film 45 with a thickness of 150 nm is deposited over the oxide cushion film 43 using an LPCVD process. The nitride film 45 serves in the following field oxidation step as an oxidation mask. The nitride film 45 is coated with a photoresist film 47 .

Thereafter, the photoresist film 47 is patterned to define active regions 49 , as shown in Fig. 4B. Using the patterned photoresist film 47 as a mask, the nitride film 45 and the oxide cushion film 43 are etched to remove their portions that are not over the active areas 49 . As a result, the silicon substrate 41 is partially exposed by the removed portions of the nitride film 45 and the oxide cushion film 43 .

Thereafter, the exposed portions of the silicon substrate 41 are etched to a depth of 200 to 500 nm to form trenches. As a result, the silicon substrate 41 has a plurality of trenches, which each lie between adjacent active regions 49 . The trenches include narrow 51a and 51b and wide 51c and 51c.

After the trenches are formed, the remaining photoresist film 47 is removed as shown in Fig. 4C. Thereafter, a second oxide cushion film 53 will grow in each trench.

A second nitride film 55 approximately 30 nm thick is formed over the entire exposed surface of the resulting structure using an LPCVD process, as shown in FIG. 4D. Thereafter, a CVD oxide film 57 is thickly deposited over the second nitride film 55 to fill in the trenches.

Then, an etch back process is carried out to etch the CVD oxide film 57 , as illustrated by FIG. 4E. Reactive ion etching (RIE) is used in the etch back process step.

In the case of the narrow trenches 51 a and 51 b, the CVD oxide film 57 completely fills the trenches and thereby forms a flat surface. The second nitride film 55 is still held in the trenches by the CVD oxide film 57 .

On the other hand, the CVD oxide film 57 forms c in the case of wide trenches 51 and 51 d spacers in the trenches. On the bottom surface of each trench, the second nitride film 55 and the second oxide cushion film 53 are etched away, causing the silicon substrate 41 to be partially exposed.

Thereafter, the CVD oxide film 57 formed in the trenches is completely removed by immersing it in HF solution, as illustrated by FIG. 4F. A field oxidation step is carried out to form a field oxide film 59 . The field oxide film 59 has a thickness of 500 nm. In the narrow trenches 51 a and 51 b, it does not grow because of the presence of the CVD oxide film 57 , as indicated above in connection with FIG. 4E, the nitride film 55 is still present there is. However, the field oxide film 59 grows on the exposed portions of the silicon substrate 41 in the wide grooves 51 c and 51 d, with the nitride film 55 is used as an oxidation mask.

The nitride films 45 and 55, which serve as the oxidation mask, are completely removed by immersion in hot phosphoric acid solution (H ₃ PO ₄ ) at a temperature of 160 ° C., as shown in FIG. 4G. Thereafter, a polysilicon film 61 is deposited over the entire free surface of the resulting structure using an LPCVD process at a temperature of 550 to 650 ° C. The polysilicon film 61 has a thickness of 500 nm in order to fill all the trenches sufficiently and thereby to ensure a flat surface.

Then, as shown in Fig. 4H, the polysilicon film 61 is etched back to obtain a flat surface. In the etching back step, the end point for the etching stop is set so that the first oxide cushion film 43 is exposed.

As a result, the narrow trenches 51 a and 51 b are filled with the polysilicon film 61 in order to isolate adjacent active regions 49 from one another. On the other hand, the wide trenches 51 c and 51 d are filled with the field oxide film 59 formed on the bottom surfaces of the trenches using the LOCOS process and with the polysilicon film 61 in order to isolate adjacent active regions 49 from one another.

Thereafter, the surface of the trench filling polysilicon film 61 is subjected to oxidation to form a thermal oxide film 63 as shown in FIG. 4I. As a result, the entire surface of the silicon substrate 41 is covered with the oxide film. Where the surface of the silicon film 61 would be exposed, a parasitic effect would occur between a connecting line and a gate line extending over the surface of the finally manufactured component, which would lead to an increase in the parasitic capacitance or the formation of leakage paths , The thermal oxide film 63 on the polysilicon film 61 serves for the polysilicon film 63 to have a passivation area in order to prevent the occurrence of the parasitic effect mentioned.

In this semiconductor device, the thermal oxide film 63 of small thickness is used as a passivation layer for the trench filling polysilicon film 61 .

The process steps illustrated in FIGS . 5A to 5F for producing the component according to the invention are each identical to the process steps illustrated by FIGS . 4A to 4F. In FIGS. 5A to 51, elements corresponding to those in Figs. 4A to 4I, each denoted by the same reference numerals.

After the field oxide film 59 is formed according to the field oxidation step illustrated by FIG. 5, a polysilicon film 61 is deposited over the entire free surface of the resulting structure using an LPCVD process, with the nitride films 45 and 55 still present, as in FIG Fig. 5G shown. The polysilicon film 61 is deposited at a temperature of 550 to 650 ° C. with a thickness of 500 nm in order to fill all the trenches sufficiently and thus to ensure a flat surface.

As illustrated by FIG. 5H, the polysilicon film 61 is then etched back to such an extent that the field oxide film 59 is exposed and a flat surface is present. In the etch back step, the nitride film 55 may be the etch stop point.

Thereafter, the surface is the subjected to filling up the trenches poly silicon film 61 of a field oxidation, the polysilicon film by a form thick field oxide film 61 covering 65 as shown in Fig. 5I. At this time, the nitride film 55 is still in the trenches. As a result, the oxide film 53 and the nitride film 55 serve to relieve stresses such as those generated when the thick field oxide film 65 is formed. The covering field oxide film 65 has a thickness of 50 to 300 nm.

Finally, the exposed nitride films 45 and 55 are removed in hot phosphoric acid solution at a temperature of 160 ° C.

In this embodiment, the field oxide film 65 having a large thickness is used as a passivation layer for the polysilicon film 61 .

According to the present invention, the following effects can be achieved the.  

First of all, the problem of those occurring at trench edges Crystal defects can be overcome because of the polysilicon film abge in the trenches at a temperature of 550 to 650 ° C. that is deeper than in the conventional process Ren. Crystal defects occur in the conventional method the lower edges of the trenches as it fills the trenches lend CVD oxide film at high temperatures of 750 to 800 ° C. is trained.

Second, the difficulty that span in a heat cycle process step following the Formation of the isolation areas are generated as the Trenches are filled with polysilicon, the same thermal expansion coefficient shows like the silicon substrate. In the conventional method using the CVD oxide film with a different thermal expansion coefficient efficient than that of the polysilicon film when heat cycle process step creates stresses, causing crystal defective occur.

Third, there is in the invention because of the use of Polysilicon film no longer has the same difficulty as before conventional method in which the CVD oxide film is thawed into an HF solution in one cleaning step damage to the formation of the insulation areas can.

Claims (17)

1. Semiconductor component with a silicon substrate ( 41 ) and with active areas ( 49 ) defined therein and an isolation area structure for isolating the active areas from one another, with:
a trench structure with narrow ( 51 a, 51 b) and wide ( 51 c, 51 d) trenches which are formed in the silicon substrate ( 41 ),
a first insulating film ( 53 ) of small thickness, which is formed on the bottom surface and the side surfaces of the narrow trenches ( 51 a, 51 b) and on the side surfaces of the wide trenches ( 51 c, 51 d),
a second thick-film insulating film ( 59 ) formed at the bottom of the wide trenches,
a nitride film ( 55 ) which covers the first insulating film ( 53 ) both in the narrow and in the wide trenches ( 51 a, 51 b, 51 c, 51 d) and in the wide trenches the opposite edges of the second Insulating film ( 59 ),
a semiconductor film ( 61 ) which fills the narrow trenches ( 51 a, 51 b) and the wide trenches ( 51 c, 51 d),
a third insulating film ( 43 ) of small thickness on the active area, and
a fourth insulating film ( 63 ) formed on the semiconductor film ( 61 ). 2. Semiconductor component according to claim 1, characterized in that the first and the third insulating film ( 53 ; 43 ) are oxide cushion films. 3. Semiconductor component according to one of claims 1 or 2, characterized in that the second insulating film ( 59 ) is a field oxide film. 4. Semiconductor component according to one of claims 1 to 3, characterized in that the semiconductor film ( 61 ) filling the trenches is a polysilium film. 5. Semiconductor component according to one of claims 1 to 4, characterized in that the fourth insulating film ( 63 ) is a thermal oxide film. 6. A semiconductor device according to claim 5, characterized in that the fourth insulating film ( 63 ) is formed such that it acts as a passivation layer for the semiconductor film ( 61 ). 7. A semiconductor device according to claim 1, characterized in that the second insulating film ( 59 ) is 500 nm thick and the fourth insulating film ( 65 ) is a field oxide film with a thickness of 50 to 300 nm. 8. A method for producing a semiconductor component, comprising the following steps:

• - successively forming a first oxide cushion film ( 43 ) and a first nitride film over a silicon substrate ( 41 );
• - Patterning the first nitride film ( 45 ) and the first oxide cushion film ( 43 ) to expose the silicon substrate ( 41 ) in its portions that do not correspond to active areas;
• - Etching the exposed portion of the silicon substrate ( 41 ) to form the several narrow and wide trenches ( 51 a, 51 d; 51 c, 51 d);
• - forming a second oxide cushion film ( 53 ) on the bottom surface and the side surfaces of each of the trenches;
• - forming a second nitride film ( 55 ) over the entire free area of the resulting structure;
• - Deposition of an oxide film ( 57 ) on the second nitride film ( 55 ) and etching back of the oxide film ( 57 ) in such a way that it remains to fill in the narrow trenches ( 51 a, 51 b) and spacers ( 57 ) on the respective side walls the wide trenches ( 51 c, 51 d) forms, while the silicon substrate ( 41 ) is exposed in its sections arranged in the wide trenches ( 51 c, 51 d);
• - Eliminate the remaining oxide film ( 57 ) by immersion in HF solution;
• - Growing a first field oxide film ( 59 ) on the exposed sections from the silicon substrate ( 41 ) in the wide trenches ( 51 c, 51 d) using a first field oxidation process,
• - Forming a polysilicon film ( 61 ) on the entire free surface of the resulting structure to fill all trenches ( 51 a, 51 b; 51 c, 51 d) with the polysilicon film ( 61 );
• - Etching the polysilicon film ( 61 ) in such a way that it completely fills the narrow and wide trenches ( 51 a, 51 b; 51 c, 51 d);
• - Forming a thermal oxide film ( 65 ) over the polysilicon film ( 61 ); and
• - Removing the first nitride film ( 45 ) over the first oxide cushion film ( 43 ) in the active areas.

9. The method according to claim 8, characterized in that the thermal oxide film over the polysilicon film ( 61 ) as a second field oxide film ( 65 ) is formed using a second field oxidation process. 10. The method according to any one of claims 8 or 9, characterized in that the second oxide cushion film ( 53 ) and optionally the first oxide cushion film ( 43 ) serve as voltage-reducing layers in the field oxidation step or in the field oxidation steps. 11. The method according to any one of claims 8 to 10, characterized in that the second nitride film ( 55 ) or the first and the second nitride film ( 45 , 55 ) serve as an oxidation mask in the field oxidation step or in the field oxidation steps. 12. The method according to any one of claims 8 to 12, characterized in that the silicon substrate ( 41 ) for forming the trenches ( 51 c, 51 d) is etched with a depth of 200 to 500 nm. 13. The method according to any one of claims 8 to 12, characterized in that the first field oxide film ( 59 ) has a thickness of 500 nm. 14. The method according to any one of claims 8 to 13, characterized in that the etching back of the oxide film ( 57 ) is carried out by reactive ion etching. 15. The method according to any one of claims 8 to 14, characterized in that the polysilicon film ( 61 ) is formed using chemical vapor deposition at low pressure at a temperature of 550 to 650 ° C. 16. The method according to claim 8 to 15, characterized in that the step of etching the polysilicon film ( 61 ) is carried out under the condition that the first nitride film ( 45 ) is used as the etching stop point. 17. The method according to claim 9, characterized in that the second field oxide film ( 65 ) has a thickness of 50 to 300 nm.