JPH04199656A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH04199656A JPH04199656A JP33120590A JP33120590A JPH04199656A JP H04199656 A JPH04199656 A JP H04199656A JP 33120590 A JP33120590 A JP 33120590A JP 33120590 A JP33120590 A JP 33120590A JP H04199656 A JPH04199656 A JP H04199656A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- groove
- dielectric
- semiconductor substrate
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 34
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 238000000034 method Methods 0.000 claims abstract description 20
- 239000011521 glass Substances 0.000 claims abstract description 10
- 230000008018 melting Effects 0.000 claims abstract description 10
- 238000002844 melting Methods 0.000 claims abstract description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 10
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 7
- 229910052710 silicon Inorganic materials 0.000 abstract description 7
- 239000010703 silicon Substances 0.000 abstract description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 abstract description 4
- 230000003647 oxidation Effects 0.000 abstract description 3
- 238000007254 oxidation reaction Methods 0.000 abstract description 3
- 229910052757 nitrogen Inorganic materials 0.000 abstract description 2
- 239000003989 dielectric material Substances 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- -1 germanium Chemical compound 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
Landscapes
- Local Oxidation Of Silicon (AREA)
- Element Separation (AREA)
Abstract
Description
この発明は、例えば素子を電気的に分離するために半導
体基板に溝が形成される半導体装置の製造方法に関する
。The present invention relates to a method of manufacturing a semiconductor device in which grooves are formed in a semiconductor substrate, for example, to electrically isolate elements.
近年、集積回路等の半導体装置の製造において、半導体
基板に比較的深い溝を形成する工程が重要となっている
。この溝は、例えば半導体装置に含まれる素子を電気的
に分離するため等に使用される。
第2図は、上述のような溝が形成される従来の半導体装
置の一例を示す。第2図を参照するに、シリコン半導体
基板1に形成された溝の側壁にはシリコン酸化膜(5i
02 )から成る絶縁膜2が形成され、絶縁膜2が形成
された溝に多結晶シリコンからなる誘電体3が化学的気
相成長(CVD)法によって埋め込まれ、溝内以外の絶
縁膜2及び誘電体3がエッチバック法によって除去され
、最後に、半導体基板1の表面に熱酸化法によりシリコ
ン酸化膜(5I02 )から成る絶縁膜2が形成され、
素子分離が完了する。In recent years, in the manufacture of semiconductor devices such as integrated circuits, the process of forming relatively deep grooves in semiconductor substrates has become important. This groove is used, for example, to electrically isolate elements included in a semiconductor device. FIG. 2 shows an example of a conventional semiconductor device in which a groove as described above is formed. Referring to FIG. 2, a silicon oxide film (5i
02) is formed, and a dielectric material 3 made of polycrystalline silicon is embedded in the groove in which the insulating film 2 is formed by chemical vapor deposition (CVD), and the insulating film 2 and other parts of the insulating film 2 other than inside the groove are buried. The dielectric 3 is removed by an etch-back method, and finally, an insulating film 2 made of a silicon oxide film (5I02) is formed on the surface of the semiconductor substrate 1 by a thermal oxidation method.
Element isolation is completed.
上述した従来の半導体装置は、第2図に示されているよ
うに、溝上部に窪みが生じる。これは、エッチバック工
程において溝内の物質かオーバーエッチされて生じるも
のであり、エツチングの制御により多少は軽減すること
は可能であるが完全に無くすことは困難である。
また、このような窪みは、以降の素子形成のための成膜
工程、パターニング工程(例えば、配線工程)において
様々な制約や障害を生じさせることになる。
この発明の目的は、溝が形成される半導体装置において
、溝上部の窪みを平坦化できる半導体装置の製造方法を
提供することにある。In the conventional semiconductor device described above, as shown in FIG. 2, a depression is formed in the upper part of the groove. This is caused by over-etching of the material in the trench during the etch-back process, and although it is possible to reduce it to some extent by controlling the etching, it is difficult to eliminate it completely. Further, such depressions cause various restrictions and obstacles in the subsequent film formation process and patterning process (for example, wiring process) for forming elements. SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device in which a groove is formed in which a recess above the groove can be flattened.
上記の目的を達成するために、この発明は、溝に誘電体
が埋め込まれた半導体基板の表面に形成された絶縁膜上
に低融点ガラス膜を形成し、その後、熱処理する。In order to achieve the above object, the present invention forms a low melting point glass film on an insulating film formed on the surface of a semiconductor substrate in which a dielectric is embedded in a groove, and then heat-treats the film.
上述の半導体装置の製造方法においては、上記絶縁膜上
の低融点ガラス膜か、溝中に埋め込まれた誘電体上部の
窪みに充填され、低融点ガラス膜の表面か平坦となり、
半導体基板の表面か平坦になる。In the method for manufacturing a semiconductor device described above, the low melting point glass film on the insulating film or the depression above the dielectric buried in the groove is filled, and the surface of the low melting point glass film is flattened;
The surface of the semiconductor substrate becomes flat.
第1図は、この発明の半導体装置の製造方法の一実施例
を示す。
この方法は、まず、第1図(a)に示されているように
、シリコン半導体基板1に形成された溝の側壁に、シリ
コン酸化膜(5i02 )から成る絶縁膜2を形成し、
絶縁膜2が形成された溝に多結晶シリコンから成る誘電
体3を減圧CVD法により埋め込み、溝内以外の絶縁膜
2及び誘電体3をエッチバック法によって除去し、シリ
コン半導体基板1の表面に熱酸化法によりシリコン酸化
膜(Si20すなわち二酸化硅素)からなる絶縁膜2を
、厚さ例えば500人形成する。
次に、第1図(b)に示されているように、半導体基板
1上の絶縁膜2の表面に、減圧CVD法により例えばP
2O5、濃度が8io1%のPSGSiO2えばIJl
sの厚さに形成する。
次に、上述のように絶縁膜2の表面上にPSGSiO2
成された半導体基板1を拡散炉中に配置し、例えば窒素
N2雰囲気中で、炉内温度1000℃で30分間リフロ
ー(ref’ low)処理する。これにより、第1図
(e)に示されているように、絶縁膜2上のPSGSi
O2溝中に埋め込まれた誘電体3の上部の窪みに充填さ
れ、PSGSiO2面が平坦となり、半導体基板1の表
面が平坦になった。
なお、上記実施例においては、半導体基板1としてシリ
コン半導体基板を使用したが、シリコン以外の例えばゲ
ルマニウム等の半導体であってもよい。
また、上記実施例では、絶縁膜2としてシリコン酸化膜
を使用したが、他の絶縁膜も使用でき、絶縁膜を多層構
造にしてもよい。
また、上記実施例では、分離用誘電体3としては多結晶
シリコンを使用したが、他の誘電体も使用できる。
また、上記実施例では、低融点ガラスとしてPSG膜を
使用したが、他の低融点ガラスも使用できる。
また、上記実施例では、熱処理としてリフロー処理を使
用したか、他の熱処理も使用できる。
要するに、窪みを充填でき、表面か平坦になれば、どの
ような低融点ガラス及び熱処理でもよい。
【発明の効果1
以上の説明から明らかなように、この発明によれば、半
導体装置の溝に埋め込まれた誘電体上に生じる窪みを平
坦にすることができる。したがって、その後の例えば素
子形成のための成膜工程及びパターニング工程等におけ
る制約や障害がなくなる。FIG. 1 shows an embodiment of the method for manufacturing a semiconductor device of the present invention. In this method, first, as shown in FIG. 1(a), an insulating film 2 made of a silicon oxide film (5i02) is formed on the side wall of a trench formed in a silicon semiconductor substrate 1.
A dielectric material 3 made of polycrystalline silicon is buried in the groove in which the insulating film 2 is formed by low-pressure CVD, and the insulating film 2 and dielectric material 3 other than inside the trench are removed by an etch-back method, and the surface of the silicon semiconductor substrate 1 is etched. An insulating film 2 made of a silicon oxide film (Si20, ie, silicon dioxide) is formed to a thickness of, for example, 500 by a thermal oxidation method. Next, as shown in FIG. 1(b), for example, P is applied to the surface of the insulating film 2 on the semiconductor substrate 1 by low pressure CVD.
2O5, PSGSiO2 with a concentration of 8io1%, for example IJl
Form to a thickness of s. Next, as described above, PSGSiO2 is placed on the surface of the insulating film 2.
The semiconductor substrate 1 thus formed is placed in a diffusion furnace, and subjected to a reflow (ref' low) treatment for 30 minutes at a furnace temperature of 1000° C., for example, in a nitrogen N2 atmosphere. As a result, as shown in FIG. 1(e), the PSGSi on the insulating film 2
The recess at the top of the dielectric 3 embedded in the O2 groove was filled, the PSGSiO2 surface became flat, and the surface of the semiconductor substrate 1 became flat. In the above embodiment, a silicon semiconductor substrate is used as the semiconductor substrate 1, but a semiconductor other than silicon, such as germanium, may be used. Further, in the above embodiment, a silicon oxide film is used as the insulating film 2, but other insulating films can also be used, and the insulating film may have a multilayer structure. Further, in the above embodiment, polycrystalline silicon is used as the isolation dielectric 3, but other dielectrics can also be used. Further, in the above embodiments, a PSG film was used as the low melting point glass, but other low melting point glasses can also be used. Further, in the above embodiments, reflow treatment was used as the heat treatment, but other heat treatment may also be used. In short, any low melting point glass and heat treatment may be used as long as it can fill the recesses and provide a flat surface. Effects of the Invention 1 As is clear from the above description, according to the present invention, it is possible to flatten a depression formed on a dielectric buried in a groove of a semiconductor device. Therefore, there are no restrictions or obstacles in the subsequent film formation process, patterning process, etc. for element formation.
第1図は、この発明による半導体装置の製造方法の一実
施例の各工程を示す断面図、第2図は、従来の半導体装
置の一例を示す断面図である。
1;シリコン半導体基板
2;絶縁膜(シリコン酸化膜)
3:誘電体(多結晶シリコン)
4:低融点ガラス(PSG膜)
代理人 弁理士 佐 藤 正 美
第1図FIG. 1 is a sectional view showing each step of an embodiment of a method for manufacturing a semiconductor device according to the present invention, and FIG. 2 is a sectional view showing an example of a conventional semiconductor device. 1; Silicon semiconductor substrate 2; Insulating film (silicon oxide film) 3: Dielectric (polycrystalline silicon) 4: Low melting point glass (PSG film) Agent: Masami Sato, patent attorney Figure 1
Claims (1)
膜を形成する工程と、 前記絶縁膜上に低融点ガラス膜を形成する工程と、 前記絶縁膜上に低融点ガラス膜が形成された半導体基板
を熱処理する工程と を含む半導体装置の製造方法。[Scope of Claims] A step of forming a groove in a semiconductor substrate, a step of embedding a dielectric in the groove, a step of forming an insulating film on the surface of the semiconductor substrate in which the dielectric is embedded in the groove, and the insulating layer. A method for manufacturing a semiconductor device, comprising: forming a low melting point glass film on the film; and heat treating the semiconductor substrate on which the low melting point glass film is formed on the insulating film.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP33120590A JPH04199656A (en) | 1990-11-29 | 1990-11-29 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP33120590A JPH04199656A (en) | 1990-11-29 | 1990-11-29 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH04199656A true JPH04199656A (en) | 1992-07-20 |
Family
ID=18241070
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP33120590A Pending JPH04199656A (en) | 1990-11-29 | 1990-11-29 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH04199656A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE4340226A1 (en) * | 1993-11-25 | 1995-06-01 | Gold Star Electronics | Semiconductor element having reduced bird beak formation |
NL9500370A (en) * | 1994-02-24 | 1995-10-02 | Mitsubishi Electric Corp | Semiconductor device and method for its manufacture. |
-
1990
- 1990-11-29 JP JP33120590A patent/JPH04199656A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE4340226A1 (en) * | 1993-11-25 | 1995-06-01 | Gold Star Electronics | Semiconductor element having reduced bird beak formation |
DE4340226C2 (en) * | 1993-11-25 | 2002-03-14 | Gold Star Electronics | Component with isolation region structure and method for producing the same |
NL9500370A (en) * | 1994-02-24 | 1995-10-02 | Mitsubishi Electric Corp | Semiconductor device and method for its manufacture. |
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