JPS59159544A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To prevent a film from reducing and a layer resistance from varying by using as an interlayer inslating film between a polycrystalline silicon layer and upper wirins an insulating film of 3-layer structure of silicon oxidized film- silicon nitrided film-PSG film and reflowing the PSG film of low density. CONSTITUTION:A polycrystalline silicon film is selectively formed on a semiconductor substrate 1, the surface is thermally oxidized to form a silicon oxidized film 7. Then, a silicon nitrided film 8 is grown on the film 7, a phosphorus glass layer 9 is grown on the film 8, the layer 9 is softened, thereby smoothing the stepwise difference on the surface of the substrate 1. The smoothing step is at 950 deg.C or lower and of oxidizing at high pressure is oxidative atmosphere of 4-10kg/cm<2>.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and more particularly to a semiconductor device including electrodes, wiring, or resistance elements made of polycrystalline silicon on a semiconductor substrate.

Silicon G-1-MO8 IC is well known as a semiconductor device using polycrystalline silicon. silicon game)
In MOS IC, polycrystalline silicon doped with impurities is used as gate electrodes, wiring, and resistance elements, and self-alignment of source and drain to the gate and multilayer wiring structure of polycrystalline silicon wiring and metal wiring are possible.↓
It is possible to downsize the device and improve its performance. Bipolar I
Also in C, resistance elements made of polycrystalline silicon have a smaller temperature coefficient than diffused resistors formed in a single crystal substrate, and bias dependence is reduced because there is no effect of the optical layer at the PN junction. It is used as one of the resistive elements due to its advantages such as:

However, in semiconductor devices using polycrystalline silicon,
The first problem is that the upper metal wiring in the multilayer wiring structure is disconnected at the stepped portion at the end of the polycrystalline silicon pattern. Recently, anisotropic etching by reactive ion etching is used for etching polycrystalline silicon, which is effective for miniaturizing patterns, and the edges of polycrystalline silicon have a sharper shape. Furthermore, the metal wiring itself that crosses this polycrystalline silicon pattern is also required to be narrow in width. As a result, breaks in the metal wiring are more likely to occur.

As a countermeasure against this problem, a phosphosilicate glass (PSG) layer glue flow method is known. In other words, since a PSG film containing a high concentration of phosphorus softens and becomes fluid at high temperatures, a SG film is formed on a polycrystalline solicon pattern95.
The surface step at the end of the polycrystalline silicon can be smoothed by high-temperature treatment at 0°C or higher (hereinafter referred to as P
SG IJ Afro-method).

From 1 to 1, there are many problems with this PSO reflow method. In other words, there are ways to make the PSG film easier to reflow, such as: ■ increasing the heat treatment temperature (>1000°C), ■ oxidizing at high pressure, and ■ increasing the phosphorus concentration in the PSG film. A problem that arises is that the high temperature heat treatment deepens the diffusion layer diffused into the single crystal substrate, for example the source/drain region in a silicon gate MO8IC. Obtaining shallow junctions along with finer patterns will lead to smaller semiconductor devices and higher performance.
The above-mentioned high temperature heat treatment becomes an obstacle to this. Next, the problem that occurs in (■) is that high-pressure oxidation increases the oxidation rate of single-crystal silicon and polycrystalline silicon, resulting in a large reduction in the polycrystalline silicon film, and as a result, the introduced impurities enter the oxide film. This is due to the fact that the layer resistance changes greatly due to the incorporation. The problems caused by (2) are: 1) If the phosphorus concentration of the SG film is high, corrosion of the aluminum wiring is likely to occur when aluminum is used as the metal wiring.

The present invention provides a highly reliable semiconductor device and a method for manufacturing the same by solving the above-mentioned drawbacks caused by using a PSG film.

That is, the present invention uses an insulating film with a three-layer structure of a silicon oxide film, a silicon nitride film, and a PSG film as an interlayer insulating film between a polycrystalline silicon layer formed on a semiconductor substrate and an upper wiring. It is characterized by reflowing a relatively low-concentration PSG film using high-pressure oxidation at extremely low temperatures.

The silicon oxide film has the function of alleviating the strain between the silicon nitride film and the polycrystalline silicon layer, and the silicon nitride film prevents the intrusion of 02 and 112 during high-pressure oxidation. Changes in layer resistance of the diffusion layer, thinning of the polycrystalline silicon film, and changes in layer resistance can be prevented. If high-pressure oxidation is used, even a PSG film with a relatively low concentration can be reflowed, and the heat treatment temperature can be lowered, so shallow junctions can be maintained, making it possible to downsize and improve the performance of the device.

Below, as an embodiment of the present invention, a silicon gate MO8IC
I will explain about it.

FIGS. 1(a) to 1(d) are cross-sectional views of a semiconductor device according to its manufacturing process. First, as shown in FIG. 1(a), a field oxide film 2 of about 1.71 m long is formed on a silicon substrate 1, and a gate oxide film 3 is formed by opening a window in the field oxide film. Thereafter, a polycrystalline silicon film of approximately 600 nm is grown on the surface of the silicon substrate by the LPCV'D method, and using the photo/cyst pattern 6 as a mask, the polycrystalline silicon jJ% is etched by the site-try etching method to form the gate electrode 4a and wiring. Alternatively, a resistive element 4b is formed. Openings 15 are formed by etching the gate oxide film with buffered hydrofluoric acid for the source and drain regions of Shichinoshun.

Next, as shown in FIG. 1), impurities such as cibron, phosphorus, or arsenic are introduced by ion implantation or thermal diffusion to form source and drain regions 5, 5'. At this time, the above impurities are also introduced into the polycrystalline silicon.

Then, the silicon substrate is thermally oxidized I2 in an oxidizing atmosphere at 900°C to 1000°C to form a silicon oxide film on the substrate surface of the source and drain regions 5 and 5', and at the same time, a silicon oxide film 7 is formed on the surface of the polycrystalline silicon 4al and 4b. Approximately 500
A°Shadow formation.

After that, as shown in Figure 1(C), LPCV is placed on the substrate.
A silicon gate 8 is grown to a thickness of 500 to 100 ON using the D method, and then a PSG film 9 containing phosphorus at a concentration of 1 to 12 mo1 is formed to a thickness of about 1 μm using an atmospheric pressure CVD method or the like. Next, a contact pole pattern is formed, and the PSG film 9 is selectively etched using a 1-etching method or the like. Thereafter, high-pressure oxidation, i.e., 1-12-
02 or dry 02 in an oxidizing atmosphere to reflow the 1''SG film.

Thereafter, as shown in FIG. 1(d) of the cylinder 1, the silicon nitride film 8 and the silicon oxide film in the contact hole portion are etched using plasma etching and buffer hood hydrofluoric acid, respectively, to form a contact hole 10. Next, aluminum is formed on the surface of the substrate by vapor deposition or the like, and a pattern is formed to form aluminum wiring 11. This results in a silicon gate MO8IC.

According to the present invention described above, even if high-pressure oxidation is performed, the polycrystalline silicon layer 4al 4b is formed by the silicon nitride film 8.
The film thickness layer resistance does not change, and the PEG film 9 can be reflowed even at low temperatures by high-pressure oxidation, and the junction depth of the source and drain regions 5.5' does not change. Furthermore, the oxide film 7 of the polycrystalline silicon layers 4a and 4b eases the strain between it and the nitride film 8.

The above embodiment is a silicon gate MO8 with a single layer structure.
1c, the present invention can also be applied to MOS ICs having a polysilicon structure of two or more layers. Furthermore, the present invention can be applied to bipolar type and other semiconductor devices. In short, the present invention is applicable to all semiconductor devices in which a polycrystalline silicon layer is formed directly or via an insulating film on a substrate, and therefore is not limited to the embodiments.

[Brief explanation of drawings]

FIGS. 1(a) to 1(d) show an embodiment of the present invention in step 11.
It is a sectional view of the semiconductor device 16' shown in the door. 1...Silicon substrate, 2...Field oxide film, 3...Gate oxidation J4.4a...
...Polycrystalline silicon gate! Extreme, 41)...
・Polycrystalline silicon wiring and resistance, 5...source region, 5'...drain region, 6...
...Photoresist, 7...Silicon oxide film,
8...Silicon opening film, 9...Phosphorsilicate glass layer, 10...Contact hole, 11...Curved aluminum heald, 15...Source, Drain forming window. -1 ship

Claims (3)

[Claims] (1) In a semiconductor device having polycrystalline silicon on a semiconductor substrate, an interlayer insulating film between the polycrystalline silicon layer and the upper wiring includes a silicon oxide film formed by thermally oxidizing the surface of the polycrystalline silicon; A semiconductor device characterized in that a film including a silicon nitride film formed on a silicon oxide film and a phosphorous glass layer further formed thereon is used. (2) A step of selectively forming a polycrystalline silicon film on a semiconductor substrate, a step of thermally oxidizing the surface of the polycrystalline silicon film to form a silicon oxide film, and a step of forming a silicon nitride film on the silicon oxide film. a step of growing a phosphorus glass layer on the silicon nitride film; and a step of softening the phosphorus glass layer to clear the stepped portion on the surface of the semiconductor substrate. A method for manufacturing a semiconductor device. (3) The smoothing step is performed by high-pressure oxidation in an oxidizing atmosphere at a temperature of 950'C or lower and a pressure of 4 Kf/c7 to 10 Kg/cm. A method for manufacturing a semiconductor device.