JPS5842254A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5842254A
JPS5842254A JP14049481A JP14049481A JPS5842254A JP S5842254 A JPS5842254 A JP S5842254A JP 14049481 A JP14049481 A JP 14049481A JP 14049481 A JP14049481 A JP 14049481A JP S5842254 A JPS5842254 A JP S5842254A
Authority
JP
Japan
Prior art keywords
film
impurity
applying
containing glass
glass film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14049481A
Other languages
Japanese (ja)
Inventor
Ikuo Kawamata
川又 郁夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP14049481A priority Critical patent/JPS5842254A/en
Publication of JPS5842254A publication Critical patent/JPS5842254A/en
Pending legal-status Critical Current

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Weting (AREA)

Abstract

PURPOSE:To obtain a metal electrode and wiring of semiconductor device having always favorable ohmic contact by a method wherein the heat treatment is performed after a glass film containing impurities is formed on a mask layer having the extremely lower etching rate than the glass film containing impurities. CONSTITUTION:The silicon nitride film 7 is made to grow applying the chemical vapor phase growth method. After then, the phospho silicate glass (PSG) film 4 is made to grow applying the CVD method, and moreover patterning of the PSG film 4 is performed applying usual photolithography to form an electrode contact window. Then the heat treatment is performed at about 950- 1,100 deg.C to make the PSG film 4 to be molten and to be softened. Accordingly the PSG film 4 is made to have the smooth shape having roundness wholly. Then the whole surface is etched applying the plasma etching method using carbon tetrafluoride (CF4) as the etchant. Etching thereof is continued till the mask film 7 is removed.

Description

【発明の詳細な説明】 本発明は半導体装置の製造方法に係り、特に不純物含有
ガラスからなる保護膜を有する半導体装置を製造する方
法の改曳に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a modification of a method for manufacturing a semiconductor device having a protective film made of impurity-containing glass.

従来、例えば絶縁ゲー)It電界効果半導体装置におい
ては、その絶縁及び保護のため、不純物含有ガラス膜、
轡に燐硅酸ガラス膜(以下P2O膜と称する)t−形成
することが多い、モしてPSG膜を形成した後、熱処理
を行ってP2O膜を溶融軟化させることにより、半導体
基板表面に形成された段を滑らかにして金属配線を形成
した時の断線を防止する方法が用いられているが、この
場合以下のような不都合が発生する。これを第1図及び
第2図を用いて説明する。
Conventionally, in an IT field effect semiconductor device (for example, an insulating film), impurity-containing glass films,
A phosphosilicate glass film (hereinafter referred to as a P2O film) is often formed on the substrate.After forming a PSG film, heat treatment is performed to melt and soften the P2O film, thereby forming it on the surface of a semiconductor substrate. A method has been used to prevent wire breakage when metal wiring is formed by smoothing the stepped steps, but in this case, the following problems occur. This will be explained using FIGS. 1 and 2.

第1図は、従来構造に於けるコンタクト部の断面図であ
り、1はN@シリコン半導体基板、2は二酸化シリコン
膜、3はP@不純物導入領域、4はP2O膜、5は電極
コンタクト窓である。この状態はP80Il[4t−形
成した後、写真蝕刻法によ31、PaG膜4及び二酸化
シリコン膜2に電極又は配線用コンタクト窓5t−あけ
九段隔の断面図である1次に熱処理を行うことによりP
8G膜4が溶融軟化して全体に丸味を帯び滑らかな形状
となる。ところが、この熱処理によfiP8G膜4から
燐が外方拡散(OUT DIFFUSION)L、それ
が電極又扛配線用コンタクト窓5内に露出しているP型
不純物、領域3の表面に拡散されてN型不純物領域6が
形成されてしまい、この;ンタクト部5のシリコン基板
表面ICP−N接合が生成されてしまう、その状態管筒
2図に示す、そして、この状態においては金属電極を形
成した場合に良好なオーミ、り・コンタクトをとること
ができない。
FIG. 1 is a cross-sectional view of a contact part in a conventional structure, where 1 is an N@ silicon semiconductor substrate, 2 is a silicon dioxide film, 3 is a P@ impurity doped region, 4 is a P2O film, and 5 is an electrode contact window. It is. In this state, after forming P80Il[4t-, 31, PaG film 4 and silicon dioxide film 2 are subjected to first heat treatment as shown in FIG. By P
The 8G film 4 is melted and softened to have a rounded and smooth shape. However, as a result of this heat treatment, phosphorus is diffused out from the fiP8G film 4 (OUT DIFFUSION), and it is diffused into the P-type impurity exposed in the contact window 5 for the electrode or strip wiring, and into the surface of the region 3. A type impurity region 6 is formed, and an ICP-N junction is generated on the silicon substrate surface of the contact portion 5, as shown in FIG. 2, and in this state, when a metal electrode is formed It is not possible to make good contact with the user.

尚、電極コンタクト窓5t−形成する場合に、コンタク
トの工、チングt−P8G膜だけに留め、その下の二酸
化シリコン膜2を残した状態でこの熱処理を行えば良−
と考えられようが、現在、そのような場合にP8G膜4
を選択的にエツチングすることは不可能であり、どうし
ても二酸化シリコン11121でエツチングせざる會え
ない状態にある。
In addition, when forming the electrode contact window 5t, it is sufficient to perform this heat treatment with the contact processing limited to only the t-P8G film and the underlying silicon dioxide film 2 remaining.
However, currently, in such cases, P8G film 4
It is impossible to selectively etch the silicon dioxide 11121, and there is no choice but to etch the silicon dioxide 11121.

本発明の目的は、この上記のような従来の欠点ある。The object of the present invention is to overcome the above-mentioned drawbacks of the prior art.

本発明の特徴は、例えば−導電性を有する不純物領域が
形成され九半導体基板表面上に、不純物含有ガラス膜の
エッチャントとエッチャントを異にして同時にはエツチ
ングされないか、あるいは、この不純物含有ガラス膜よ
り工、チングレートが著しく低い物質からなるマスク層
を形成する工程と、そのマスク層の上にこの不純物含有
ガラス膜を形成し、その不純物含有ガラス膜のみに、不
純物領域とのコンタクト窓をあけ、さらに熱処理を行っ
て不純物含有ガラス膜の表面全円滑化させる工程と、こ
の不純物含有ガラス膜をエツチングのマスクとしてマス
ク層にコンタクト窓をあけ、しかる後、電極配線を形成
する工程とを含む半導体装置の製造方法にある。
A feature of the present invention is, for example, when an impurity region having conductivity is formed on the surface of a semiconductor substrate, the impurity-containing glass film is etched using a different etchant and the etchant is not etched at the same time, or the impurity-containing glass film is A process of forming a mask layer made of a material with a significantly low ching rate, forming this impurity-containing glass film on the mask layer, and opening a contact window with the impurity region only in the impurity-containing glass film. A semiconductor device comprising the steps of: further performing heat treatment to smooth the entire surface of the impurity-containing glass film; and using the impurity-containing glass film as an etching mask to open a contact window in the mask layer, and then forming electrode wiring. It is in the manufacturing method.

すなわち、本発明はP801iの如き不純物含有ガラス
膜に電極コンタクト窓を形成してから熱処理を行うても
前述の如1p−n接合は形成され表いよう#C%そして
良好なオーミックコンタクトがとれた電極を有する半導
体装置を得られるようにするものであり、以下これを詳
細に説明する。
That is, in the present invention, even if an electrode contact window is formed on an impurity-containing glass film such as P801i and then heat treatment is performed, a p-n junction as described above is formed. This makes it possible to obtain a semiconductor device having electrodes, and this will be explained in detail below.

第3図(7)乃至に)は本発明の一実施例の工程説明図
であり、次にこれ等の図を参照しつつ説明する。
FIGS. 3(7) to 3) are process explanatory diagrams of an embodiment of the present invention, and the following description will be made with reference to these diagrams.

第3図(7):通常の技法を適用し、n型シリコン半導
体基板l上にフィールドの二酸化シリコン膜2、ソース
領域或いはドレイン領域であるP型不純物導入領域3、
ゲート酸化膜8、シ1】コンゲート9が形成された状態
を表わしている。
FIG. 3 (7): Applying a conventional technique, a field silicon dioxide film 2, a P-type impurity doped region 3 serving as a source region or a drain region, are formed on an n-type silicon semiconductor substrate l.
A state in which a gate oxide film 8 and a composite gate 9 are formed is shown.

第3図((イ):さらに化学気相成長法を適用し、窒化
シリコン膜7t−例えば厚さ500人〜100OAに成
長させる。
FIG. 3 ((A): Chemical vapor deposition is further applied to grow the silicon nitride film 7t to a thickness of, for example, 500 to 100 OA.

第3図(fjIニジかる後CVD法を適用してP8G膜
4を例えば厚さ7000λ〜15000λ程WILに成
長させ、さらに通常のフォト・リゾグラフィ’fc適用
してPSGS着膜パターンエングを行ない電極コンタク
ト窓を形成する。
Figure 3 (After fjI coating, the CVD method is applied to grow the P8G film 4 to a thickness of, for example, 7,000λ to 15,000λ, WIL, and then the PSGS film is pattern-engraved by applying normal photolithography'fc to form electrode contacts. form a window.

第3図に);次に温[950℃〜1100℃程度の熱処
理を施して、P2O3[4の溶融軟化を行なう。
(See FIG. 3); Next, heat treatment is performed at a temperature of about 950°C to 1100°C to melt and soften the P2O3[4.

これに依り、PSGS着膜全体的に丸味を帯びた滑らか
な形状になる。この工程でP8G膜4から燐が外方拡散
しても、不純物導入領域3上にはマスク膜7が在るから
、その燐が領域3に入り込んでp−n  接合を形成す
るおそれはない。
As a result, the entire PSGS deposited film has a rounded and smooth shape. Even if phosphorus diffuses outward from the P8G film 4 in this step, since the mask film 7 is present on the impurity-introduced region 3, there is no fear that the phosphorus will enter the region 3 and form a pn junction.

第3図t!6:次にエッチャントとして四弗化炭素(C
F4)を用いたプラズY@工、チング法を適用して全f
fi’tエツチングする。そして、このエツチングはマ
スク膜7が除去されるまで行なう。この場合の工、チン
グレートは、P2O:窒化シリコン=1:100@度で
あるから、PSGS着膜殆んどエツチングされないうち
にマスク膜7を除去できる。この工程を経ることに依ハ
電極コンタクト窓sFi完成され、その内部にはシリコ
ン−面が露出される。
Figure 3 t! 6: Next, carbon tetrafluoride (C
F4) using Plas Y @ engineering, applying the ching method to obtain all f
fi't etching. This etching is continued until the mask film 7 is removed. Since the etching rate in this case is P2O:silicon nitride=1:100 degrees, the mask film 7 can be removed before the PSGS deposited film is hardly etched. Through this process, the electrode contact window sFi is completed, and the silicon surface is exposed inside the window.

この後、通常の技法を適用して、例えばアルミニウム等
の金属電極、配線を形成して装置を完成させる。
Thereafter, conventional techniques are applied to form metal electrodes, such as aluminum, and wiring to complete the device.

以上の説明で判るように、本発明によれば、不純物含有
ガラス膜に電極コンタクト窓を形成してから澄融軟化し
てその表面を円滑にする加工を行なりても、その際外方
拡散された不純物が半導体基板中に取り込まれて無用な
接合を形成することは皆無になるので、常に良好なオー
ミックコンタクトのとれた金属電極・配線を有する半導
体装置を得ることが出来る。
As can be seen from the above explanation, according to the present invention, even if an electrode contact window is formed on an impurity-containing glass film and then the surface is smoothed by clearing and softening, outward diffusion Since there is no possibility that the impurities introduced into the semiconductor substrate are incorporated into the semiconductor substrate and form unnecessary junctions, it is possible to obtain a semiconductor device having metal electrodes and wiring with good ohmic contact at all times.

なお本実施例では窒化シリコン膜を不純物含有ガラス膜
として使用したが、マスク膜としては不純物含有ガラス
、即ち本実施例ではPEGであるが、その工、チャント
でエツチングされないか成りはエツチングレートが著し
く低i物質の膜であれば良く、窒化シリコンには限定さ
れない。
In this example, a silicon nitride film was used as the impurity-containing glass film, but as the mask film, impurity-containing glass, that is, PEG in this example, was used, but unless it is etched by the process or chant, the etching rate will be extremely high. It may be a film of a low i material, and is not limited to silicon nitride.

【図面の簡単な説明】[Brief explanation of the drawing]

w、1図及び第2図は従来例の説明図、第3図(7)乃
至(4)は本発明による実施例の工程説明図をそれぞれ
表わす。 なお図に於いて、 1・・・・・・半導体基板、2・・・・・・二酸化シリ
プン膜、3・・・・・・不純物導入領域、4・・・・・
・不純物含有ガラス膜、5・・・・・・電極コンタクト
窓、6・・・・・・不純物導入領域3とは逆の導伝ff
1t示す不純物導入領域、7・・・・・・マスク膜、8
・・・・・・ゲート酸化膜、9・・・・・・シリコンゲ
ート電極、tそれぞれ示す。 第1 図 第2図  63 第3図
w, Figures 1 and 2 are explanatory views of the conventional example, and Figures 3 (7) to (4) are process explanatory views of the embodiment according to the present invention. In the figure, 1... Semiconductor substrate, 2... Silicon dioxide film, 3... Impurity introduced region, 4...
- Impurity-containing glass film, 5... electrode contact window, 6... conduction ff opposite to impurity introduction region 3
Impurity introduced region shown as 1t, 7...Mask film, 8
. . . Gate oxide film, 9 . . . Silicon gate electrode, t, respectively. Figure 1 Figure 2 63 Figure 3

Claims (1)

【特許請求の範囲】[Claims] 基板上に不純物含有ガラス膜の工、チャントと工、チャ
ント管異にして同時にはエツチングされVいか、あるい
は、該不純物含有ガラス膜より工、チングレートが著し
く低い物質からなるマスク層を形成する工程と、該マス
ク層の上に前記不純物含有ガラス膜を形成し、該不純物
含有ガラス膜のみに開口を形成し、さらに熱処理を行っ
て該不純物含有ガラス膜の表面を円滑化させる工程と、
該不純物含有ガラス膜をエツチングのマスクとして前記
マスク層に開口を形成し、しかる後電極配線を形成する
工程とを含むことを特徴とする半導体装置の製造方法。
A step of forming an impurity-containing glass film on a substrate, etching a chant tube, and etching the chant tube at the same time, or forming a mask layer made of a material whose etching rate is significantly lower than that of the impurity-containing glass film. forming the impurity-containing glass film on the mask layer, forming an opening only in the impurity-containing glass film, and further performing heat treatment to smooth the surface of the impurity-containing glass film;
A method of manufacturing a semiconductor device, comprising the steps of forming an opening in the mask layer using the impurity-containing glass film as an etching mask, and then forming an electrode wiring.
JP14049481A 1981-09-07 1981-09-07 Manufacture of semiconductor device Pending JPS5842254A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14049481A JPS5842254A (en) 1981-09-07 1981-09-07 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14049481A JPS5842254A (en) 1981-09-07 1981-09-07 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5842254A true JPS5842254A (en) 1983-03-11

Family

ID=15269923

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14049481A Pending JPS5842254A (en) 1981-09-07 1981-09-07 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5842254A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63111668A (en) * 1986-10-30 1988-05-16 Mitsubishi Electric Corp Semiconductor device and manufacture of the same
JPH02290044A (en) * 1989-02-17 1990-11-29 Matsushita Electron Corp Manufacture of semiconductor device
US5037777A (en) * 1990-07-02 1991-08-06 Motorola Inc. Method for forming a multi-layer semiconductor device using selective planarization
US5399532A (en) * 1991-05-30 1995-03-21 At&T Corp. Integrated circuit window etch and planarization
US5538922A (en) * 1991-06-03 1996-07-23 Motorola, Inc. Method for forming contact to a semiconductor device
JP2006193946A (en) * 2005-01-12 2006-07-27 Mitani Mokkosho:Kk Work tool

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5445583A (en) * 1977-09-19 1979-04-10 Matsushita Electric Ind Co Ltd Manufacture for semiconductor device
JPS55107267A (en) * 1979-02-08 1980-08-16 Toshiba Corp Manufacture of complementarity mos semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5445583A (en) * 1977-09-19 1979-04-10 Matsushita Electric Ind Co Ltd Manufacture for semiconductor device
JPS55107267A (en) * 1979-02-08 1980-08-16 Toshiba Corp Manufacture of complementarity mos semiconductor device

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63111668A (en) * 1986-10-30 1988-05-16 Mitsubishi Electric Corp Semiconductor device and manufacture of the same
JPH02290044A (en) * 1989-02-17 1990-11-29 Matsushita Electron Corp Manufacture of semiconductor device
US5037777A (en) * 1990-07-02 1991-08-06 Motorola Inc. Method for forming a multi-layer semiconductor device using selective planarization
US5399532A (en) * 1991-05-30 1995-03-21 At&T Corp. Integrated circuit window etch and planarization
US5538922A (en) * 1991-06-03 1996-07-23 Motorola, Inc. Method for forming contact to a semiconductor device
JP2006193946A (en) * 2005-01-12 2006-07-27 Mitani Mokkosho:Kk Work tool

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