JPS62160730A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS62160730A
JPS62160730A JP297586A JP297586A JPS62160730A JP S62160730 A JPS62160730 A JP S62160730A JP 297586 A JP297586 A JP 297586A JP 297586 A JP297586 A JP 297586A JP S62160730 A JPS62160730 A JP S62160730A
Authority
JP
Japan
Prior art keywords
film
substrate
forming
psg
region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP297586A
Other languages
Japanese (ja)
Inventor
Katsuyuki Inayoshi
稲吉 勝幸
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP297586A priority Critical patent/JPS62160730A/en
Publication of JPS62160730A publication Critical patent/JPS62160730A/en
Pending legal-status Critical Current

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To prevent diffusion of phosphorus atoms, by forming an SiO2 film, which has a form that is protruded to the side end part of a PSG film, so as to wrap the side end part of the PSG film, which is formed for the purpose of flattening the surface of a substrate, and in which a window is formed for forming an electrode window. CONSTITUTION:An SiO2 film 22 is formed on a substrate 21. A photoresist film 24, in which a base forming region 23 is opened, is formed. Thereafter, boron atom ions are implanted. Then, a PSG film 25 is formed. Thereafter the PSG film is dissolved, and a glass flow film is obtained. A first SiO2 film 26 is further formed by a CVD method. A window is formed through the SiO2 film 22, the PSG film 25 and the SiO2 film 26 on a base-contact forming region 28 and a collector contact region 29. Thereafter, a second CVD SiO2 film 30 is formed. Then, the CVD SiO2 film 30 undergoes anisotropic etching. The side end part of the PSG film 25, in which the window is provided, is surrounded with the CVD SiO2 film 30. Then the surface is coated with a poly Si film 31. Arsenic ion atoms are implanted, and an emitter region 27 and a collector contact region 29 are formed. Since the phosphorus atoms in the glass flow film are not diffused in the base contact film, the highly reliable device can be obtained.

Description

【発明の詳細な説明】 〔概要〕 半導体装置の製造方法であって、半導体素子形成領域を
設けたSi基板上にガラスフローした燐珪酸ガラス膜(
以下PSG膜と称する)を形成して基板表面を平坦化す
る工程を有する半導体装置の製造に於いて、不純物原子
を導入するために窓開きしたPSG膜の側端部を二酸化
シリコン(SiO2)膜にて包み込み、このPSG膜上
に形成され、電極形成用の〜配線膜のHにSi基板のS
tが浸食されないように設けたポリSi膜に、前記PS
G膜の燐原子が拡散し、更に基板のベースコンタクト領
域内に導入されるのを防止した製造方法。
[Detailed Description of the Invention] [Summary] A method for manufacturing a semiconductor device, which comprises forming a phosphosilicate glass film (
In the manufacturing of semiconductor devices, which includes a process of forming a PSG film (hereinafter referred to as a PSG film) and planarizing the substrate surface, the side edges of the PSG film, which are opened to introduce impurity atoms, are covered with a silicon dioxide (SiO2) film. The S of the Si substrate is formed on the PSG film, and the H of the wiring film for forming electrodes is formed on the PSG film.
The poly-Si film provided to prevent erosion of the PS
A manufacturing method that prevents phosphorus atoms in the G film from diffusing and further introducing into the base contact region of the substrate.

〔産業上の利用分野〕[Industrial application field]

本発明は半導体装置の製造方法に係り、特に素子を形成
した基板上を平坦にするため、ガラスフローしたPSG
膜を用いたバイポーラ型半導体装置の製造方法に関する
The present invention relates to a method for manufacturing a semiconductor device, and in particular, in order to flatten a substrate on which an element is formed, a glass-flowed PSG is used.
The present invention relates to a method for manufacturing a bipolar semiconductor device using a film.

MO3型半導体装置を形成する場合、ゲート電極上にP
SG膜を形成後、このPSG膜をウェット酸化の雰囲気
で高温処理し、このPSG膜のガラスを溶融してガラス
フローし、このガラスフローしたPSG膜でゲート電極
上に緩い勾配を持つ絶縁膜を形成し、この上に電極形成
用全屈膜を形成することで、ゲート電極上の肩の部分上
の金属膜に亀裂が発生しない方法が取られている。
When forming an MO3 type semiconductor device, P is placed on the gate electrode.
After forming the SG film, this PSG film is treated at high temperature in a wet oxidation atmosphere, the glass of this PSG film is melted and glass flowed, and this glass flowed PSG film is used to form an insulating film with a gentle slope on the gate electrode. A method has been adopted in which cracks do not occur in the metal film on the shoulder portion of the gate electrode by forming a full-reflection film for electrode formation thereon.

このような素子形成領域を設けたSi基板の表面を平坦
にすることは、バイポーラ型半導体装置を形成する場合
でも要望されており、基板上を平坦にするために、この
ようなガラスフローしたPSGH’Aを基板上に形成し
た場合に、エミッタ領域を拡散で形成する際、このPS
G膜中の燐原子がベース領域に拡散してコンタクト形成
ができなくなる不都合を除去することが要望されている
Flattening the surface of a Si substrate with such an element formation region is required even when forming a bipolar semiconductor device, and in order to flatten the surface of the substrate, such a glass-flowed PSGH is used. 'A is formed on the substrate, and when forming the emitter region by diffusion, this PS
It is desired to eliminate the disadvantage that phosphorus atoms in the G film diffuse into the base region, making it impossible to form a contact.

〔従来の技術〕 このような半導体素子形成領域が形成されたSi基板を
平坦にするためにPSG膜を用いたバイポーラ型半導体
装置の従来の製造方法について第7図を用いながら説明
する。
[Prior Art] A conventional method for manufacturing a bipolar semiconductor device using a PSG film to flatten a Si substrate on which a semiconductor element formation region is formed will be described with reference to FIG.

第7図に示すように従来のバイポーラ型半導体装置の製
造は、P型のSi基板1に燐等の原子を拡散して高濃度
のN型の埋込み層2を形成後、該基板1上にN型のSi
エピタキシャル層3を形成する。
As shown in FIG. 7, conventional bipolar semiconductor device manufacturing involves the formation of a highly concentrated N-type buried layer 2 by diffusing atoms such as phosphorus into a P-type Si substrate 1, and then forming a highly concentrated N-type buried layer 2 on the substrate 1. N-type Si
An epitaxial layer 3 is formed.

その後、基板に硼素(B)等のP型の不純物原子を拡散
してP型の素子間分離領域4を形成する。
Thereafter, P-type impurity atoms such as boron (B) are diffused into the substrate to form P-type element isolation regions 4.

次いでエピタキシャル層3内にP型の不純物原子を導入
してP型のベース領域5を所定のパターンに形成する。
Next, P-type impurity atoms are introduced into the epitaxial layer 3 to form a P-type base region 5 in a predetermined pattern.

このように形成した基板上に、熱酸化法により5i02
膜6を形成後、基板上を平坦にするためのPSG膜7を
全面に形成し、水蒸気の雰囲気内で加熱してPSG膜7
を溶融してガラスフロー膜を形成する。
On the substrate thus formed, 5i02 was deposited by thermal oxidation.
After forming the film 6, a PSG film 7 is formed on the entire surface of the substrate to make it flat, and heated in a water vapor atmosphere to form the PSG film 7.
is melted to form a glass flow membrane.

次いでエミッタ形成領域8、コレクタコンタクト領域9
、並びにベースコンタクト領域10形成のために、前記
sio21m!6、およびpsc膜7を窓開きしする。
Next, an emitter formation region 8 and a collector contact region 9 are formed.
, and for forming the base contact region 10, the sio21m! 6, and the psc membrane 7 is opened.

次いで後の工程で、該基板上に形成する配線膜のアルミ
ニウム(All)に依って基板1が浸食されるのを防止
するのを目的としてCVD法によるポリSi膜11を形
成する。
Then, in a later step, a poly-Si film 11 is formed by CVD in order to prevent the substrate 1 from being eroded by the aluminum (All) of the wiring film formed on the substrate.

次いでベースコンタクト領域10上をホトレジストIf
fのようなマスクを用いて被覆して砒素(As)原子を
イオン注入後、基板1を熱処理してエミッタ領域8、お
よびコレクタコンタクト領域9を形成していた。
Next, a photoresist If is applied over the base contact region 10.
After arsenic (As) atoms are ion-implanted using a mask such as f, the substrate 1 is heat-treated to form an emitter region 8 and a collector contact region 9.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

然し、このような従来の方法では、このイオン注入され
砒素原子を熱処理する拡散工程で、PSG膜7内の燐原
子がポリSi膜11内に入り込み、更にこの燐原子がベ
ースコンタクト領域10内に導入されてその部分の抵抗
が高くなり、その上に形成されるN電極とコンタクトが
取れない問題点を生じる。
However, in such a conventional method, phosphorus atoms in the PSG film 7 enter into the poly-Si film 11 during the diffusion step of heat-treating the ion-implanted arsenic atoms, and these phosphorus atoms also enter the base contact region 10. When introduced, the resistance of that part becomes high, causing a problem that contact cannot be made with the N electrode formed thereon.

本発明は上記した問題点を除去し、基板上を平坦にする
ためにPSGガラスフローを用いた場合に於いても、上
記PSG膜内の燐原子がベースコンタクト領域内に導入
されないようにした半導体装置の提供を目的とする。
The present invention eliminates the above problems and provides a semiconductor in which phosphorus atoms in the PSG film are not introduced into the base contact region even when PSG glass flow is used to flatten the substrate. The purpose is to provide equipment.

〔問題点を解決するための手段〕[Means for solving problems]

本発明の半導体装置の製造方法は、半導体素子形成領域
を設けたSi基板21上に5i02膜22を形成後、p
sc膜25を形成して該PSG膜25を熔融する工程、 該基板上に第1の化学蒸着(CV D)法によるSiO
2膜26膜形6後、不純物導入領域上の第1のCVD法
による5i02膜26、熔融PSGlff25およびS
iO2膜22全22きする工程、 該基板21上に第2のCVD法による5i02膜30を
形成後、該第2のCVDSiO2膜30を異方性エツチ
ングする工程、 該基板21上にポリSi膜31を形成後、該窓開きした
箇所より基板に不純物原子を導入する工程を有する。
In the method of manufacturing a semiconductor device of the present invention, after forming a 5i02 film 22 on a Si substrate 21 provided with a semiconductor element formation region,
forming a sc film 25 and melting the PSG film 25; depositing SiO on the substrate by a first chemical vapor deposition (CVD) method;
After the 2-film 26 film type 6, the 5i02 film 26 formed by the first CVD method on the impurity doped region, the molten PSGlff25 and S
A step of forming a 5i02 film 30 on the substrate 21 by a second CVD method, and then anisotropically etching the second CVD SiO2 film 30. A step of etching the entire iO2 film 22 on the substrate 21 After forming 31, there is a step of introducing impurity atoms into the substrate through the apertured portion.

〔作用〕[Effect]

本発明の半導体装置の製造方法は、基板21上の平坦化
を目的として形成され、電極窓形成のために窓開きされ
たPSG膜25の側端部を包み込むように該PSG膜2
5の側端部側に、張り出した形の5i02膜30を形成
することで、〜電極がS+基板のSiを浸食するのを防
止するために形成されたポリSi膜31に上記PSG膜
25の燐原子が拡散滲透するのを防止し、ベースコンタ
クト領域28にPSG膜25の燐原子が拡散導入される
のを防止するようにする。
In the method of manufacturing a semiconductor device of the present invention, the PSG film 25 is formed so as to wrap around the side edge of the PSG film 25, which is formed for the purpose of planarization on the substrate 21 and has an opening for forming an electrode window.
By forming an overhanging 5i02 film 30 on the side end of the PSG film 25, the poly-Si film 31 is formed to prevent the electrode from corroding the Si of the S+ substrate. This is to prevent phosphorus atoms from diffusing into the base contact region 28 and preventing phosphorus atoms of the PSG film 25 from being diffused into the base contact region 28.

〔実施例〕〔Example〕

以下、図面を用いながら本発明の一実施例につき詳細に
説明する。
Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

第1図より第6図までは、本発明の半導体装置の製造方
法の一実施例を工程順に示す断面図で、図面を簡単にす
るために基板上のエピタキシャル層が形成された主要部
のみを示している。
FIG. 1 to FIG. 6 are cross-sectional views showing one embodiment of the method for manufacturing a semiconductor device of the present invention in the order of steps, and in order to simplify the drawings, only the main part where the epitaxial layer is formed on the substrate is shown. It shows.

まず第1図に示すように、前記第7図に示したN型の高
濃度埋込み層2が形成され、その上にN型のSiエピタ
キシャル層3が形成され、P型の素子間分離領域4が形
成されたP型のSi基板2工を用窓する。
First, as shown in FIG. 1, the N type heavily doped buried layer 2 shown in FIG. 7 is formed, an N type Si epitaxial layer 3 is formed thereon, and a P type element isolation region 4 The two P-type Si substrates on which are formed are used.

次いで該基板21上に熱酸化法によりSiO2膜22膜
形2する。
Next, a SiO2 film 22 is formed on the substrate 21 by thermal oxidation.

次いでベース形成領域23が開口されたホトレジスト膜
24を形成後、このホトレジスト膜24をマスI十 りとしてドーズ量が5×10〜5×10 原子/clT
+2、加速エネルギーが30KVの条件で硼素原子をイ
オン注入する。
Next, after forming a photoresist film 24 with an opening in the base formation region 23, this photoresist film 24 is made into a mass I and the dose amount is 5×10 to 5×10 atoms/clT.
Boron atoms are ion-implanted under conditions of +2 and acceleration energy of 30 KV.

次いで第2図に示すように、該基板上にPSG膜25を
形成後、この基板を水蒸気の雰囲気内にて加熱し、前記
したPSG膜を溶融してガラスフロー膜とする。
Next, as shown in FIG. 2, after forming a PSG film 25 on the substrate, the substrate is heated in a steam atmosphere to melt the PSG film and form a glass flow film.

更にその上に第1のCVDによる5102M’A26を
形成する。
Further, 5102M'A26 is formed thereon by first CVD.

更に第3図に示すようにエミッタ形成領域27上、ベー
スコンタクト形成領域28上、コレクタコンタクト領域
9上の前記5i02膜22、PSG膜25、第1のCV
DSiO2膜26を窓開きした後、基板上に第2のCV
DSiO2膜30を形成する。
Furthermore, as shown in FIG. 3, the 5i02 film 22, the PSG film 25, the first CV
After opening the DSiO2 film 26, a second CV is formed on the substrate.
A DSiO2 film 30 is formed.

次いで第4図に示すようにリアクティブイオン(RIE
)−Cッチング法により第2のCVD5iOz膜30を
異方性エツチングし、窓開きしたPSG膜25の側端部
をこの第2のCVDSiO2膜30で囲うようにする。
Next, as shown in Fig. 4, reactive ion (RIE)
)-C etching method to anisotropically etch the second CVD5iOz film 30 so that the side edges of the window-opened PSG film 25 are surrounded by the second CVDSiO2 film 30.

次いで第5図に示すように該基板上をポリ5ilQ31
で被覆するようにする。
Next, as shown in FIG.
Make sure to cover it with

このポリSi膜31は後の工程で基板上に〜の配線膜を
形成した時、この鰯が基板のStを浸食するのを防止す
るために設ける。
This poly-Si film 31 is provided in order to prevent this sardine from corroding the St of the substrate when the wiring films .about. are formed on the substrate in a later step.

次いでベースコンタクト領域をホトレジストのようなマ
スクを用いて被覆して砒素原子をイオン注入してエミッ
タ領域27、およびコレクタコンタクト領域29を形成
する。
The base contact region is then covered using a mask such as photoresist, and arsenic atoms are ion-implanted to form emitter region 27 and collector contact region 29.

このようにすれば、砒素原子をイオン注入後、熱処理し
てエミッタ領域を形成する過程で、psGB’i!25
の側端部側より燐原子が、〜電極を形成する際のこの鰯
が基板のStを浸食するのを防止するために形成された
ポリSi膜31内を拡散して基板のベースコンタクト領
域内に導入されるのが防止され、ベースコンタクトが良
好に形成された高信頼度の半導体装置が得られる。
In this way, psGB'i! is generated in the process of forming the emitter region by heat treatment after ion implantation of arsenic atoms. 25
Phosphorus atoms diffuse into the poly-Si film 31, which is formed to prevent the sardines from eroding the St of the substrate when forming the electrode, from the side edge side of the substrate, and enter the base contact region of the substrate. A highly reliable semiconductor device with well-formed base contacts can be obtained.

更に基板上が平滑になるので、基板上に形成する〜配線
が断線、或いはショートする現象が除去される。
Furthermore, since the surface of the substrate becomes smooth, the phenomenon of disconnection or short-circuiting of wiring formed on the substrate is eliminated.

またエミッタ形成のための砒素原子のイオン注入の際の
マスクとなる第1の5i02膜26の側面に形成された
第2の5iz21e!30によりイオン注入領域が狭め
られ、エミッタ領域が微細に形成されるため、高速、高
集積化された半導体装置が得られる。
Also, a second 5iz21e! film is formed on the side surface of the first 5i02 film 26, which serves as a mask during ion implantation of arsenic atoms to form an emitter. Since the ion implantation region is narrowed by 30 and the emitter region is formed finely, a high-speed, highly integrated semiconductor device can be obtained.

更に基板上を平坦化するためのpsc膜が耐湿性の良好
な5i02膜で被覆されるので、耐湿性の向上した高信
頼度の半導体装置が得られる。
Furthermore, since the psc film for planarizing the substrate is covered with a 5i02 film having good moisture resistance, a highly reliable semiconductor device with improved moisture resistance can be obtained.

以上述べた実施例では、バイポーラ型半導体装置につい
て例を用いて述べたが、本発明の方法はCMO5半導体
装置にも適用できる。
Although the embodiments described above have been described using bipolar semiconductor devices as an example, the method of the present invention can also be applied to CMO5 semiconductor devices.

〔発明の効果〕〔Effect of the invention〕

以上述べたように、本発明の半導体装置の製造方法によ
れば、基板上を平坦にするために設けたPSG膜のガラ
スフロー膜の燐原子が、Si基板のSiと〜配線膜との
〜に依って浸食されるのを防止するために形成したポリ
Si膜を拡散して基板のベースコンタクト領域に拡散さ
れることがなくなるため、ベースコンタクトが充分数れ
る高信頼度の半導体装置が得られる効果がある。
As described above, according to the method of manufacturing a semiconductor device of the present invention, the phosphorus atoms of the glass flow film of the PSG film provided to flatten the substrate are separated from the Si of the Si substrate and the wiring film. Since the poly-Si film formed to prevent corrosion by the polysilicon is diffused into the base contact region of the substrate, a highly reliable semiconductor device with a sufficient number of base contacts can be obtained. effective.

【図面の簡単な説明】[Brief explanation of drawings]

第1図より第6図までは本発明の半導体装置の製造方法
の一実施例を工程順に示す断面図、第7図は従来の半導
体装置の製造方法を説明するための断面図である。 図に於いて、 21はSi基板、22はSiO2膜、23はベース領域
、24はホトレジスト膜、25はPSG膜、26は第1
のCVD5i02膜、27はエミッタ領域、28はベー
スコンタクト領域、29はコレクタコンタクト領域、3
0は第2の5iO211!f!、31はポリSi膜を示
す。 ンLNg乃のうC−ス々9引へsA’ニオ【の m 滓省ド所nPSG力゛うlフロー衰k う1丁めCVD
 S:Ozl勇形八・へ1g2 図 斗IMEJh22q CVD S’+02R(−yb八
へxir第 3 図 、f/l−a%tqfz、ncVDs’rOzflkJ
!Fn工、’?−f rglffi第4図 ンi−両≦Eすbりぢに′ソ5i17flづ札ρ(工′
ネigり@511 113戸Hのエミ、〕4tQ”、コレフヲ麿p%EK’
eすt城1)へ゛エネ¥回第 6 図
1 to 6 are cross-sectional views showing one embodiment of the method for manufacturing a semiconductor device according to the present invention in the order of steps, and FIG. 7 is a cross-sectional view for explaining a conventional method for manufacturing a semiconductor device. In the figure, 21 is a Si substrate, 22 is an SiO2 film, 23 is a base region, 24 is a photoresist film, 25 is a PSG film, and 26 is a first
CVD5i02 film, 27 is an emitter region, 28 is a base contact region, 29 is a collector contact region, 3
0 is the second 5iO211! f! , 31 indicates a poly-Si film. N LNg no C - Susu 9 draw sA'Nio
S: Ozl Yugata 8, 1g2 Zuto IMEJh22q CVD S'+02R (-yb 8 3rd figure, f/l-a%tqfz, ncVDs'rOzflkJ
! Fn engineering,'? -f rglffiFig.
Neiguri @ 511 Emi of 113 H,] 4tQ", Korefuwomaro p%EK'
EST Castle 1) Energy¥ Part 6 Figure 6

Claims (1)

【特許請求の範囲】 半導体素子形成領域を設けたシリコン(Si)基板(2
1)上に二酸化シリコン膜(22)を形成後、燐珪酸ガ
ラス(25)膜を形成して該燐珪酸ガラス膜(25)を
溶融する工程、 該基板(21)上に第1の化学蒸着法による二酸化シリ
コン膜(26)を形成後、不純物導入領域上の第1の化
学蒸着法による二酸化シリコン膜(26)、溶融した燐
珪酸ガラス膜(25)、二酸化シリコン膜(22)を窓
開きする工程、 該基板(21)上に第2の化学蒸着法による二酸化シリ
コン膜(30)を形成後、該二酸化シリコン膜(30)
を異方性エッチングする工程、 該基板(21)上にポリシリコン膜(31)を形成後、
前記窓開きした箇所より基板(21)に不純物原子を導
入する工程を有することを特徴とする半導体装置の製造
方法。
[Claims] A silicon (Si) substrate (2) provided with a semiconductor element formation region.
1) After forming a silicon dioxide film (22) on the substrate, forming a phosphosilicate glass (25) film and melting the phosphosilicate glass film (25), a first chemical vapor deposition process on the substrate (21); After forming the silicon dioxide film (26) by the method, the silicon dioxide film (26) by the first chemical vapor deposition method, the molten phosphosilicate glass film (25), and the silicon dioxide film (22) on the impurity introduction region are opened. After forming a silicon dioxide film (30) on the substrate (21) by a second chemical vapor deposition method, forming the silicon dioxide film (30) on the substrate (21).
After forming a polysilicon film (31) on the substrate (21),
A method for manufacturing a semiconductor device, comprising the step of introducing impurity atoms into the substrate (21) through the open window.
JP297586A 1986-01-09 1986-01-09 Manufacture of semiconductor device Pending JPS62160730A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP297586A JPS62160730A (en) 1986-01-09 1986-01-09 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP297586A JPS62160730A (en) 1986-01-09 1986-01-09 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS62160730A true JPS62160730A (en) 1987-07-16

Family

ID=11544369

Family Applications (1)

Application Number Title Priority Date Filing Date
JP297586A Pending JPS62160730A (en) 1986-01-09 1986-01-09 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS62160730A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63177539A (en) * 1987-01-19 1988-07-21 Nec Corp Semiconductor device and its manufacture
JPH01212451A (en) * 1988-02-20 1989-08-25 Sony Corp Manufacture of semiconductor device
JPWO2015194590A1 (en) * 2014-06-18 2017-04-20 富士電機株式会社 Semiconductor device and manufacturing method of semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63177539A (en) * 1987-01-19 1988-07-21 Nec Corp Semiconductor device and its manufacture
JPH01212451A (en) * 1988-02-20 1989-08-25 Sony Corp Manufacture of semiconductor device
JPWO2015194590A1 (en) * 2014-06-18 2017-04-20 富士電機株式会社 Semiconductor device and manufacturing method of semiconductor device
US10050133B2 (en) 2014-06-18 2018-08-14 Fuji Electric Co., Ltd. Application of thin insulating film layer in semiconductor device and method of manufacturing semiconductor device

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