JPS63177539A - Semiconductor device and its manufacture - Google Patents
Semiconductor device and its manufactureInfo
- Publication number
- JPS63177539A JPS63177539A JP1025387A JP1025387A JPS63177539A JP S63177539 A JPS63177539 A JP S63177539A JP 1025387 A JP1025387 A JP 1025387A JP 1025387 A JP1025387 A JP 1025387A JP S63177539 A JPS63177539 A JP S63177539A
- Authority
- JP
- Japan
- Prior art keywords
- film
- insulating film
- layer
- wiring
- insulating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 238000005530 etching Methods 0.000 claims abstract description 11
- 238000000034 method Methods 0.000 claims description 8
- 239000000758 substrate Substances 0.000 abstract description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 4
- 238000007796 conventional method Methods 0.000 abstract description 2
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 2
- 239000000377 silicon dioxide Substances 0.000 abstract description 2
- 239000011248 coating agent Substances 0.000 abstract 1
- 238000000576 coating method Methods 0.000 abstract 1
- 238000005121 nitriding Methods 0.000 abstract 1
- 238000005245 sintering Methods 0.000 abstract 1
- 239000000463 material Substances 0.000 description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 230000007547 defect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 210000004709 eyebrow Anatomy 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
Landscapes
- Local Oxidation Of Silicon (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置およびその製造方法に関し、特にス
テップカバーレッジを良好にしたカバーレッジ改善膜を
含む配線層間膜にスルーホールを開孔してなる半導体装
置及びその製造方法に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor device and a method for manufacturing the same, and in particular to a semiconductor device and a method for manufacturing the same. The present invention relates to a semiconductor device and a manufacturing method thereof.
従来、この種の3層構造絶縁層のスルーホールは、レジ
ストでバターニングし、そのレジストパターンをマスク
にして3層絶縁層をエツチング開孔した後、レジストを
剥離し、そのまま次の層の配線材料を成長させていた。Conventionally, through-holes in this type of three-layer insulating layer were patterned with a resist, and the three-layer insulating layer was etched using the resist pattern as a mask to open the hole.Then, the resist was peeled off and the wiring was directly connected to the next layer. The material was growing.
上述した従来のスルーホール形状の問題点を図面を用い
て説明する。第4図は従来の半導体装置の製造方法によ
り形成された半導体装置の要部断面図である。第4図に
示す様に従来の半導体装置は基板1の上にある下層配線
膜2.下部絶縁膜3゜カバーレッジ改善膜4.上部絶縁
膜5.上層配線6とからなっている。そして8はカバー
レッジ改善膜4と上層配線6との接触部である。4のカ
バーレッジ改善膜の材料は通常、有機物又は有機媒体含
有物であり、配線材料と反応しやすい、そのため、カバ
ーレッジ改善膜4と上層配線6の接触部8において、両
者が反応し、スルーホール部で配線の電気的不良などが
置きやすくなり、信頼性が低下するという欠点があった
。The problems with the conventional through-hole shape described above will be explained with reference to the drawings. FIG. 4 is a sectional view of a main part of a semiconductor device formed by a conventional semiconductor device manufacturing method. As shown in FIG. 4, a conventional semiconductor device has a lower wiring film 2 on a substrate 1. Lower insulating film 3° Coverage improvement film 4. Upper insulating film 5. It consists of upper layer wiring 6. Reference numeral 8 denotes a contact portion between the coverage improvement film 4 and the upper layer wiring 6. The material of the coverage improvement film 4 is usually an organic substance or a substance containing an organic medium, and it easily reacts with the wiring material. This has the disadvantage that electrical faults in the wiring are likely to occur in the hole portions, reducing reliability.
本発明の目的は、眉間絶縁層としてステップカバーレッ
ジを改善するためのカバーレッジ改善膜を含む3層構造
の絶縁層のスルーホール部の側面においてカバーレッジ
改善膜材料と上部配線材料が直接接触することがなく、
従って両者の反応がなくなり、スルーホール部で配線の
電気的不良などが起きない半導体装置及びその製造方法
を提供することにある。An object of the present invention is to directly contact the coverage improving film material and the upper wiring material on the side surface of the through-hole part of the insulating layer having a three-layer structure including the coverage improving film for improving the step coverage as an insulating layer between the eyebrows. Without a doubt,
Therefore, it is an object of the present invention to provide a semiconductor device and a method for manufacturing the same, in which there is no reaction between the two, and electrical defects in the wiring do not occur in the through-hole portion.
本発明の第1の発明の半導体装置は、上層配線と下層配
線間を絶縁する絶縁層が上部絶縁膜上下部絶縁膜及びそ
の2つの絶縁膜にはさまれたカバーレッジ改善膜よりな
る3層構造を有し、該絶縁層にスルーホールを有する半
導体装置において、前記絶縁層に設けられた前記スルー
ホール内部側面の少なくともカバーレッジ改善膜の側面
が他の薄い絶縁膜により被覆されていることを特徴とし
て構成される。In the semiconductor device of the first aspect of the present invention, the insulating layer that insulates between the upper layer interconnect and the lower layer interconnect is a three-layer insulating layer consisting of an upper insulating film, an upper insulating film, a lower insulating film, and a coverage improvement film sandwiched between the two insulating films. In the semiconductor device having a through hole in the insulating layer, at least the side surface of the coverage improvement film on the inner side surface of the through hole provided in the insulating layer is covered with another thin insulating film. Constructed as a feature.
また、本発明の第2の発明の半導体装置の製造方法は、
上層配線と下層配線間を絶縁する絶縁層として上部絶縁
膜と下部絶縁膜及びその2つの絶縁膜にはさまれたカバ
ーレッジ改善膜よりなる3層構造の絶縁層を形成する工
程と、該3層構造の絶縁層にスルーホールを形成する工
程とを含む半導体装置の製造方法において、前記3層構
造の絶縁層の垂直方向のエツチングを行ないスルーホー
ルを開孔する工程と、該スルーホールを含む表面に薄い
絶縁膜を一様に形成する工程と、その後垂直方向に異方
性エツチングを行ない薄い絶縁膜の厚みの分だけエツチ
ングする工程とを含むことを特徴として構成される。Further, the method for manufacturing a semiconductor device according to the second invention of the present invention includes:
forming an insulating layer with a three-layer structure consisting of an upper insulating film, a lower insulating film, and a coverage improvement film sandwiched between the two insulating films as an insulating layer for insulating between the upper layer wiring and the lower layer wiring; forming a through hole in an insulating layer having a layered structure; The method is characterized by comprising the steps of uniformly forming a thin insulating film on the surface, and then performing anisotropic etching in the vertical direction to etch by the thickness of the thin insulating film.
次に、本発明の実施例について図面を参照して説明する
。第1図は本発明の第1の発明の半導体装置の一実施例
の断面図である。Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a sectional view of an embodiment of a semiconductor device according to a first aspect of the present invention.
第1図に示すように、本実施例はシリコン基板1上に形
成された下層配線2を覆って形成された下部絶縁膜3と
カバーレッジ改善膜4と上部絶縁膜5とよりなる3層構
造を有する眉間の絶縁膜を有し、その絶縁層には下層配
線2と上層配線6とを接続するためのスルーホールが開
孔され、そのスルーホールの絶縁層の側面は薄いスルー
ホール側面絶縁膜7により被覆されており、この薄いス
ルーホール側面絶縁膜により上層配線とカバーレッジ改
善膜の接触が防がれる構造を有している。As shown in FIG. 1, this embodiment has a three-layer structure consisting of a lower insulating film 3 formed to cover a lower wiring 2 formed on a silicon substrate 1, a coverage improvement film 4, and an upper insulating film 5. The insulating layer has a through hole for connecting the lower layer wiring 2 and the upper layer wiring 6, and the side surface of the insulating layer of the through hole is covered with a thin through hole side insulating film. 7, and has a structure in which contact between the upper layer wiring and the coverage improvement film is prevented by this thin through-hole side insulating film.
第2図(a)、(b)は本発明の第2の発明の一実施例
を説明するために工程順に示した一部製造工程における
素子の断面図であり、第1図に示した一実施例の製造方
法につき説明する。FIGS. 2(a) and 2(b) are cross-sectional views of an element in some manufacturing steps shown in the order of steps for explaining an embodiment of the second invention of the present invention, and are similar to those shown in FIG. 1. The manufacturing method of the example will be explained.
まず、第2図(a)に示すように、シリコン基板1の表
面に形成された下層配線2を覆って下部絶縁膜3(例え
ばプラズマ窒化膜)、その上に二酸化ケイ素溶液を塗布
した後焼結することにより形成したカバーレッジ改善膜
4.その上に上部絶縁膜5(例えばプラズマ窒化膜)の
3層よりなる絶縁層を形成する。次に、従来方法と同様
にスルーホールを形成する。次いでスルーホールを含む
表面に0.1〜0.5μmのプラズマ窒化膜の薄い絶縁
膜9を一様に形成する。First, as shown in FIG. 2(a), a lower insulating film 3 (for example, a plasma nitride film) is applied to cover the lower wiring 2 formed on the surface of the silicon substrate 1, and a silicon dioxide solution is applied thereon, followed by baking. Coverage improvement film formed by bonding 4. Thereon, an insulating layer consisting of three layers of an upper insulating film 5 (for example, a plasma nitride film) is formed. Next, through holes are formed in the same manner as in the conventional method. Next, a thin insulating film 9 of plasma nitride film having a thickness of 0.1 to 0.5 μm is uniformly formed on the surface including the through holes.
次に、第2図(b)に示すように、一様に異性性エツチ
ングを行ない、薄い絶縁膜9の厚さ分だけエツチングす
ると、スルーホール内部側面にのみ薄い絶縁膜9が残り
スルーホール側面絶縁膜7を形成することができる。Next, as shown in FIG. 2(b), when etching is performed uniformly by the thickness of the thin insulating film 9, the thin insulating film 9 remains only on the inner side surface of the through hole. An insulating film 7 can be formed.
次に、上層配線を形成すると、第1図に示した本発明の
一実施例のカバーレッジ改善膜と直接接触することがな
い配線を有する半導体装置が得られる。Next, by forming upper layer wiring, a semiconductor device having wiring that does not come into direct contact with the coverage improving film of the embodiment of the present invention shown in FIG. 1 is obtained.
第3図は本発明の他の実施例の構造並びにその製造方法
を説明するための素子の断面図である。FIG. 3 is a sectional view of an element for explaining the structure and manufacturing method of another embodiment of the present invention.
本実施例では第1の実施例と異なる点を重点にして説明
する。This embodiment will be explained with emphasis on the points that are different from the first embodiment.
第3図に示すように、スルーホール部の上層配線6のカ
バーレッジ改善として、絶縁層3,4゜5の開孔時、レ
ジストのバターニング後のエツチング方法として、初め
当方性エツチングを行い、次いで異方径エツチングを行
って開孔する。この時の当方性エツチング深さをカバー
レッジ改善膜4に達する前に止めれば、本発明の第1の
実施例と同じようにスルーホール開孔後、薄い絶縁膜を
一様に成長させ、異方性エツチングを行えば、スルーホ
ール周囲の異方性エッチ部にのみ薄い絶縁膜を残すこと
ができる。それにより少なくともスルーホール側面のカ
バーレッジ改善膜が薄い絶縁膜に覆われた構造が得られ
、その結果カバーレッジ改善膜と配線材料が直接接触す
ることがない半導体装置が得られる。As shown in FIG. 3, in order to improve the coverage of the upper layer wiring 6 in the through-hole portion, when opening the insulating layers 3 and 4.5, as an etching method after patterning the resist, first isotropic etching is performed. Next, anisotropic etching is performed to form holes. If the depth of the isotropic etching at this time is stopped before reaching the coverage improvement film 4, the thin insulating film can be uniformly grown after the through-hole is opened, as in the first embodiment of the present invention, and the If anisotropic etching is performed, a thin insulating film can be left only in the anisotropically etched area around the through hole. As a result, a structure is obtained in which the coverage improvement film on at least the side surface of the through hole is covered with a thin insulating film, and as a result, a semiconductor device is obtained in which the coverage improvement film and the wiring material do not come into direct contact.
以上説明したように本発明は、配線間絶縁層として、カ
バーレッジ改善材料を用いている時に、下層と上層の配
線間スルーホール開孔後、薄い絶縁膜を一様に成長し、
全面を異方性エツチングし、スルーホール開孔部側面に
のみ薄い絶縁膜を残した半導体装置が得られ、その結果
、完成された半導体装置は、カバーレッジ改善材料と配
線材料とが直接接触することがないため、カバーレッジ
改善材料との反応がなくなりスルーホール部で配線の電
気的不良などが起きないという効果がある。As explained above, in the present invention, when a coverage improving material is used as an inter-wiring insulating layer, a thin insulating film is uniformly grown after opening a through-hole between the lower and upper interconnects,
A semiconductor device is obtained by anisotropically etching the entire surface, leaving a thin insulating film only on the side surfaces of the through-hole openings.As a result, in the completed semiconductor device, the coverage improvement material and the wiring material are in direct contact. Therefore, there is no reaction with the coverage improving material, and there is an effect that electrical defects in the wiring do not occur in the through-hole portion.
第1図は本発明の第1の発明の一実施例の断面図、第2
図(a)、(b)は本発明の第2の発明の一実施例を説
明するために工程順に示した一部途中工程の素子の断面
図、第3図は本発明の他の実施例の構造並びに製造方法
を説明するための素子の断面図、第4図は従来例を説明
するためのスルーホール構造を有する素子の断面図であ
る。
1・・・シリコン基板、2・・・下層配線、3・・・下
部絶縁膜、4・・・カバーレッジ改善膜、5・・・上部
絶縁膜、6・・・上層配線、7・・・スルーホール側面
絶縁層、8・・・4と6の接触部、9・・・薄い絶縁材
料。FIG. 1 is a sectional view of an embodiment of the first invention of the present invention, and FIG.
Figures (a) and (b) are cross-sectional views of an element partially in the middle of the process shown in the order of steps to explain an embodiment of the second invention of the present invention, and Fig. 3 is another embodiment of the present invention. FIG. 4 is a sectional view of an element having a through-hole structure to explain a conventional example. DESCRIPTION OF SYMBOLS 1... Silicon substrate, 2... Lower layer wiring, 3... Lower insulating film, 4... Coverage improvement film, 5... Upper insulating film, 6... Upper layer wiring, 7... Through-hole side insulating layer, 8... contact portion between 4 and 6, 9... thin insulating material.
Claims (2)
縁膜と下部絶縁膜及びその2つの絶縁膜にはさまれたカ
バーレッジ改善膜よりなる3層構造を有し、該絶縁層に
スルーホールを有する半導体装置において、前記絶縁層
に設けられた前記スルーホール内部側面の少なくともカ
バーレッジ改善膜の側面が他の薄い絶縁膜により被覆さ
れていることを特徴とする半導体装置。(1) The insulating layer that insulates between the upper layer wiring and the lower layer wiring has a three-layer structure consisting of an upper insulating film, a lower insulating film, and a coverage improvement film sandwiched between these two insulating films, and the insulating layer 1. A semiconductor device having a through hole, wherein at least a side surface of a coverage improvement film on an inner side surface of the through hole provided in the insulating layer is covered with another thin insulating film.
部絶縁膜と下部絶縁膜及びその2つの絶縁膜にはさまれ
たカバーレッジ改善膜よりなる3層構造の絶縁層を形成
する工程と、該3層構造の絶縁層にスルーホールを形成
する工程とを含む半導体装置の製造方法において、前記
3層構造の絶縁層の垂直方向のエッチングを行ないスル
ーホールを開孔する工程と、該スルーホールを含む表面
に薄い絶縁膜を一様に形成する工程と、その後垂直方向
に異方性エッチングを行ない薄い絶縁膜の厚みの分だけ
エッチングする工程とを含むことを特徴とする半導体装
置の製造方法。(2) A step of forming an insulating layer with a three-layer structure consisting of an upper insulating film, a lower insulating film, and a coverage improvement film sandwiched between the two insulating films as an insulating layer that insulates between the upper layer wiring and the lower layer wiring. forming a through hole in the insulating layer having the three-layer structure; Manufacturing a semiconductor device comprising the steps of uniformly forming a thin insulating film on a surface including holes, and then performing anisotropic etching in the vertical direction to etch by the thickness of the thin insulating film. Method.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1025387A JPS63177539A (en) | 1987-01-19 | 1987-01-19 | Semiconductor device and its manufacture |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1025387A JPS63177539A (en) | 1987-01-19 | 1987-01-19 | Semiconductor device and its manufacture |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS63177539A true JPS63177539A (en) | 1988-07-21 |
Family
ID=11745152
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1025387A Pending JPS63177539A (en) | 1987-01-19 | 1987-01-19 | Semiconductor device and its manufacture |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS63177539A (en) |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS594057A (en) * | 1982-06-30 | 1984-01-10 | Toshiba Corp | Formation of contact hole |
JPS59124742A (en) * | 1982-12-29 | 1984-07-18 | Matsushita Electronics Corp | Manufacture of semiconductor device |
JPS60109248A (en) * | 1983-11-18 | 1985-06-14 | Hitachi Ltd | Semiconductor ic device and manufacture thereof |
JPS62160730A (en) * | 1986-01-09 | 1987-07-16 | Fujitsu Ltd | Manufacture of semiconductor device |
-
1987
- 1987-01-19 JP JP1025387A patent/JPS63177539A/en active Pending
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS594057A (en) * | 1982-06-30 | 1984-01-10 | Toshiba Corp | Formation of contact hole |
JPS59124742A (en) * | 1982-12-29 | 1984-07-18 | Matsushita Electronics Corp | Manufacture of semiconductor device |
JPS60109248A (en) * | 1983-11-18 | 1985-06-14 | Hitachi Ltd | Semiconductor ic device and manufacture thereof |
JPS62160730A (en) * | 1986-01-09 | 1987-07-16 | Fujitsu Ltd | Manufacture of semiconductor device |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JPS63177539A (en) | Semiconductor device and its manufacture | |
JPH02142162A (en) | Semiconductor device and manufacture thereof | |
JPH0346977B2 (en) | ||
JPS63258043A (en) | Manufacture of semiconductor device | |
JPH04109654A (en) | Semiconductor device and manufacture thereof | |
JPS6484722A (en) | Manufacture of semiconductor device | |
JPS62155537A (en) | Manufacture of semiconductor device | |
JP2758765B2 (en) | Method for manufacturing semiconductor device | |
JPH02111052A (en) | Formation of multilayer interconnection | |
JPS6235537A (en) | Semiconductor device and manufacture thereof | |
JPH0697290A (en) | Manufacture of semiconductor device | |
JPH03248533A (en) | Semiconductor integrated circuit device | |
JPH05283537A (en) | Fabrication of semiconductor device | |
JPS63226931A (en) | Manufacture of semiconductor device | |
JPS6334928A (en) | Formation of through hole | |
JPS63312658A (en) | Manufacture of semiconductor device | |
JPS58147042A (en) | Preparation of semiconductor device | |
JPH0290616A (en) | Through-hole forming method for interlayer insulating film | |
JPH02237137A (en) | Manufacture of semiconductor device | |
JPH0927492A (en) | Manufacture of semiconductor device | |
JPS6181656A (en) | Multilayer interconnection method of semiconductor element | |
JPH03224229A (en) | Manufacture of semiconductor device | |
JPS61187235A (en) | Manufacture of semiconductor device | |
JPH04290424A (en) | Manufacture of semiconductor device, and semiconductor device | |
JPH02105552A (en) | Manufacture of semiconductor device |