JPH0359577B2 - - Google Patents
Info
- Publication number
- JPH0359577B2 JPH0359577B2 JP56102882A JP10288281A JPH0359577B2 JP H0359577 B2 JPH0359577 B2 JP H0359577B2 JP 56102882 A JP56102882 A JP 56102882A JP 10288281 A JP10288281 A JP 10288281A JP H0359577 B2 JPH0359577 B2 JP H0359577B2
- Authority
- JP
- Japan
- Prior art keywords
- polysilicon layer
- gate electrode
- etching
- insulating film
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 54
- 229920005591 polysilicon Polymers 0.000 claims description 53
- 238000005530 etching Methods 0.000 claims description 34
- 238000000034 method Methods 0.000 claims description 23
- 239000004065 semiconductor Substances 0.000 claims description 9
- 238000000059 patterning Methods 0.000 claims description 8
- 239000012535 impurity Substances 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 7
- 238000004519 manufacturing process Methods 0.000 claims description 4
- 230000007423 decrease Effects 0.000 claims description 2
- 150000002500 ions Chemical class 0.000 claims description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 13
- 229910052698 phosphorus Inorganic materials 0.000 description 13
- 239000011574 phosphorus Substances 0.000 description 13
- 238000009792 diffusion process Methods 0.000 description 12
- 238000001020 plasma etching Methods 0.000 description 12
- 238000009413 insulation Methods 0.000 description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 239000005368 silicate glass Substances 0.000 description 5
- 229910004298 SiO 2 Inorganic materials 0.000 description 4
- 239000007789 gas Substances 0.000 description 4
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 235000012431 wafers Nutrition 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- VZGDMQKNWNREIO-UHFFFAOYSA-N tetrachloromethane Chemical compound ClC(Cl)(Cl)Cl VZGDMQKNWNREIO-UHFFFAOYSA-N 0.000 description 2
- 238000000137 annealing Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- RLOWWWKZYUNIDI-UHFFFAOYSA-N phosphinic chloride Chemical compound ClP=O RLOWWWKZYUNIDI-UHFFFAOYSA-N 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
- H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers
Description
【発明の詳細な説明】
本発明は半導体装置の製造方法、より詳しくは
ゲート電極とすべき多結晶シリコン（ポリシリコ
ン）層をパターニングする際、当該パターンにテ
ーパを設けかつパターン幅を精度よくエツチング
する方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and more specifically, when patterning a polycrystalline silicon (polysilicon) layer to be used as a gate electrode, the pattern is tapered and the pattern width is precisely etched. Regarding how to.
最近、半導体集積回路製造技術における高集積
化の向上に伴ない多層配線が多用されるようにな
り、その結果かゝる多層配線において導電層間の
絶縁が重要になつてきた。従来技術では、例え
ば、半導体基板の表面にゲート酸化膜を介して形
成されるゲート電極の場合には、このゲート電極
となるべきポリシリコンをエツチングする場合、
当該ポリシリコン層にテーパを設けることがなか
つたため、導電層上に塗布した絶縁例えばりん・
けい酸ガラス（PSG）膜の厚さがポリシリコン
層の段部のところで薄くなる部分ができ、絶縁不
良または短絡のような絶縁効果に支障をきたす事
例の発生が経験された。 Recently, as semiconductor integrated circuit manufacturing technology has become more highly integrated, multilayer wiring has come into widespread use, and as a result, insulation between conductive layers in such multilayer wiring has become important. In the conventional technology, for example, in the case of a gate electrode formed on the surface of a semiconductor substrate via a gate oxide film, when polysilicon that is to become the gate electrode is etched,
Since the polysilicon layer was not tapered, the insulation coated on the conductive layer, such as phosphorus,
Cases have been experienced in which the thickness of the silicate glass (PSG) film becomes thinner at the steps of the polysilicon layer, causing problems with the insulation effect such as insulation failure or short circuits.
また一方では、このゲート電極の上部角で、こ
のゲート電極表面を覆うように形成される絶縁膜
が薄くなるという問題を解消しようと、プラズマ
エツチングのように、エツチング残余のポリシリ
コン断面を垂直形状にしうる異方的なエツチング
を施した後に、さらにこの残余のポリシリコン表
面をエツチング液に晒して等方的にエツチング
し、このポリシリコンの上部角を除去するという
手法も試みられたが、このような単純な異方性エ
ツチングと等方性エツチングの組み合わせによつ
ては、ゲート電極下部まで余計にエツチングして
しまい、ゲート長を短くしてしまうという問題が
ある。この場合には当初の異方性エツチング時
に、この等方性エツチングでのエツチング分を見
込んで、やや大きめにポリシリコンを残すという
方法も考えられようが、現在ではゲート電極は十
分に微細化が進んでおり、このような方法によつ
ては、規定のゲート長になるようにエツチングを
制御することは極めて困難であり、実用的な手法
であるとは言い難い。 On the other hand, in order to solve the problem that the insulating film formed to cover the gate electrode surface becomes thinner at the upper corner of the gate electrode, a method such as plasma etching is used to vertically shape the etched polysilicon cross section. Another method was attempted in which the remaining polysilicon surface was exposed to an etching solution and etched isotropically to remove the upper corner of the polysilicon after anisotropic etching was performed to remove the upper corner of the polysilicon. Such a simple combination of anisotropic etching and isotropic etching has the problem of excessively etching the lower part of the gate electrode, shortening the gate length. In this case, it may be possible to consider leaving a slightly larger polysilicon layer during the initial anisotropic etching to take into account the amount of etching in this isotropic etching, but at present gate electrodes have not been sufficiently miniaturized. However, with such a method, it is extremely difficult to control etching to a specified gate length, and it is difficult to say that it is a practical method.
従来技術についてより詳細に説明すると、第１
図は従来方法におけるゲート電極となるべきポリ
シリコン層のパターン形成方法を示している。同
図において１はシリコン基板、２は二酸化シリコ
ン（SiO2）膜、３はポリシリコン層、４はホト
レジスト膜、５はりん・けい酸ガラス（PSG）
膜を示す。同図を参照すると、同図ａに示す如く
基板１に塗布されたSiO2膜２上にポリシリコン
層３が例えば化学気相成長法（CVD法）で形成
されていて、かゝるポリシリコン層３にりん(P)の
ドーピングをなし（同図矢印で示す）、しかる後、
熱処理（アニール）を行ない、ポリシリコンのゲ
ート電極を形成する。このときゲート電極（ポリ
シリコン層）内のりん濃度は一定の傾斜をもつた
ものである。次に、レジスト膜４を塗布し、しか
る後、RIE（リアクテイブ・イオン・エツチング）
型装置によりエツチングをなしてパターニングを
行なう（同図ｂ）。さらに残るレジスト膜４を剥
離し、絶縁用のりん・けい酸ガラス（PSG）膜
５を形成する（同図ｅ）。 To explain the prior art in more detail, the first
The figure shows a conventional method for patterning a polysilicon layer to become a gate electrode. In the figure, 1 is a silicon substrate, 2 is a silicon dioxide (SiO 2 ) film, 3 is a polysilicon layer, 4 is a photoresist film, and 5 is phosphorous silicate glass (PSG).
The membrane is shown. Referring to the figure, as shown in figure a, a polysilicon layer 3 is formed on a SiO 2 film 2 coated on a substrate 1 by, for example, chemical vapor deposition (CVD). Layer 3 is not doped with phosphorus (P) (indicated by the arrow in the figure), and then,
Heat treatment (annealing) is performed to form a polysilicon gate electrode. At this time, the phosphorus concentration within the gate electrode (polysilicon layer) has a certain slope. Next, a resist film 4 is applied, and then RIE (reactive ion etching) is applied.
Patterning is performed by etching using a molding device (FIG. 2(b)). Furthermore, the remaining resist film 4 is peeled off, and an insulating phosphorous silicate glass (PSG) film 5 is formed (see e in the figure).
以上説明した如く、従来のゲート電極（ポリシ
リコン層）のパターニング技術では、同図ｂに示
す如く、エツチングされたゲート電極（ポリシリ
コン層）の断面３′の形状がRIE法によるエツチ
ングの方向性が良いため、矩形をなしている（ゲ
ート電極（ポリシリコン層）内のりん濃度均一に
よるエツチング速度が一定のため）ので、当該ゲ
ート電極（ポリシリコン層）に絶縁膜（PSG）
を塗布した場合、同図ｃにおいて矢印で示すよう
に絶縁膜の薄い部分（段差）が生じ、このゲート
電極表面に絶縁膜を被着形成し、さらにこの絶縁
膜の表面に配線層を形成するいわゆる多層配線を
なした場合、前記した如くにこの部分に破損が生
じ絶縁不良の原因になる。 As explained above, in the conventional gate electrode (polysilicon layer) patterning technology, as shown in Figure b, the shape of the cross section 3' of the etched gate electrode (polysilicon layer) is determined by the directionality of the etching by the RIE method. Since the etching rate is rectangular (because the etching rate is constant due to the uniform phosphorus concentration in the gate electrode (polysilicon layer)), an insulating film (PSG) is formed on the gate electrode (polysilicon layer).
When this is applied, a thin part (step) of the insulating film is formed as shown by the arrow in Figure c, an insulating film is deposited on the surface of this gate electrode, and a wiring layer is further formed on the surface of this insulating film. When a so-called multilayer wiring is formed, damage occurs in this portion as described above, causing insulation failure.
他方、ゲート電極（ポリシリコン層）エツチン
グをバレル型装置を用いるプラズマ法によつて行
つた場合、エツチングされたゲート電極（ポリシ
リコン層）の断面の形状は同図ｂに破線で示す如
く、サイドエツチングされた台形をなし、テーパ
がついている。しかし、パターン幅が規格とは異
なり半導体装置の精度上問題が生ずる。 On the other hand, when the gate electrode (polysilicon layer) is etched by the plasma method using a barrel type device, the cross-sectional shape of the etched gate electrode (polysilicon layer) is side-shaped as shown by the broken line in Figure b. It has an etched trapezoidal shape and is tapered. However, since the pattern width is different from the standard, a problem arises in terms of the accuracy of the semiconductor device.
本発明の目的は、半導体基板表面に絶縁膜を介
して形成されるポリシリコン層の表面から、不純
物イオンを添加して、該ポリシリコン層内の不純
物濃度が表面から該絶縁膜に近い側へ漸次小さく
なるように拡散させる工程と、次いで、該ポリシ
リコン層表面に選択的にレジスト膜をパターニン
グ形成する工程と、次いで、該レジスト膜をマス
クにして、該ポリシリコン層を、前記絶縁膜表面
が露出しないように、しかも該ポリシリコン層と
該レジスト膜の界面に平行な方向へのエツチング
量が、該界面から該絶縁膜に近い側へと漸次小さ
くなるようにエツチングする工程と、次いで、該
レジスト膜がパターニングされた部分以外のポリ
シリコン層を、前記絶縁膜が露出するまで異方性
エツチングして、該ポリシリコン層の残余を上部
側面がなだらかであり、かつ他の側面が該絶縁膜
表面に対して略垂直な面であるゲート電極とする
工程と、次いで、該レジスト膜を剥離した後、少
なくとも該ゲート電極上部側面が露出しないよう
に、少なくとも該ゲート電極上部側面が露出しな
いように該ゲート電極表面に絶縁被膜を形成する
工程とを含むことを特徴とする半導体装置の製造
方法によつて達成される。 An object of the present invention is to add impurity ions from the surface of a polysilicon layer formed on the surface of a semiconductor substrate via an insulating film, so that the impurity concentration in the polysilicon layer is reduced from the surface to the side closer to the insulating film. a step of diffusing the polysilicon layer so as to gradually become smaller; a step of selectively patterning a resist film on the surface of the polysilicon layer; a step of etching so that the polysilicon layer and the resist film are not exposed, and the amount of etching in a direction parallel to the interface between the polysilicon layer and the resist film gradually decreases from the interface to the side closer to the insulating film; The polysilicon layer other than the portion where the resist film is patterned is anisotropically etched until the insulating film is exposed, and the remaining polysilicon layer is etched so that the upper side surface is smooth and the other side surface is the insulating layer. A step of forming a gate electrode with a surface substantially perpendicular to the film surface, and then, after peeling off the resist film, at least an upper side surface of the gate electrode is formed so that at least an upper side surface of the gate electrode is not exposed. This is achieved by a method for manufacturing a semiconductor device, which is characterized in that it includes the steps of: forming an insulating film on the surface of the gate electrode.
以下、添付図面を参照して本発明の実施例を説
明する。 Embodiments of the present invention will be described below with reference to the accompanying drawings.
第２図は本発明の方法を実施する工程における
ゲート電極（ポリシリコン層）を断面で示す図で
あり、図において、１はシリコン基板、２は二酸
化シリコン（SiO2）膜、２３，２３′，２３″は
ポリシリコン層、４はレジスト膜、５はりん・け
い酸ガラス（PSG）膜である。同図を参照する
と、そのａにおいてポリシリコンの導電層２３を
形成するために、りん(P)をドーピングするが、本
発明では、ドーピングされたゲート電極（ポリシ
リコン層）内のりん濃度に変化をつけるため、２
段階に分けて、すなわち初めに通常の拡散法によ
り、第３図に示す如き拡散装置によつてりん(P)の
ドーピングを行う。同図において、３１は拡散
炉、３２はウエハで、窒素（N2）ガス取入口３
３より流入し、排気口３４より真空装置を経て排
気される。同拡散装置によつてりん(P)のドーピン
グを行なう場合、窒素（N2）雰囲気中で拡散源
としてPOCl3（液体）を用い、拡散炉内温度は拡
散炉外部の加熱体（図示せず）による熱で900℃
に保たれている。このとき拡散されるりん(P)の拡
散深さは約4000〓である。かゝるドーピングによ
つてポリシリコン層２３は導電性を有するように
なる。次に、イオン打ち込み（Ion
Implantation：I.I.）法によつて再びりん(P)をド
ーピングする。かゝるりんのI.I.は、ドーズ量１
×1014cm-2で行われ、この場合、拡散深さは浅
く、打ち込まれたりん（P+）はゲート電極（ポ
リシリコン層）表面付近で停止する。この結果ゲ
ート電極（ポリシリコン層）内のりん(P)濃度は当
該ゲート電極（ポリシリコン層）表面付近２３′
で大きく、表面より深くなるにしたがつて小さく
なる。かゝる不純物原子りん(P)の濃度勾配をつけ
た後で、レジスト膜４を塗布し、しかる後光照射
によりパターニングをし、次いでドライエツチン
グを行なう。 FIG. 2 is a cross-sectional view of the gate electrode (polysilicon layer) in the process of implementing the method of the present invention. In the figure, 1 is a silicon substrate, 2 is a silicon dioxide (SiO 2 ) film, 23, 23' , 23'' is a polysilicon layer, 4 is a resist film, and 5 is a phosphorous silicate glass (PSG) film. Referring to the figure, in order to form a conductive layer 23 of polysilicon at a, phosphorus ( However, in the present invention, in order to change the phosphorus concentration in the doped gate electrode (polysilicon layer),
Doping with phosphorus (P) is carried out in stages, ie, first by a conventional diffusion method using a diffusion apparatus as shown in FIG. In the figure, 31 is a diffusion furnace, 32 is a wafer, and nitrogen (N 2 ) gas intake port 3
3 and is exhausted from the exhaust port 34 via a vacuum device. When doping phosphorus (P) using the same diffusion device, POCl 3 (liquid) is used as a diffusion source in a nitrogen (N 2 ) atmosphere, and the temperature inside the diffusion furnace is controlled by a heating element (not shown) outside the diffusion furnace. ) with heat of 900℃
is maintained. The diffusion depth of phosphorus (P) diffused at this time is approximately 4000㎜. Such doping makes polysilicon layer 23 electrically conductive. Next, ion implantation (Ion
Implantation: II) Dope with phosphorus (P) again. Karurin II has a dose of 1
×10 14 cm -2 , and in this case, the diffusion depth is shallow and the implanted phosphorus (P + ) stops near the surface of the gate electrode (polysilicon layer). As a result, the phosphorus (P) concentration in the gate electrode (polysilicon layer) is 23' near the surface of the gate electrode (polysilicon layer).
It is large at the surface, and becomes smaller as it gets deeper from the surface. After creating such a concentration gradient of the impurity atoms phosphorus (P), a resist film 4 is applied, patterned by irradiation with light, and then dry etched.
ドライエツチング処理は初めゲート電極（ポリ
シリコン層）内の不純物濃度によるエツチング速
度の差を利用してサイドエツチングが進行するよ
うにし、しかる後、方向性の良いエツチングを行
なう２段階からなる。初めのエツチングは第４図
の概略断面図で示されるバレル型プラズマエツチ
ング装置により行なわれ、同図において４１は拡
散炉、４２は高周波コイル、４３はウエハでCF4
ガスは取入口４４より流入し、排気口４５から真
空装置（図示せず）を経て排気される。このプラ
ズマ法によるエツチングは第２図ｂに矢印Ａで示
されるようなサイドエツチングができることを特
徴としており、当該プラズマ法によるエツチング
を続行すると第１図ｂに破線で示されるようなサ
イドエツチングがなされ、エツチングされたゲー
ト電極（ポリシリコン層）の断面の寸法が規格よ
り大きくずれてしまう。 The dry etching process consists of two steps: first, side etching is progressed by utilizing the difference in etching speed depending on the impurity concentration in the gate electrode (polysilicon layer), and then etching with good directionality is performed. The initial etching is carried out using a barrel-type plasma etching apparatus shown in the schematic cross-sectional view of FIG .
Gas flows in through the intake port 44 and is exhausted through the exhaust port 45 via a vacuum device (not shown). Etching by this plasma method is characterized by the ability to perform side etching as shown by the arrow A in FIG. 2b, and if etching by the plasma method is continued, side etching as shown by the broken line in FIG. , the cross-sectional dimension of the etched gate electrode (polysilicon layer) deviates greatly from the standard.
本発明の方法では、かゝるプラズマ法によるエ
ツチングを第２図ｂに矢印Ａで示されるサイドエ
ツチングができた段階で処理を打切り、続いてエ
ツチング方法をRIEリアクテイブ・イオン・エツ
チング）法に換え、ゲート電極（ポリシリコン
層）のエツチングを完成させる。RIEによるエツ
チングは第５図の概略断面図で示される装置によ
つて行われる。同図において、５１はチエンバ
ー、５２，５４は対向電極で一方の電極５４にウ
エハ４３が設置され、両電極間には高周波電源５
５より高周波電圧が印加される。使用するガス
（CCl4）は取入口５６より拡散炉５１内に流入
し、排気口５７より真空装置（図示せず）を経て
排気される。かゝるRIE法によるエツチングは、
パワー300〔Ｗ〕、圧力0.2〔Torr〕の四塩化炭素
（CCl4）ガスを用いて行なわれる。このときのエ
ツチング速度は4000〔〓／min〕である。RIE法
によるエツチングは方向性が良く、第２図ｂ中に
おいて矢印Ｂで示される如くエツチングされる。 In the method of the present invention, the plasma etching process is terminated at the stage when side etching as shown by arrow A in FIG. , complete the etching of the gate electrode (polysilicon layer). Etching by RIE is performed using the apparatus shown in the schematic cross-sectional view of FIG. In the figure, 51 is a chamber, 52 and 54 are opposing electrodes, a wafer 43 is installed on one electrode 54, and a high frequency power source 5 is placed between the two electrodes.
5, a high frequency voltage is applied. The gas (CCl 4 ) to be used flows into the diffusion furnace 51 from the intake port 56 and is exhausted from the exhaust port 57 via a vacuum device (not shown). Etching by the RIE method is
It is carried out using carbon tetrachloride (CCl 4 ) gas at a power of 300 [W] and a pressure of 0.2 [Torr]. The etching speed at this time was 4000 [/min]. Etching by the RIE method has good directionality and is etched as shown by arrow B in FIG. 2b.
以上２段階のエツチングにより第２図ｂに示す
如く、テーパを有した規格寸法通りのゲート電極
（ポリシリコン層）が得られる。しかる後、レジ
スト膜４を剥離し、絶縁膜（PSG）５を形成す
ると、第２図ｃに示す如く、従来方法で見られた
絶縁膜の薄い部分が同図矢印Ｃで示されるように
十分厚く形成され、従来の多層配線の際問題とな
つた絶縁不良を防ぐことができる。 Through the above two-step etching process, a tapered gate electrode (polysilicon layer) having standard dimensions is obtained, as shown in FIG. 2b. After that, when the resist film 4 is peeled off and an insulating film (PSG) 5 is formed, as shown in FIG. It is formed thickly and can prevent insulation defects that have been a problem with conventional multilayer wiring.
以上説明した如く、本発明の方法によればゲー
ト電極（ポリシリコン層）の不純物(P)濃度に変化
をもたせ当該ゲート電極（ポリシリコン層）のエ
ツチングをプラズマ法およびRIE法の各長所を生
かして２段階に分けて行うことによりパターン幅
の精度の良いしかもテーパを有したゲート電極
（ポリシリコン層）を形成することができ、かゝ
るテーパを有するため、絶縁膜をゲート電極（ポ
リシリコン層）上に十分な厚さで均一に形成する
ことができ、多層配線の際生ずる絶縁膜破損によ
る絶縁不良を防止することができ、半導体装置の
信頼性を高めるに寄与する。 As explained above, according to the method of the present invention, the impurity (P) concentration of the gate electrode (polysilicon layer) is varied, and the etching of the gate electrode (polysilicon layer) takes advantage of the advantages of the plasma method and the RIE method. By performing this in two steps, it is possible to form a gate electrode (polysilicon layer) with a high precision pattern width and a taper. It can be formed uniformly to a sufficient thickness on a multilayer wiring layer, and can prevent insulation defects due to damage to the insulation film that occur during multilayer wiring, contributing to improving the reliability of semiconductor devices.
第１図は従来方法におけるポリシリコン層のパ
ターニングを示す断面図、第２図は本発明の方法
によるポリシリコン層のパターニングを示す断面
図、第３図は拡散炉の概略断面図、第４図はバレ
ル型プラズマエツチング装置の概略断面図、第５
図はRIE型エツチング装置の概略断面図である。
図中、１はシリコン基板、２は二酸化シリコン
（SiO2）膜、３，２３，２３′，２３″はポリシリ
コン層、４はレジスト膜、５はりん・けい酸ガラ
ス膜（絶縁膜）、３１，４１，５１は拡散炉、３
２，４３はウエハ、３３，４４，５６は取入口、
３４，４５，５７は排気口、４２は高周波コイ
ル、５２，５４は対向電極、５５は高周波電源を
示す。
FIG. 1 is a cross-sectional view showing patterning of a polysilicon layer by a conventional method, FIG. 2 is a cross-sectional view showing patterning of a polysilicon layer by the method of the present invention, FIG. 3 is a schematic cross-sectional view of a diffusion furnace, and FIG. 5 is a schematic cross-sectional view of a barrel-type plasma etching apparatus.
The figure is a schematic cross-sectional view of an RIE type etching apparatus. In the figure, 1 is a silicon substrate, 2 is a silicon dioxide (SiO 2 ) film, 3, 23, 23', 23'' are polysilicon layers, 4 is a resist film, 5 is a phosphorous/silicate glass film (insulating film), 31, 41, 51 are diffusion furnaces, 3
2, 43 are wafers, 33, 44, 56 are intake ports,
34, 45, 57 are exhaust ports, 42 is a high frequency coil, 52, 54 are counter electrodes, and 55 is a high frequency power source.
Claims (1)
ポリシリコン層の表面から、不純物イオンを添加
して、該ポリシリコン層内の不純物濃度が表面か
ら該絶縁膜に近い側へ漸次小さくなるように拡散
させる工程と、 次いで、該ポリシリコン層表面に選択的にレジ
スト膜をパターニング形成する工程と、 次いで、該レジスト膜をマスクにして、該ポリ
シリコン層を、前記絶縁膜表面が露出しないよう
に、しかも該ポリシリコン層と該レジスト膜の界
面に平行な方向へのエツチング量が、該界面から
該絶縁膜に近い側へと漸次小さくなるようにエツ
チングする工程と、 次いで、該レジスト膜がパターニングされた部
分以外のポリシリコン層を、前記絶縁膜が露出す
るまで異方性エツチングして、該ポリシリコン層
の残余を上部側面がなだらかであり、かつ他の側
面が該絶縁膜表面に対して略垂直な面であるゲー
ト電極とする工程と、 次いで、該レジスト膜を剥離した後、少なくと
も該ゲート電極上部側面が露出しないように、該
ゲート電極表面に絶縁被膜を形成する工程と を含むことを特徴とする半導体装置の製造方法。[Claims] 1. Impurity ions are added from the surface of a polysilicon layer formed on the surface of a semiconductor substrate via an insulating film, so that the impurity concentration in the polysilicon layer is lowered from the surface to the side closer to the insulating film. a step of selectively patterning a resist film on the surface of the polysilicon layer; and a step of diffusing the polysilicon layer into the insulating film using the resist film as a mask. a step of etching so that the surface is not exposed and the amount of etching in a direction parallel to the interface between the polysilicon layer and the resist film gradually decreases from the interface toward the side closer to the insulating film; , the polysilicon layer other than the part where the resist film is patterned is anisotropically etched until the insulating film is exposed, and the remaining polysilicon layer is etched so that the upper side surface is smooth and the other side surface is smooth. forming a gate electrode with a surface substantially perpendicular to the surface of the insulating film; and then, after peeling off the resist film, forming an insulating film on the surface of the gate electrode so that at least the upper side surface of the gate electrode is not exposed. A method for manufacturing a semiconductor device, comprising the steps of:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10288281A JPS584932A (en) | 1981-06-30 | 1981-06-30 | Manufacture for semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10288281A JPS584932A (en) | 1981-06-30 | 1981-06-30 | Manufacture for semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS584932A JPS584932A (en) | 1983-01-12 |
| JPH0359577B2 true JPH0359577B2 (en) | 1991-09-11 |
Family
ID=14339233
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10288281A Granted JPS584932A (en) | 1981-06-30 | 1981-06-30 | Manufacture for semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS584932A (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59181539A (en) * | 1983-03-31 | 1984-10-16 | Toshiba Corp | Manufacture of semiconductor device |
| JPS60735A (en) * | 1983-06-16 | 1985-01-05 | Pioneer Electronic Corp | Formation of electrode |
| JPS6025249A (en) * | 1983-07-22 | 1985-02-08 | Pioneer Electronic Corp | Manufacture of semiconductor device |
| US5316616A (en) * | 1988-02-09 | 1994-05-31 | Fujitsu Limited | Dry etching with hydrogen bromide or bromine |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS50118673A (en) * | 1974-03-01 | 1975-09-17 | ||
| JPS5470771A (en) * | 1977-11-16 | 1979-06-06 | Cho Lsi Gijutsu Kenkyu Kumiai | Dry etching method |
| JPS5487172A (en) * | 1977-12-23 | 1979-07-11 | Hitachi Ltd | Manufacture for simiconductor device |
-
1981
- 1981-06-30 JP JP10288281A patent/JPS584932A/en active Granted
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS50118673A (en) * | 1974-03-01 | 1975-09-17 | ||
| JPS5470771A (en) * | 1977-11-16 | 1979-06-06 | Cho Lsi Gijutsu Kenkyu Kumiai | Dry etching method |
| JPS5487172A (en) * | 1977-12-23 | 1979-07-11 | Hitachi Ltd | Manufacture for simiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS584932A (en) | 1983-01-12 |
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