JPS60219759A - Manufacture of semiconductor ic device - Google Patents

Abstract

PURPOSE:To improve the dielectric strength of the upper end of a groove by rounding this upper end by a method wherein the side surface of a stepwise difference formed by side-etching the periphery of the groove is coated with a thin film having a thickness of the side-etching amount, and is then directively etched. CONSTITUTION:An Si oxide film 8 is deposited on the surface of an Si substrate 2, and next an Mo film 9 is deposited. Then, after the film 9 is etched by using the patterned resist as a mask, an aperture region is formed in the substrate surface by etching the film 8. The groove 3 is formed by etching by using the film 9 as a mask; thereafter, the substrate 2 is exposed to the peripheral region 12 of the groove 3 by side-etching the side surface of the film 8 to the same degree as the thickness of the film 8. After the side surface of the stepwise difference of the film 8 is coated in arc form with an Si oxide film 13 with a thickness of the side-etching amount or more, the film 13 is removed with it left on the region 12, and then the upper end of the groove is rounded by reactive ion etching.

Description

Detailed Description of the Invention (Field of Industrial Application) The present invention relates to a semiconductor integrated circuit device formed using a groove formed on the surface of a silicon substrate. The present invention relates to a method of manufacturing a device.

(Prior art) In the conventional trench forming method, as shown in Figure 1, reactive ion etching ( Since the grooves 3 are formed on the surface of the silicon substrate 2 by RIE (RIE) or a parallel plate type etching device t, the upper ends 4 of the grooves are at right angles. Therefore, as shown in FIG. 2, when the silicon oxide film 5 is formed by heat-treating the trench surface in an oxidizing atmosphere at 900° C. to 1000° C., the silicon oxide film 5 becomes extremely thin at the upper end portion 4 of the trench. However, as a result, the trench type capacitor using silicon oxide 11#5 as an insulating film has the disadvantage that its dielectric strength deteriorates significantly. In addition, when forming a dielectric region using a trench, if a silicon oxide film is deposited as the insulating thin film 6 by, for example, the CVD method, as shown in FIG.
il) 7 was generated and the grooves could not be completely filled.

(Object of the Invention) An object of the invention is to provide roundness to the upper end of a groove formed in a semiconductor integrated circuit device in order to eliminate these drawbacks.

(Construction of the Invention) To achieve the above object, the present invention includes a step of forming a patterned laminated film consisting of at least two layers on a silicon substrate, and etching the surface of the silicon substrate using an lAf mask for the upper layer of the laminated film. a step of performing Zide etching on the lower layer film of the laminated film, then removing the upper layer film of the laminated film, and forming a step of the lower layer film in the peripheral region of the groove; The process includes a step of etching a thin film having a film thickness equal to or greater than the step side + b side etching amount of the F layer film, and a step of etching the silicon substrate gold directionally in the peripheral region of the thin film and the groove. The gist of the invention is a method of manufacturing a semiconductor integrated circuit device.

Next, the present invention will be described in detail, but the embodiments are merely illustrative, and without departing from the spirit of the present invention, all modifications and improvements may be made.

(Example 1) As shown in FIG. 4, a silicon oxide film 8 is deposited on the surface of a silicon substrate 2 by a CVD method, and then a molybdenum film 9 is deposited by a vapor deposition method or a sputter deposition method.

Next, 5th r5! The above molybde 71199f is etched onto the patterned resist 10'i mask as shown in J. The etching is carried out using, for example, an etching apparatus with parallel plate electrodes using CC1tR and oxygen. The silicon oxide film 8 is then etched by reactive ion etching using CF4 and hydrogen to form an opening region 11 on the surface of the silicon substrate.

Next, as shown in FIG. 6, an elastomer plate @3 is formed on the silicon substrate using the molybdenum film 9 as a mask.

Next, as shown in FIG. 7, silicon is oxidized using a buffered hydrofluoric acid solution. Side etching is performed on the side surface 1 of the silicon oxide film 8 to the same extent as the thickness of the silicon oxide film 8 to expose the silicon substrate in the peripheral region 12 of the groove 3.

Next, after removing molybdenum mk using a mixture of sulfuric acid and hydrogen peroxide, a silicon oxide film 8 is formed as shown in FIG.
A silicon oxide film 13 having a thickness greater than that of the side etching is cut out from the side surface of the step. The cylindrical shape is obtained, for example, by a so-called high temperature CVD method using SI L + N20'C at 800°C. In this CVD method, almost the same film thickness is deposited on the flat surface and the step end face, so that the step of the silicon oxide film 8 is thicker than the peripheral region 1 of the trench 3.
Silicon oxide film 1 whose surface shape is an arc at 211C
Covered by 3.

In this embodiment, a silicon oxide film formed by the island temperature CVD method was used to cover the steps of the silicon oxide film 8, but the steps can also be covered with a silicon oxide film formed by the bias sputtering method.

Next, as shown in FIG. 9, the silicon oxide film 13 on the silicon oxide film 8 is etched by reactive ion etching using CF and hydrogen. Ii[3
A silicon oxide film 13 is left in the peripheral region 12 of the semiconductor device.

Next, as shown in FIG. 1O, the silicon oxide film 13 and the silicon oxide film 13 are etched under reactive ion etching conditions in which the etching rates of the silicon and silicon oxide films are approximately equal, so that the silicon is sequentially exposed in the surrounding region 2 of the trench 30. The substrate is etched at the same time to give roundness to the upper end of the groove. Reactive ion etching conditions include, for example, CBrF, pressure 14-30 mtorr, R
F output 0.1 W/l:A is used.

Next, the silicon oxide film 13 and the silicon oxide film 8 remaining after the above-mentioned reactive ion etching are removed using a buffered hydrofluoric acid solution to form a groove with a rounded top end as shown in FIG.

(Embodiment 2) (Applicable to trench type MOS capacitor) A case where an MO8 type capacitor is formed on the trench surface will be explained. In this embodiment, a case will be described in which a silicon oxide film is used in place of the molybdenum film used as an etching mask in the first embodiment. In FIG. 12, a silicon oxide film 14 with a thickness of 50 to 500 mm is formed by thermal oxidation on the surface of a silicon substrate 20, and a silicon nitride film 15 is sequentially formed on it with a thickness of 50 mm.
~2000 large, silicon oxide film 16'l-thickness 0.4~
0.611m, silicon substrate @ 17'i thickness 50
0 to 2000 A t and the thickness to of the silicon oxide film 18 is, for example, 0.
4 to 1.0 pm Deposited by CVD method. The thickness of the silicon oxide film 16 is set to be larger than the amount of side etching described below.

Next, as shown in FIG. 13, a silicon oxide film 18. which is deposited by the CVD method on a patterned resist 19 mask. Silicon lacquered film 17. silicon oxide 111f
i16. The silicon nitride film 15 and the silicon oxide 11114 formed by thermal oxidation are removed by reactive ion etching to form an opening 11t.

For example, CF, H2 gas is used for the etching.

After removing the resist 19, the silicon substrate 2 is etched using a silicon oxide yi418i mask to form a groove 3, as shown in FIG. 8g14. In this etching, 5iC44 is used, for example, since the etching rate of silicon is higher than that of a silicon oxide film.

Film thickness t of silicon oxide wA18 deposited by CVD method
0 is the depth of the groove formed on the surface of the silicon substrate 'ktB + the etching rate of the silicon oxide film in reactive ion etching of silicon is the etching rate of silicon or times the etching rate of silicon, then to > rt, (1) It is necessary that , and the thickness t of the silicon oxide film 18 remaining after silicon reactive ion etching,
is the side etching depth td of the silicon oxide film 16 which will be described in the next step, then t, < d (2). Since t, = to-rt, the thickness t0 of the silicon oxide film 18 to be deposited is becomes r ts < to < r ts + d (3).

Next, as shown in FIG. 15, the silicon oxide layer 16' is side-etched to a depth d using a buffered hydrofluoric acid solution. d
is made approximately equal to the film thickness of silicon oxide l116. At this time, the silicon oxide film 18 remaining on the silicon nitride film 17 is completely removed, and the thermally oxidized silicon oxide film 14 is slightly side etched.

Next, the silicon nitride film 17 is removed using phosphoric acid heated to about 160° C. as shown in FIG.

At this time, a part of the silicon nitride @ 15 exposed by side etching of the silicon oxide 14916 is also removed.
A region 12 having a width d is formed around the groove.

Next, as shown in FIG. 17, a silicon oxide film 20 with a thickness of about d is deposited, for example, by high-temperature CVD, to cover the steps of the silicon oxide NlAl6. At this time, the silicon oxide layer protrudes from the side surface of the silicon oxide film 16: l
tp is the film thickness on a flat surface. Next, as shown in FIG. 18, the silicon oxide film is etched by reactive ions. The reactive ion etching conditions may be the same as those for CVD silicon oxidation described above. At this time, reactive ion etching is performed to such an extent that the silicon substrate is not exposed at the end of the groove 3 formed on the surface of the silicon substrate. The determination of completion of reactive ion etching is not strict, and the point is that it is sufficient to prevent the silicon substrate 2 from being exposed at the end of the groove 3.

Next, as shown in FIG. 19, the remaining silicon oxide film 20 and the region 12 around the trench 30 are sequentially etched by reactive ion etching of the silicon oxide film 20 in a Shimada pattern. As the reactive ion etching conditions, for example, d
CBrF=, pressure 14~3Q m torr,
By using the RF output o, t W/crd 'c,
The upper end of the groove 3 is rounded.

The reactive ion etching is performed so that the silicon substrate is exposed and etched around the groove 3, so that no step is formed on the silicon substrate at the end of the silicon nitride film 15.

Next, after removing the silicon oxide film 20 remaining on the cap 3 with a buffered hydrofluoric acid solution, the silicon substrate was etched using a mixed solution of nitric acid, hydrofluoric acid, and acetic acid to remove the damaged layer caused by reactive ion etching, as shown in Figure 20. Surface layer thickness 200~
Remove 500A.

Next, silicon formula @15 and thermal oxidation silicon oxide film 1
After removing 4, as shown in FIG. 21, a trap capacitor insulating film 21t is formed to a thickness of 1000 Å by thermal oxidation, and a capacitor electrode 221 is formed using polycrystalline silicon doped with phosphorus. Instead of polycrystalline silicon doped with phosphorus as a capacitor electrode, polycrystalline silicon doped with impurities such as arsenic or polycrystalline silicon with no added impurities is deposited, and then impurities such as phosphorus and arsenic are diffused or ionized. It is possible to use a material that has been doped with Eri for injection or the like. Alternatively, it goes without saying that a metal such as molybdenum or a silicide such as molypsilicide may be used as the electrode. In order to prevent defects in the capacitor insulating film, the capacitor insulating film may be formed by removing the oxide III formed on the silicon substrate surface by so-called sacrificial oxidation before forming the capacitor electrode, and then performing thermal oxidation again.

(Example 3) (Groove MO with groove [11i[n #'
(Application to S capacitor) After forming a groove with rounded groove ends as shown in FIG. 20 using a p-type silicon substrate in Example 2, a second
As shown in FIG. 2, f) K, PSG 23 is deposited, and phosphorus is diffused onto the surface of the silicon substrate in the trench by heat treatment in a violet atmosphere to form an n-type layer 24. Instead of solid phase diffusion from PSG, solid phase diffusion from arsenic doped glass or poct
It is also possible to create an n-type layer by vapor phase diffusion from s.

Next, after removing the PSG using a buffered hydrofluoric acid solution and removing the silicon nitride film 15 and the thermally oxidized silicon oxide film 14, the capacitor insulating film and electrodes are formed as described with reference to FIG. When a p-type layer is provided on the inner surface of the groove, an n-type substrate is used, and boron-doped glass or the like is used for the p-type diffusion layer.

(Example 4) (Application to separator isolation) In FIG. 20 of Example 2, thermal oxidation is carried out completely, a silicon oxide film 5 is formed on the inner surface of the groove shown in FIG. 23, and then a CVD silicon oxide film is formed. 26 to fill the trench. In order to completely fill the trench, the thickness of the silicon oxide film 26 is set to be at least half the width of the trench.

Next, as shown in FIG. U, the silicon oxide film 26 is etched by reactive ion etching to remove the silicon oxide film 26 in areas other than the grooves.

Next, as shown in FIG. 25, the silicon nitride film 15 and silicon oxide film 14 are removed.

In order to fill the @, instead of the CVD silicon oxide film 26 in FIG. 23, polycrystalline silicon is deposited to a thickness of more than half the trench width as shown in FIG. 26, and then, for example, a parallel plate electrode structure is formed. CCt using the etching V apparatus of
A structure may also be used in which polycrystalline silicon in areas other than the grooves is removed by directional etching using a gas such as the like, and the surface of the polycrystalline silicon n remaining in the groove areas is thermally oxidized to form a silicon oxide film base.

(Effects of the Invention) As explained above, according to the present invention, since the upper end of the groove is rounded, the silicon oxide film at the upper end of the groove can be thinned and the electric field concentrated. Since the pressure is relaxed, the breakdown voltage is improved.

In addition, when applied to the separation area, the rounded top of the groove makes it easier to deposit a thin film inside the groove compared to when the top of the groove is at a right angle, resulting in scratches. It has the effect of suppressing

[Brief explanation of drawings]

Figure 1 is a cross-sectional view of a groove formed by a conventional groove forming method, Figure 2 is a cross-sectional view of a silicon oxide film formed when thermally oxidizing a groove surface vrJ whose groove ends are perpendicular to each other, and the third figure is a cross-sectional view of a groove formed by filling the groove. Figures 4 to ii show examples of the method for forming grooves according to the present invention, and Figures 12 to 21 show the resulting scratches (beards) in each manufacturing process when a non-explosion 8A is applied to a groove-shaped MOS capacitor. 22 is a cross-sectional view of a groove-type MOS capacitor in which an n-type layer is formed on the inner surface of the groove;
Figure 251 is a cross-sectional view of each manufacturing process when applied to element isolation. FIG. 26 shows a cross-sectional view when element isolation is performed using polycrystalline silicon and a structure whose surface is thermally oxidized. ■... Etching-resistant thin film 2... Silicon substrate 3... Grooves 4 formed on the silicon substrate surface...
... Groove top end 5 ... Silicon oxide film 6 formed by thermal oxidation
...Insulator thin film 7...S (full) 8...Silicon oxide film deposited by CVD method 9...Molybdenum film lO... Buttered resist 11...
... Opening 12 ... Groove peripheral region 13 ... Silicon oxide film 14 ... Silicon oxide film 15 ... Silicon enriched film 16 ... ... Silicon oxide film 17 ... Silicon enriched film 18 ... Silicon oxide film 19 ... Resist 20 ... Silicon oxide film 21 ... ... Capacitor insulating film 22 ... Capacitor electrode 23 ... PSG 24 ... N-type layer substrate ... Silicon oxide film 26 ... CVD silicon oxide film...
Polycrystalline silicon...Silicon oxide film Fig. 4 Fig. 5 Fig. 6 Fig. 8 Fig. 11 Fig. 13 Fig. 17 Fig. 20 Fig. 23 Fig. 25

Claims (1)

[Scope of Claims] A step of forming a patterned laminated film consisting of at least two layers on a silicon substrate, a step of etching the surface of the silicon substrate using the upper layer of the laminated film as a mask to form a groove; A step of side etching the T layer of the laminated film, then removing the upper layer of the laminated film, forming a step of the lower layer in the peripheral area of the groove, and removing the step opening of the lower layer by the amount of zide etching. A semiconductor integrated circuit device characterized by comprising the steps of forming a thin film having a thickness of at least 100% or more, and directionally etching the thin film and the silicon substrate in the peripheral area of the groove. Production method.