JPS63185043A - Manufacturing method of semiconductor device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] Industrial applications The present invention relates to a method of manufacturing a semiconductor device.

Conventional technology Semiconductor MO8) As for isolation technology between transistors,
Conventionally, the LOCO8 method has been commonly used, and in recent submicron transistors, the BOX method (1983 IΣD
M83-27 Toshiba) is beginning to be applied.

Problems to be solved by the invention The LOCO8 method is shown in FIG. As shown in the figure, when a part of the substrate 1 is oxidized using the pads SiO2, Si3N48 on the silicon substrate 1 as a mask to form an oxide film 9o, a part of the oxide film called a bird's beak 9 is formed.
By narrowing the effective channel width of the transistor formed in the 1A portion, a phenomenon called a narrow channel effect occurs as shown by the curve 10o in FIG. For this reason, it is difficult to apply to element isolation of 2 μm or less. FIG. 3 shows the narrow channel effect, and the curve 2oO is the method of the present invention, 3, which will be described later.
00 indicates the reverse channel effect of the conventional BOX method.

An example of the BOX method for this category is shown in FIG.

An oxide film 2 and a PolySi 3 are formed on a substrate 1, and the substrate 1 is dry-etched using the PolySi 3 and the oxide film 2 as masks in areas that will become isolation regions. Next, CVDS
i○2e is deposited and resist 7 is applied by spin coating. Thereafter, dry etching is performed under etching conditions such that the etching speeds of the resist 7 and the CvDSlo 26 are equal to each other for planarization. Finally, Po1ySi 3 and 510 in the element area
22 is selectively removed.

Unlike the BOX method and the Locos method, there is no encroachment of 5IO2 into the device region, so this method is suitable for miniaturization of devices. However, the BOX method also has drawbacks.

This is because electric field concentration occurs at the corner (edge) 40o, the threshold voltage at the corner decreases, and an excessive current flows at the corner, resulting in the transistor characteristics 50 shown in Figure 6.
A hump current shown at 0 flows.

Note that eoo is a normal characteristic. For this reason, LOCO9
An inverse narrow channel effect occurs, which is the opposite of the law.

Therefore, at the stage of Figure 4(,), as shown in Figure 6,
A method of suppressing the hump current is to perform diagonal ion implantation and heat treatment to raise the threshold voltage of a part of the corner. 6o is an injection region, and 51 is a diffusion region. However, with this method, Po1ySt 3 and 5iO32
is on the surface, making it impossible to inject sufficiently. Furthermore, since the injection is performed from the side, the efficiency of injection from the side itself is poor due to the influence of reflection. Therefore, in order to obtain a sufficiently high threshold voltage at a portion of the corner, it is necessary to increase the implantation concentration. Then, the implanted ions seep into the channel portion, which affects the characteristics. Therefore, it is difficult to control the injection amount.

Therefore, an inclined box shown in FIG. 7 was proposed.

By sloping a portion of such a corner, electric field concentration at the portion of the corner is reduced. This makes it possible to reduce the amount of ion implantation required to lower the threshold at some corners. Therefore, seepage of implanted ions into the channel portion can also be reduced. However, in this case, although transistors are formed in the regions IA and 1B, for example, there is a drawback that the isolation voltage between adjacent transistors is reduced.

Means for Solving the Problems In order to solve the above problems, the present invention provides a layer in contact with the semiconductor of the multilayer film on the element region used as a mask for etching the semiconductor in the field region in the BOX separation method, or By side-etching the layer on the insulating film that is in contact with the semiconductor and forming the insulating film buried in the field region also in the side-etched part, an insulating film thicker than the gate oxide film is formed in a part of the corner of the element region. This suppresses electric field concentration in a part of the corner.
This suppresses the pump current.

Operation According to the present invention, an insulating film thicker than a gate oxide film can be formed on a portion of a semiconductor corner of an element region by the method described above. Furthermore, the portion where the thick insulating film is to be formed is the portion where side etching has been performed. Since this side etching can be performed during selective etching of the multilayer film, any side etching can be performed. Therefore, it is possible to form a thick insulating film with any desired width in a part of the corner.

This makes it possible to reduce electric field concentration at a portion of the corner and suppress a drop in threshold voltage at the portion of the corner. In other words, h
The pump current can be suppressed.

Example FIG. 1 shows an embodiment of the present invention.

(,), 20 nm of 5io2 (thermal oxide film) 2,140 nm of PolySi 3.500 nm on Si substrate 1
After forming the PSG4 in the field region, the PSG4 in the field region is dry etched, and then the Po1ySi3 is further etched. At this time, PolySi 3 is etched under the conditions of side etching of 50 nm. 510 below
22, selective etching of Po1ySi3 can be performed, and arbitrary side etching is possible.

(b) In the figure, 51022 and the portion of the Sl substrate 1 that will become the field region are etched by 500 nm by anisotropic dry etching using the PSG 4 as a mask. Since anisotropic dry etching is used, the edges of PSG4, 51022, and St substrate 1 coincide, and only the edge of Po1ySi3 is recessed by 50 nm.

(C) After removing PSG4, CVD5iO25 is deposited. In this step, a thick insulating film 16 can be formed in a part of the corner. Furthermore, a resist 6 is applied to flatten the surface.

(d) In the figure, Po1ySi was etched under the drive etching conditions of etching CVD5IO
Etching is performed until the surface of No. 3 is exposed, and Sio2 for isolation is formed in the field region.

(-) In the figure, Po1ySi 3 and 5iO2 on the element region
Remove 2. As a result, an element isolation structure separated by JSt02g is formed.

After that, a part of the element formation region 1 of the substrate 1 is
Gate oxide film, gate electrode, source at 0.

A transistor (not shown) is manufactured by forming a drain and the like.

By this method, it is possible to form an insulating film thicker than the gate oxide film in a part of the corner of the element region. Moreover, the width of this thick insulating film corresponds to the amount of side etching, and this side etching can be performed when selectively etching a multilayer film, so any side etching can be performed. Therefore, it is possible to form a thick insulating film in any desired width of a part of the corner. The cross-sectional shape of the present invention is similar to LOGO8 separation, but LOCO8 separation differs greatly from the present invention in that the encroachment of Si (~) cannot be controlled.

This makes it possible to reduce electric field concentration at a portion of the corner and suppress a drop in threshold voltage at the corner. In other words, h
The pump current can be suppressed.

Since an insulating film thicker than the gate oxide film is formed at a corner part of the effect element region of the invention, electric field concentration at the corner part can be suppressed. Therefore, it is possible to suppress a decrease in the threshold voltage at a part of the corner, and it is possible to suppress the hump current.

Further, the thick insulating film region in a part of the corner is determined by the amount of side etching. Since this side etching can be performed during selective etching of the multilayer film, any side etching can be performed. Therefore, it is possible to form a thick insulating film in any desired width of a part of the corner.

In this way, the present invention enables semiconductor elements to be formed at high density without a slight deterioration in performance, and is suitable for large-scale LSI
This greatly contributes to the production of

[Brief explanation of the drawing]

Figure 1 is a cross-sectional view of the process of an embodiment of the present invention, Figure 2 is a cross-sectional view of the process of the r, ocos method, Figure 3 is a diagram showing the channel width effect of each separation method, and Figure 4 is the conventional BOX method. Figure 6 is a cross-sectional view of the process of conventional 1...S1 substrate, 2
...SiO2,3...Po1ySi. 4-------P SG, is, 1es'--・-
-CVDf3*02.6...Resist, 1o.
...Element formation area. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
f! 1 and lS Fig. 1 Wi2 Fig. 3 Mask tea r7-ru' Machinawate 19 lips Fig. 4 Fig. 5 OVll. Figure 6t//Figure 117

Claims (1)

[Claims] A step of forming a multilayer film on a semiconductor substrate and etching a field region of the semiconductor substrate using the multilayer film as a mask, and etching a layer of the multilayer film remaining on the element formation region that is in contact with the semiconductor substrate or the semiconductor A step of side-etching a layer on an insulating film in contact with the substrate, a step of forming an insulating film in the side-etched portion and a field region, and a step of forming a semiconductor element on the element formation region. A method for manufacturing a featured semiconductor device.