JPS6025249A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent recess filling polysilicon from being hollowed by a method wherein an impurity layer with fast etching rate is formed on the surface of a substrate to be an inclined surface with arbitrary angle. CONSTITUTION:An impurity layer 10 is formed on the surface of a silicon semiconductor substrate 1 to be coated with a resist layer 4 for patterning process. When these layers are isotropically etched, the etching rate in the region from the surface of substrate to the impurity layer 10 is accelerated e.g. assuming the downward direction to be 1.0, the lateral direction will be 0.7. The inclined angle of the impurity layer 10 will be e.g. 40-60 deg.. Moreover after the substrate 1 is vertically etched down to the specified depth, an SiO2 film 2 is formed on the surface of the substrate 1 including a recess 1a and polysilicon 3 is deposited on the film 2. Furthermore, the recess is etched to be filled with the polysilicon 3 and finally the surface of the polysilicon 3 in the recess 1a may be oxidized to be an isolated separation region.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) The present invention relates to a method for manufacturing a semiconductor device for forming a recessed portion in a device layer IL, and in particular,
Reactive ion etching is used in the manufacturing process of SI.

This invention relates to a method for making four-part coins according to R11;).

For example, as an isolation technology between elements such as transistors, LO
It has a CO8 structure. This involves selective oxidation using St and N4 as a mask to thicken the oxide film and perform element isolation. However, in the oxidation process, both ends of the 5isN4 film swell up, creating a gap between the isolation region and the element region. The boundary part gradually becomes thinner toward the element region like a bird's beak (called a bird's peak), and since no element can be formed in this part, the area ratio of the isolation region increases both in the element region and in the other direction. This is a factor that hinders higher density.

Therefore, in order to solve this problem, as shown in FIG. 1, a recess 1a is formed in the substrate as an isolation region, and the inside of the recess 1a is filled with polysilicon or SiO! A structure has been proposed in which it is buried. This four part la is made by the trench method using the above-mentioned RIE.

However, in such a configuration, the s t ox film 2 is formed on the fundamental wave surface including the four parts 1a, and then the recess 1a is filled with polysilicon 3. However, since the steps of the recess 1a are at right angles, the polysilicon 3 is Due to the poor step coverage of the silicon 3, a hollow 3a is likely to be formed inside, as shown in FIG.

To solve this problem, as shown in FIG. 2, using the patterned resist layer 4 as a mask, first perform isotropic etching to form a sacroslant surface with a predetermined angle α, and then perform RIE. A structure in which vertical side walls are formed by anisotropic etching has been taught.

Since the stepped portions of the four portions 1a have the inclined surfaces as described above, it is possible to prevent hollows from forming in the polysilicon that is subsequently filled.

However, in isotropic etching to form an inclined surface, the etching rate l/C in the downward direction is 1, whereas the etching rate in the lateral direction is usually about 0.7, so the inclination angle α cannot be made large enough, and , the angle cannot be set freely.

Therefore, in view of the above-mentioned problems of forming recesses, the present invention aims to improve the step coverage of polysilicon by forming an impurity layer with a fast etching rate on the substrate surface and forming an inclined surface with an arbitrary angle. The present invention provides a method for manufacturing a semiconductor device according to the present invention.

Hereinafter, the manufacturing method according to the present invention will be explained with reference to sectional views of the process steps shown in FIGS. 3g to 3.

First, ion implantation or solid diffusion is performed on the surface of the silicon semiconductor substrate 1 using phosphorus or arsenic as an impurity,
An impurity layer 10 is formed (FIG. 3g). Next, a resist layer 4 is coated over the entire surface of the substrate, and portions that will become separation regions are patterned by photolithography (FIG. 3b). In this state, the substrate surface exposed by patterning is subjected to isotropic etching using the resist 4 as a mask. From the substrate surface to the impurity layer 104, the etching rate is fast; for example, when the downward direction is 1.0, the etching rate in the opposite direction is 0.7 (FIG. 3C).

The inclination angle of this impurity layer 10 is set to, for example, 40° to 60'. Furthermore, anisotropic etching is performed in the vertical direction to a predetermined depth of the substrate 1 by RIE (Fig. 3d).
, the resist 4 is removed once.

Next, 810 t% 2 of J is formed on the surface of the substrate including the four parts 1a (FIG. 3e), and shibori silicon 3 is immersed in oil on the substrate surface by low pressure CVD (FIG. 3f).

Then, the polysilicon 3 is etched in the trench to the extent that the SiO film 2 on the substrate surface is exposed, and the four parts 1a are filled with polysilicon 3* (Fig. 3g), and finally the surface of the polysilicon 3 in the recess 1a is etched. is oxidized so that polysilicon 3 is buried in the four parts 1a to form an insulating isolation region (FIG. 3h).

In the above embodiment, the etching rate of the impurity layer 10 can be arbitrarily set by controlling the amount of impurity introduced in the step shown in FIG. 3g.

Therefore, the inclination angle is also arbitrary without being limited to the embodiment.

As described above, according to the present invention, the inclination of the openings of the four element isolation parts can be controlled arbitrarily, so it is possible to prevent hollows from forming in the polysilicon filled in the recesses, and improve step coverage. be able to.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a conventionally proposed element isolation structure, FIG. 2 is a diagram showing a further improved isolation structure, and FIGS. 110
FIG. 1... Silicon substrate 1a... Concavity 10... Impurity layer 2... Si ox film 3... Polysilicon 3 &...・Hollow 4... Resist patent applicant Pioneer Co., Ltd.

Claims (1)

[Claims] A process of forming an impurity layer with a high etching rate on the surface of a semiconductor substrate by ion implantation, a process of forming a resist layer on the surface and applying a pattern for element isolation, and a process of opening holes in the resist layer by vacuuming. the impurity layer is isotropically etched from the substrate (7) t") to a constant depth to form four parts for element isolation. A method for manufacturing a semiconductor device, characterized in that: