JPS621243A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To improve the capacity of element isolation by forming a projecting type substrate region at a predetermined position, depositing an insulating film and flattening the surface when shaping a groove for element isolation. CONSTITUTION:A thermal oxide film layer 32 and an silicon nitride film 33 are formed onto a P-type silicon substrate 31, the silicon nitride film 33 and the thermal oxide film 32 are patterned, and a plasma CVD film 34 is deposited on the whole surface. The plasma CVD film 34 is etched with ammonium fluoride. Etching quickly progresses at a stepped section at that time, and the plasma CVD film 34 takes an etched shape. Grooves are shaped to the peripheral sections of a groove for element isolation through etching while using the plasma CVD film 34 as a mask, the plasma CVD film 34 is removed through etching by ammonium fluoride, and the grooves for element isolation are formed while employing the silicon nitride film 33 as a mask. The silicon nitride film 33 and the thermal oxide film 32 are removed, and a plasma CVD film 35 is buried into the grooves.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device, in particular, in order to electrically isolate each element on a semiconductor substrate, an insulating film is provided in an element isolation region. The present invention relates to a method of manufacturing a semiconductor device in which a semiconductor device is embedded.

[Technical background of the invention and its problems]

Semiconductor device using silicon as a semiconductor, special VCMO
In 811 semiconductor devices, a thick oxide film is formed in so-called field regions (element isolation regions) between elements in order to eliminate insulation defects due to parasitic channels and to reduce parasitic capacitance.

Conventionally, as an element isolation method using such an oxide film, a portion of the silicon substrate in the field area is processed.

A method is used in which a trench is formed by using a protrusion, and a field oxide film is buried therein so as to be flat using CVD technology.

The prior art will be briefly explained using FIG. 2. Figure 2<a
) As shown in K, Pfli in countries with a specific resistance of 5 to 50Ω
(100) A silicon substrate 21 is prepared, and a groove having a depth of, for example, about 0.6 μm is formed in the element isolation region. next,
As shown in FIG. 2(b), an insulating film 22 having the same depth as the groove is uniformly deposited on the surface of the substrate by, for example, CVD. Next, as shown in FIG. 2(C), a surface flattening layer [24] that can flatten the surface is formed. As the leveling film, for example, a plasma CVD film is used.

Thereafter, as shown in FIG. 2(d), the flattened film 24
When the insulating film 22 and the insulating film 22 are etched from the surface under etching conditions in which the etching rates for both are substantially equal to expose the substrate surface above the element region, the groove in the element isolation region is filled with the insulating film 22.

However, in the above-mentioned conventional method, when the element isolation region is made finer and the width of the groove is narrowed in order to increase the degree of integration, there is a problem that the element isolation ability decreases.

[Purpose of the invention]

The present invention improves the drawbacks of the conventional method described above, and provides a semiconductor device with a convex substrate region within a groove for device isolation, thereby increasing the device isolation ability due to the shielding effect of the convex substrate region. The purpose is to provide a method for manufacturing the device.

[Summary of the invention]

According to the present invention, a convex substrate region is provided at a predetermined position when forming a trench for device isolation. Thereafter, an insulating film is further deposited to flatten the surface as in the conventional method.

〔Effect of the invention〕

According to the present invention, since there is a convex substrate region in the groove provided for element isolation, a shielding effect (the line of force terminates in the convex substrate region, and the semiconductor substrate at the bottom around the groove (It becomes difficult to terminate), the element isolation ability is improved. Therefore, the reliability of the integrated circuit can be improved.

[Embodiments of the invention]

FIG. 1(a) is a top view of a semiconductor device manufactured according to the present invention, and FIG. 1(b) is a sectional view taken along line XX' in FIG. 1(a).

Examples of the present invention will be described below using fs3 diagrams. As shown in Figure 3(a), the specific resistance is 5 to 500 na.
A P-type (100) silicon substrate 31 of i1 degree is prepared, for example, a thermal oxide film layer 32 is formed to a thickness of 50 nm, a silicon nitride film 33 is further formed to a thickness of 0.15 μm, and then the silicon nitride film 33. The thermal oxide film 32 is etched in the element isolation region.
Patterning for masks. Next, for example, plasma C
A VD film 34 is deposited over the entire surface to a thickness of 0.35 μm.

Next, as shown in FIG. 3(b), the plasma CVD film 34 is coated with a thickness of, for example, 0.1 μm using concentrated ammonium.
etching. At this time, etching progresses quickly at the difference portion, and the plasma CVD film 34 takes on the etched shape shown in FIG. 3(b).

Next, as shown in FIG. 3(C), the plasma CVD
Using the film 34 as a mask, perform RIE Ic etching to a depth of, for example, 0.3 μm around the trench for element isolation.
form a groove.

Next, as shown in FIG. 3(d), the plasma CVD film 34 is removed by etching with concentrated ammonium.

Next, as shown in FIG. 3(e), etching is performed by RIB using the silicon nitride film 33 as a mask.
Form trenches for element isolation.

Next, as shown in FIG. 3(f), unlike the conventional technique, the silicon nitride film 33. The thermal oxide film 32 is removed, and the groove is further filled with, for example, a plasma CVD film 35.

Thereafter, a gate oxide film and a source are formed in the element formation region in the same manner as in the normal MO8 type semiconductor device manufacturing process.

A transistor is created by forming a drain diffusion layer.

According to this embodiment, since there is a convex substrate region in the groove provided for element isolation, the element isolation ability can be improved due to the shielding effect.

[Brief explanation of drawings]

FIGS. 1(a) and (b) are diagrams for explaining the element isolation method of the present invention, FIGS. 2(a) to (d) are process cross-sectional views for explaining the conventional element isolation method, and FIG. Figures (a) to (f) are process cross-sectional views explaining one embodiment of the present invention. In the figure, 1.21.31...Silicon substrate, 2.22,24,34.35...P9. (MaCVD
1l, 32... thermal oxide film, 33... silicon nitride film. Representative Patent Attorney Kensuke Norichika (and 1 other person) (cL)? 2 11th M (α) Figure 2 t(L) (e) tf) $ Figure 3

Claims (1)

[Claims] forming a mask material in the center of the element isolation region of the semiconductor substrate; etching only the peripheral part of the element isolation region of the semiconductor substrate using the mask material as a mask;
a step of removing the mask material, a step of forming a trench in the element isolation region so that the peripheral part of the trench is deeper than a central part of the trench, and a step of burying an insulator in the trench of the element isolation region. and forming an element on a substrate outside the element isolation region.