JPS61290737A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To provide a high-temperature integrated circuit, by forming first trenches with a given depth on a semiconductor substrate, by leaving selectively oxidation-resistant thin films around the step sections of the trenches, and by forming second deep and narrow trenches around the step sections of the first trenches. CONSTITUTION:On a section for an element to be formed on a semiconductor substrate 11, a mask material film 14 is formed. The mask material film on sections to form element separation regions is selectively removed, and first trenches 11A, 11B with a given depth are formed in the substrate 11. A oxidation-resistant thin film 17 is formed at the trench sections 11A, 11B. The thin film 17 is selectively left around the step sections of the trenches 11A, 11B. Using the thin film 17 as a mask, an insulating film 19 is formed. Using the thin film 17 and the insulating film 19 as a mask, around the step sections of the trenches 11A, 11B, second narrow and deeper trenches 23A, 23B are formed. The element separating material is left in the trenches 23A, 23B. In this way, a high-performance integrated circuit can be provided.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing a semiconductor integrated circuit or the like by improving isolation technology between elements.

2. Description of the Related Art In recent years in the manufacture of semiconductor devices, research has been conducted into methods of separating integrated elements using insulators. For example, the Technical Digest International Electron Devices Meeting (TECHNIC
AL DIGEST INTERNATIONAL E
LCTRON DEVICE MEETING) 19s
3PP, 27-30 describes a method for simultaneously forming narrow isolation regions and wide field regions. This prior art will be explained with reference to FIG. (a)
In the process, the element isolation regions on the silicon substrate 31 are selectively etched to form grooves 32A and 32B. Φ
), an insulating film 33 is deposited, and a first resist 34 is formed in the wide isolation portion using an exposure method.

A resist film is coated thereon to form a second resist film 35. As a result, resist is filled on the narrow isolation portion (groove 32A) and on the wide isolation portion (groove 32B) to make the entire area flat. Thereafter, the resist films 35, 34 and the insulating film 33 are etched at the same etching speed up to the broken line in FIG. 36A, 36B and element formation region 37
Form it flat. (d) Element formation area 3 in the process
7 and MOS) transistor T1. Form T2. Reference numerals 38 and 39 denote a source, a drain/drain, 40 a gate insulating film, and 41 a gate electrode.

This method is characterized by the fact that it requires one more photomask in the process, and is not necessarily a simple manufacturing technique.

On the other hand, a method of forming a narrow and deep isolation region and a wide and shallow isolation region (field region) in a self-aligned manner is disclosed in Patent Application No. 14853 of 1988; When forming separation regions with two photomasks,
Since a lift-off method or the like is used, it cannot necessarily be said to be simple, and a more specific and easy method is desired.

Problems to be Solved by the Invention The present inventors have already developed a method in the Showa era of forming both narrow and wide separations simultaneously in a self-aligned manner without increasing the number of photomasks and with a small pattern conversion difference. Although it was disclosed in Patent Application No. 44337 of 1959, Bar Polar IC, CMO
It has not been possible to present a method for simultaneously forming a narrower, deeper isolation region and a wider, shallower isolation region, which are effective for 9I, in a self-aligned manner using a single photomask process. In view of these conventional problems, the present invention increases the number of photomasks.

Means for Solving the Problems In order to solve these problems, the present invention includes a step of forming a mask material film on a portion of a semiconductor substrate where an element is to be formed;
selectively removing the mask material film on the region where element isolation is to be formed and forming a first groove portion of a predetermined depth in the semiconductor substrate; forming an oxidation-resistant thin film in the groove portion;
a step of selectively leaving the thin film in the periphery of the gap of the groove, a step of forming an insulating film using the oxidation-resistant thin film as a mask, and a step of masking the fabric material film and the insulating film. The present invention provides a method comprising the steps of forming a narrower and deeper second groove in the periphery of the groove, and leaving an element isolation material in the second groove. .

For production According to the method according to the invention, a bipolar IC.

MO3IC (Specially KCMO3) 'K around the li element, it is possible to form a narrow and deep isolation region with a process that requires fewer photomasks compared to the conventional method so that pattern conversion is small, and parasitic channel current between elements can be prevented. It is possible to provide a method for manufacturing a high-performance integrated circuit that is excellent in preventing chip-up and the like.

Example An embodiment of the present invention will be described below.

First, a mask material film is formed on a portion of a predetermined silicon semiconductor substrate for MOS or bipolar where an element is to be formed. As for the structure of this mask material film, a single film or various composite films of two or more layers can be used. As the film material, a silicon nitride film, a thick insulating film such as CU D -3102, or a conductive film such as silicide or high melting point metal may be used depending on the case. The most preferable mask material film is about 2000 to 3000 m
A two-layer film with a mericon nitride film of about 80% is considered.

Next, the pattern of the mask material film is changed by a photo mask process to expose the surface of the semiconductor substrate in the area where the element isolation region is to be formed, and further, by etching, narrow and wide first patterns are formed in the substrate. Form a groove. As an etching method, reactive ion etching method (R
Grooves with vertical steps can be formed by anisotropic etching such as IE), and if an etching solution that is anisotropic to the crystal plane is used, device characteristics with less pattern conversion can be achieved. A groove portion having tapered side surfaces with excellent properties can be formed.

Next, an oxidation-resistant film is formed over almost the entire surface of the semiconductor substrate. Various methods can be considered as such methods, such as forming a thermal nitride film directly on the substrate surface and forming a silicon nitride film by deposition. As the most preferable deposited film material, a silicon nitride film based on a thin thermal oxide film can be used.

Next, a mask material is left around the step portion of the groove portion.

The condition is that no photomask is used at this stage. One such method is to apply a fluid organic thin film, such as a photoresist film or a silica film, to the step between a narrow groove and a wide groove using a spin coating method. A thin layer is formed in the center of the groove,
Lightly etch the mask material to leave it around the step in the groove.

Another method is to deposit phosphosilicate glass (PSG) or the like on the entire surface and etch the main plane of the semiconductor using an anisotropic etching method such as RIE, leaving a mask material around the steps. can.

Next, using the mask material left around the stepped portion as a mask, the oxidation-resistant film within the groove portion is removed. After that, the mask material film is further removed. However, depending on the mask material used, it may be removed in a later step.

Next, by a thermal oxidation method, the portion where the heat-resistant film is not formed is oxidized, and a wide silicon oxide film is formed to almost the same height as the main plane of the area where the semiconductor element is to be formed. . At this time, a narrow trench formed with a wide oxide film is formed around the area where the element is to be formed.

Next, the bottom surface of the narrow groove is etched more deeply using the mask material film pattern on the area where the element is to be formed and the wide oxide film as a mask. As a result, a narrow and deep second groove portion is formed.

Next, the second groove is filled with a separation material.

Such filling methods include direct oxidation, depositing a separation material film over the entire surface to a thickness sufficiently thicker than half the width of the narrow groove, and back-etching the separation material film flat from the surface. A possible method is to leave the separation material in the groove portion of No. 2. As the separation material, a low-melting insulating material such as COD 5102 + silicon nitride film, an insulator such as Ar1.203, or various types of silicide glass may be used. Furthermore, a conductive material such as polycrystalline silicon or silicide can also be used as an isolation material. In this case, at least a portion of the surface of the semiconductor substrate is oxidized or oxidized for insulation before depositing the conductive material. After nitriding, it is filled with a conductive material.

Furthermore, by normal integrated circuit manufacturing methods, 1vfO
3. Forming various elements such as bipolar.

As described above, according to the method of the present invention, a narrow and deep isolation region having an arbitrary depth around the element portion and a wide and shallow isolation region connected to this in a self-aligned manner form the area where the element is to be formed. It was possible to provide a semiconductor device that can be formed at the same height as the main plane of the semiconductor device and has excellent planarization.

FIG. 1 is a cross-sectional view of an M○S integrated circuit formed by the method of the present invention, in which a narrow deep isolation region and a wide shallow isolation region are formed around a transistor.

Further, a specific force membrane of the present invention will be explained using FIGS. 2(a) to (i). Hereinafter, the formation of an MO3 integrated circuit element will be described in detail as an example.

First, as shown in FIG. 2(a), a silicon oxide film (Si02
) 1000 layers 12, and then a silicon nitride film (S
After depositing 2,000 layers of iN) 13, a resist pattern 14 is formed by a photomask process, and using this as a mask, the oxide film 12, nitride film 13, and silicon substrate 11 are etched to a depth of approximately soo.

A narrow groove portion 11A and a wide groove portion 11B were formed in the groove, and boron was implanted into the bottom surface of the groove portion to form a channel stop region 15.

Next, as shown in FIG. 2(b), a resist pattern 14 is formed.
is removed and thermally oxidized to form a thin oxide film 16 of about 50 OA.
A silicon nitride film 17 of about 700 layers was formed on the entire surface, and a resist 18 was formed by spin coating to a thickness sufficiently thicker than half the width of the narrow groove.

Next, as shown in FIG. 2(c), the resist 18' (z-back etching is performed using an anisotropic etching method such as RIE, and the resist 18' is etched at the gap in the groove around the area where the element is to be formed. was left as a mask, and the nitride film 17 was etched using this as a mask.

Next, as shown in FIG. 2(d), a resist pattern 18 is formed.
was removed, and an oxidation-resistant silicon nitride film 17 was formed only in the vicinity of the gap in the trench.

Next, as shown in FIG. 2(e), using the oxidation-resistant nitride film masking material 13.17 as a mask, the bottom surface of the wide trench is thermally oxidized to form a wide field oxide film 19 with a width of about 1 μm, and the device is removed. So that the height is about the same as the main plane of the planned part,
An oxide film 19 was formed within the trench.

Next, as shown in FIG. 2(, f), the silicon nitride film is etched by approximately 700 layers to remove the nitride film 17, and the nitride film 13, oxide film 12, oxide film 19, etc. are used as masks to remove the device. RIE the bottom of the narrow groove around the planned formation area.
Etching is performed using an anisotropic etching method such as 1.
Narrow grooves 2OA, 2oB' with a depth of 5μ! ! i-
A channel stop region 21 was formed at the bottom of this deep groove by ion implantation of Boro 7 or the like.

Next, as shown in FIG. 2(q), the exposed semiconductor substrate 1
The surface of 10 is thermally oxidized to form an oxide film 22 of approximately 10000 m thick, the nitride film 13 is removed, and a polysilicon film 23 is formed with a thickness sufficiently thicker than half the width of the narrow grooves 2OA and 20B. , deposited on the entire surface.

Next, as shown in FIG. 2(h), the surface of the polysilicon film (poly 5i) 23 is flattened and back-etched to expose the surface of the oxide film 12.19, and the polysilicon film is formed into a deep narrow groove. The surface was then thermally oxidized to form an oxide film 24.

As a result, the surface of the deep narrow trench is insulated with the oxide film 22, and a polysilicon film 22 is formed as an isolation material inside the oxide film 22.
3A and 23B were filled to form a deep narrow element isolation region integrated with the oxide film 19 which will become a wide element isolation region.

Next, as shown in FIG. 2(i), polysilicon 26A is formed using a normal MOS/IC manufacturing method.

Gate 25B, n type circulation areas 26A, 26B.

n-channel MOS with 26C and 26D as source and drain) Rangemetal T1. Here, an example that should be improved is that the channel stop region is not formed on the side surface of the narrow groove, so when forming the narrow groove, the side surface is etched into a tapered shape. It is preferable to form a channel cut on this side surface by ion implantation or the like.Also, although this embodiment targets the n-channel O8, the method according to the present invention applies to the P-channel MO3, 0MO3, It is possible to employ this method as a manufacturing method for various semiconductor devices such as bar polars.

Effects of the Invention As described above, according to the present invention, the element isolation region of semiconductor devices such as MOS and bipolar can be formed with a small number of photo-mask steps, with small pattern conversion differences, good flatness, and a narrow area around the element to an arbitrary depth. Since the insulation is achieved by using the insulator, it is possible to obtain a structure that has excellent performance in preventing latch-up and the like and is suitable for miniaturization, so it is possible to realize a method of manufacturing a semiconductor device that is excellent in high integration and high performance.

[Brief explanation of the drawing]

(Figure 1 shows a MOS manufactured by an embodiment method of the present invention)
Cross-sectional views showing the structure of transistors, Figures 2(a) to (i)
3A to 3D are process cross-sectional views for explaining the manufacturing method of this embodiment, and FIGS. 3A to 3D are process cross-sectional views for explaining the conventional method. 11...P-type semiconductor substrate, 11A, 11B. 2OA, 20B...-Groove, 12, 16, 19° 22.24.27...Oxide film, 13.17...
...Nitride film, 15, 15A, 16B, 21...
...P type O channel cut area, 18...Resist, 23° 23A, 23B, 2sA, 25B
...Polysilicon, 26A, 28B, 26C,
26D-...n+ type semiconductor region. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure ff=-δshij! Gum! tS (6,8 N)
N no Q Figure 2 Figure 3

Claims (6)

[Claims] (1) A step of forming a mask material film on a portion of a semiconductor substrate where an element is to be formed, selectively removing the mask material film on a region where an element isolation is to be formed, and forming a first mask material film to a predetermined depth on the semiconductor substrate. a step of forming a groove, a step of forming an oxidation-resistant thin film in the groove, a step of selectively leaving the thin film around the gap of the groove, and a step of forming the oxidation-resistant thin film in the groove. A semiconductor device comprising the steps of: forming an insulating oxide film as a mask; and forming a narrow and deep second trench in the periphery of the trench using the mask material film and the insulating film as a mask. Production method. (2) In the step of selectively leaving a thin film around the difference in the groove, a deposited film is used and the deposited film is left only around the difference by anisotropic etching,
2. The method of manufacturing a semiconductor device according to claim 1, which includes a step of selectively leaving the thin film by etching the remaining deposited film as a mask. (3) At least a portion of the semiconductor substrate surface of the second groove is insulated, and furthermore, a separating material such as a conductive material film or an insulating material film is left in the groove. A method for manufacturing a semiconductor device. (4) The method for manufacturing a semiconductor device according to claim 1, wherein a separating material such as an insulating material film is left in the second groove. (5) The method for manufacturing a semiconductor device according to claim 2, wherein the deposited film is an organic thin film such as a photoresist film or a silica film. (6) The method of manufacturing a semiconductor device according to claim 1, wherein an oxidation-resistant mask material is used as the mask material formed on the portion of the semiconductor substrate where elements are to be formed.