JPH02290044A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To make it possible to completely bury a wiring layer in an aperture part having a high aspect ratio by a method wherein a recessed part having a large opening is formed on the position where a contact hole will be formed, and a contact hole having a small opening is formed on the bottom of the recessed part. CONSTITUTION:A recessed part having a wide opening width is formed at the position, where a contact hole will be formed, on a first insulating film 27 of the BPSG film on the polycrystalline silicon wiring layer 24a located on a silicon substrate 21. An insulating film 33, which is similar to the film covering the above-mentioned recessed part 32, is provided and when a contact hole 35a, having a small opening width and reaching a layer 24a, is perforated on the bottom face of the recessed part 32, an aperture part having high aspect ratio is formed, and an aluminum wiring 36 can be buried completely.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method of manufacturing a semiconductor device having fine contacts.

2. Description of the Related Art In recent semiconductor devices, as elements become denser and more highly integrated, wiring and contact portions are becoming increasingly finer. A conventional method for forming a contact structure will be described in detail with reference to process cross-sectional views of FIGS. 5fa) to 5(f).

First, selective oxidation (selective oxidation) for device isolation with a film thickness of about 500 nm is performed on one main surface side of the silicon substrate 1 using a known technique.
A LOGOS film 2 is formed in a predetermined area. Thereafter, a gate oxide film 3 having a thickness of 20 nm is formed. Next, the film thickness is 30
A polycrystalline silicon gate layer 4a and a polycrystalline silicon wiring layer 4b having a thickness of 0 to 500 nm are formed. After that, using the polycrystalline silicon gate layer 4a as a mask, the diffusion layer (diffusion layer wiring) 5 is
ion implantation, annealing to activate the ions, and M
An OS type semiconductor element is formed. After that, an oxide film 6 with a thickness of about 300 nm is deposited over the entire surface of the substrate [Fig. 5 [a]
]. This oxide film is generally formed by a chemical vapor deposition (CVD) method.

Next, a film with a thickness of 400 nm (7)B is formed on the oxide film 6 by CVD.
A PSG film 7 is deposited. This BPSG film 7 is made of, for example, B
Impurity concentrations of approximately 3 wt% and P concentration of approximately 5 wt% are used.

Thereafter, heat treatment is performed at 900° C. for 60 minutes in a nitrogen atmosphere to cause the BPSG film 7 to flow and reduce the level difference on the substrate surface [FIG. 5(b)]. At this time, the oxide film 6 is BPSG
This prevents thermal diffusion of phosphorus (P) and boron (B) from the film 7 to the substrate.

Next, a photoresist is applied onto this BPSG film 7 and a predetermined resist pattern is formed by photolithography. Using this resist pattern as a mask, the oxide film 6 and B
The PSG film 7 is removed by etching to form a contact hole 8. Furthermore, the resist pattern is removed [Fig.
)].

Next, a polycide wiring layer 9 is formed [FIG. 5(d)]
. This polycide wiring layer 9 is composed of two layers: a lower polycrystalline silicon film 9a with a thickness of 200 nm and an upper layer tungsten silicide (WS i x ) film 9b with a thickness of 200 nm. Polycrystalline silicon film 9a is heat-treated in a nitrogen atmosphere containing a phosphorous compound to introduce phosphorus, and tungsten silicide film 9b is deposited by CVD. This wiring layer 9 is patterned using anisotropic etching such as RIE.

This polycide wiring layer 9 has lower wiring resistance than a single polycrystalline silicon layer, and can improve circuit delay due to wiring resistance.

Next, a BPS film with a thickness of 500 nm is applied to the entire surface of the substrate by CVD.
A G film 10 is deposited. This BPSG film 10 is made of, for example, B
Impurity concentrations of approximately 3 wt% and P concentration of approximately 5 wt% are used.

Thereafter, a heat treatment is performed at 900° C. for 60 minutes in a nitrogen atmosphere to cause the BPSG film 10 to flow and reduce the level difference caused by the wiring on the surface of the substrate.

Next, a photoresist is applied onto this BF'SG film 10, and a predetermined resist pattern is formed by photolithography. Subsequently, the oxide film 6 and the BPSG films 7 and 10 are removed by RIE etching using the resist pattern as a mask.
After removing the resist pattern, contact holes 11 are formed [FIG. 5(e)]. Next, an aluminum alloy wiring layer 12 is formed. This aluminum alloy wiring layer 12
is made to a film thickness of 0.005 by a well-known method such as sputtering.
It is deposited to a thickness of 8 μm and patterned by anisotropic etching such as RIE etching [FIG. 5(f)].

Through the above steps, a conventional semiconductor device is almost completed.

Problems to be Solved by the Invention However, when the size of the opening of the contact hole becomes minute, the aspect ratio (hole depth/hole width) of the opening increases to 1 or more. For this reason, the degree of coverage of the aluminum alloy film on the side wall of the contact opening decreases, and the aluminum alloy film becomes partially thin. This thinning of the film results in disadvantages such as an increase in contact resistance and a decrease in the reliability of the aluminum electrode (for example, electromigration is more likely to occur).

As described above, in the conventional semiconductor device manufacturing method, when an opening with a high aspect ratio is formed by miniaturizing the contact hole, it becomes difficult to fill the opening with an aluminum alloy film.

SUMMARY OF THE INVENTION An object of the present invention is to solve such conventional problems and provide a method for manufacturing a semiconductor device that can reliably embed a wiring layer such as an aluminum alloy film into an opening having a high aspect ratio.

Means for Solving the Problems In summary, the present invention provides that, before forming a contact hole in an insulating film, a recess with a large opening width is formed in advance at the contact hole forming position of the insulating film, and then, the recess is opened in the insulating film. A contact hole with a small opening width is formed in the bottom surface of the contact hole.

Effect: According to the manufacturing method of the present invention, the opening size of the recess at the top of the contact hole can be increased, and by reducing the shadowing effect when depositing the aluminum alloy, the side wall of the contact hole can be made larger. The coverage of the aluminum alloy is improved to reduce contact resistance and improve reliability. In addition, since the bottom of the contact hole can be drilled with high precision, it is possible to make fine interconnections with the wiring layer, and even when devices are integrated at high density, an appropriate distance between the contact hole and the gate electrode can be maintained. However, it is also possible to prevent electrical leakage between wiring layers.

Embodiment A first embodiment of the method for manufacturing a semiconductor device according to the present invention is described below.
This will be described in detail with reference to the sequential cross-sectional views of the manufacturing process of the semiconductor device shown in FIG.

First, a thermal oxide film is formed on one main surface of the P-type (100) silicon substrate 21, and a nitride film is deposited on the thermal oxide film.

Thereafter, photoresist is applied, exposed, and developed to open a window in a region where a selective oxide film (LOGOS film) for element isolation is to be formed. Next, using the photoresist as a mask, the nitride film is etched and the thermal oxide film is removed by etching to expose the surface of the silicon substrate 21. Thereafter, the photoresist is removed and the exposed silicon substrate 21 is oxidized in an oxidizing atmosphere to form a selective oxide film 22 with a thickness of about 500 nm. After this, the nitride film and thermal oxide film are removed.

Next, the surface of the silicon substrate 21 is thermally oxidized to form a gate oxide film 23 with a thickness of 20 nm, for example, and then a gate oxide film 23 with a thickness of 30 nm is formed.
-500 nm polycrystalline silicon that will become the polycrystalline silicon gate layer 24a is formed using CVD. This polycrystalline silicon is doped with impurities to lower its resistance. Doping methods include forming undoped polycrystalline silicon and then injecting impurities with ion implantation, or diffusing impurities from the vapor phase of impurity gas, or using a CVD device that produces polycrystalline silicon to form polycrystalline silicon. A method is used in which polycrystalline silicon containing impurities is formed simultaneously with the growth by mixing a gas containing an impurity element with the gas used to grow the silicon.

Thereafter, the polycrystalline silicon is etched using a photoresist with windows opened in a predetermined region as a mask using ordinary photolithography to form a polycrystalline silicon gate layer 24a.

After this, ions are implanted into the entire surface of the silicon substrate 2] and the diffusion layer (
A diffusion layer wiring) 25 is formed. At this time, the polycrystalline silicon gate layer 2 4. Each of them serves as a mask, and no ions are implanted into the silicon substrate 21 directly below the selective oxide film 22.

After forming the MOS type semiconductor device as described above, an oxide film 2 with a thickness of about 300 nm is formed on the entire surface of the silicon substrate 21.
6 is deposited using CVD [FIG. 1(a)].

Next, the oxide film 26" was deposited by CVD to a film thickness of 500 nm BPS.
A G film 27 is deposited.

For this BPSG film 27, for example, an oxide film having a poron concentration of about 3 wt% and a phosphorus concentration of about 5 wt% is used.

At this time, as the concentration of boron and phosphorus increases, the melting temperature of the BPSG film 27 decreases, allowing it to flow at a low temperature.

However, if the boron concentration is too high, the hygroscopicity of the BPSG film 27 will increase, resulting in a problem that the composition of the film will become unstable.

Furthermore, if the phosphorus concentration is too high, there will be a problem that the aluminum alloy wiring will be corroded.

For these reasons, by setting the concentrations of boron and phosphorus to appropriate values, a stable process that satisfies good planarization and reliability can be obtained.

Thereafter, heat treatment is performed at 900° C. for 60 minutes in a nitrogen atmosphere to cause the BPSG film 27 to flow and flatten the surface of the BPSG film 27 [FIG. 1(b)].

At this time, boron and phosphorus in the BPSG film 27 diffuse through the film and further into the oxide film 26, but as shown in FIG. There's nothing to do.

Next, a photoresist is applied onto the BPSG film 27, exposed, and developed to open a window at a position that will become a contact for a MOS type semiconductor element.

Using this photoresist pattern (not shown) as a mask, the BPSG film 27 is removed by dry etching, the oxide film 26 is removed by dry etching, and the gate oxide film 23 below is also dry etched to remove the silicon substrate 1.
Machining and sowing until exposed.

Contact hole 28 is formed as described above.

At this time, the dry ethoching of the BPSG film 27 was performed using a parallel plate type plasma etching apparatus, and the gas species was CHF3.
, He, O= gas mixture ratio C H F 3He O2
The total gas flow rate IQQcc/
Etching was performed at min., RF power of 500 W, and etching time of 120 seconds.

After forming the contact hole 28, the photoresist on the uppermost surface of the silicon substrate 21 used as a mask is removed [FIG. 1(C)].

At this time, high-energy ions generated by dry etching collide with the silicon substrate 21 and cause defects, but the exposed surface of the silicon substrate 21 is cleaned and the natural oxide film formed on the exposed surface of the silicon substrate 21 is further removed. Defects on the surface of the silicon substrate 21 caused by dry etching are removed.

Further, the natural oxide film was removed by etching for about 1 minute using buffered hydrofluoric acid (a mixed solution of hydrogen fluoride and ammonium fluoride) as an etching solution.

Next, a polycrystalline silicon film 29a is formed on the entire surface of the silicon substrate 21.
For example, a film of 200 nm thick is deposited by CVD to cover the contact hole 28. This polycrystalline silicon film 29a is doped with impurities in the same way as the gate electrode. Here, after growing a non-doped polycrystalline silicon film, heat treatment is performed at a temperature of 900° C. in an atmosphere of gas species PH3 (phosphine).
, heat treatment was performed for 30 minutes. The polycrystalline silicon film 9a thus obtained has a resistivity of approximately 50 Ω·cm.

Specifically, the conditions for forming the polycrystalline silicon film 29a include gas species S i H. (silane) at a gas flow rate of 150cc/mi
n, the growth temperature was 600°C and the growth time was 50 minutes.

Furthermore, a tungsten silicide (WSix) film 29b
is deposited, for example, at a thickness of 20'O nm.

At this time, the tungsten silicide film 29b is formed by CVD. The formation conditions are as follows: gas species WFo (tungsten hexafluoride), SiO4 (silane), gas mixture ratio WF6/S i H4 = 1/1 6 0 total gas flow rate 15
00cc/min, growth temperature 350°C. Growth time 10
It's done in minutes.

After this, a window is opened in a predetermined region of the tungsten silicide film 29b using ordinary photolithography, and a window is opened in a predetermined area of the tungsten silicide film 29b using a reactive ion etching process.
9a is removed by etching.

At this time, the etching conditions for the tungsten silicide film 29b and the polycrystalline silicon film 29a are as follows: using a parallel plate type plasma etching device, gas species SF6,
C2C ffl2F< was carried out at a gas mixture ratio of 1:1, a total gas flow rate of 50 cc/min, an RF power of 100 W, and an etching time of 2 minutes.

In the manner described above, polycide wiring layer 29 consisting of a laminated film of polycrystalline silicon film 29a and tungsten silicide film 29b is formed.

This polycrystalline wiring layer 29 can have lower wiring resistance than that of a single layer of polycrystalline silicon that is normally used, so that when a semiconductor element is formed, circuit delay caused by wiring resistance can be improved.

After this, the photoresist is removed [FIG. 1(d)].

Next, a BPSG film 3 is formed on the entire surface of the silicon substrate 1 using CVD.
Deposit 0. The impurity concentration and growth conditions at this time were the same as those for the BPSG film 27 shown in FIG. A film with a thickness of about 300 nm is used because it is smaller than the level difference on the silicon substrate 21 when the film is heated.

Thereafter, heat treatment is performed at 900° C. for 60 minutes in a nitrogen atmosphere to cause the BPSG film 27 to flow and flatten the substrate surface [FIG. 1(e)].

Next, a photoresist 31 is applied, exposed, and developed on this BPSG film 30 to open a window at a position that will become a contact for a MOS type semiconductor element.

Using this photoresist pattern 31 as a mask, BPS
The G film 30 is removed by dry etching, and the BPSG film 27 formed of FC+ in FIG. 1 is also dry etched.

At this time, dry etching is performed to leave a thickness of about 300 to 400 nm from the BPSG film 27 to the silicon substrate 2, including the thickness of the oxide film 26, to form a recess 32 [FIG. 1(f)].

Here, dry etching of the BPSG film 30 and the BPSG film 27 is performed using a parallel plate plasma etching apparatus using gas types C H F:+, H e , and 02 at a gas mixing ratio of 4:5:1, respectively. Total gas flow rate 100cc/mi
The etching process was performed using an RF power of 500 W and an etching time of 40 seconds.

The BPSG film 27 is separated from the silicon substrate 1 by approximately 3004 0
Esoching time is controlled to leave 0 nm, and by controlling in this way, ±10
The recessed portion 32 can be formed with a variation of about 10%.

In this way, the formation of the recessed portion 32 can be realized by a stable and highly reliable process using ordinary dry etching.

Moreover, the BPSG film 2 formed in this recess 32
7 or the remaining film thickness of the oxide film 26 becomes too thick, the effect of improving the step coverage of the aluminum alloy which will be the wiring formed in the later process will be reduced.
It is necessary to use a stable and reliable tri-esotting process.

Furthermore, when the aluminum alloy wiring 36 is also brought into contact with the polycide wiring layer 29, the polycide wiring layer 29 crosses inside the recess 32, so that the side wall of the polycide wiring layer 29 becomes a steep step. Aluminum alloy step coverage deteriorates. Therefore, a recess 32 is formed in a region that completely includes the polycide wiring layer 29.
It is necessary to consider the formation position of the resist 31 pattern to prevent the formation of the resist 31 pattern.

However, when making contact with the diffusion layer 25, it is sufficient that the polycide wiring layer 29 is not completely included. Therefore, a recess 32 having a large window width can be formed even between minute wiring lines. The window width of this recess 32 is 2
Approximately 3 μm is appropriate; if it is too small, the recess 32
Since the side walls of the aluminum alloy have a steep shape, when an aluminum alloy for wiring is formed in a later step, the amount of improvement in step coverage will be reduced. On the other hand, if it is too large, the polycide wiring layer 29 will cross inside the recess 32, resulting in a steep step on the side wall of the polycide wiring layer 29, resulting in poor aluminum alloy step coverage.
The underlying flatness of the aluminum alloy wiring layer deteriorates. For this reason, it is desirable that the thickness be about 15 μm even if it is small, and about 5 μm even if it is large.

Next, after removing the photoresist 31, the BPSG is applied again.
A film 33 is deposited to a thickness of about 400 nm using CVD.

The impurity concentration in the BPSG film 33 used here is 4 wt% boron and 5 wt% phosphorus.

The impurity concentration of the BPSG film 33 used here is that the concentration of boron is increased compared to the previous two BPSG films 27.30.As mentioned earlier, as the concentration of boron and phosphorus increases, the melting temperature of the BPSG film 33 increases. This is because the temperature decreases and it can flow at low temperatures.

However, if the boron concentration is too high, the hygroscopicity of the BPSG film 33 increases, causing a problem that the composition of the film becomes unstable.

Furthermore, if the phosphorus concentration is too high, there will be a problem that the aluminum alloy wiring will be corroded.

For these reasons, by setting the concentrations of boron and phosphorus to appropriate values, a stable process that satisfies good planarization and reliability can be obtained.

That is, here, the BPSG when etching is finished.
Since the height from the surface of the film 27 to the surface of the upper BPSG film 30, that is, the depth of the recess 32, is about 400,500 nm, the deposited BPSG film 33 has good step coverage.
The boron concentration is increased to ensure sufficient flow and a smooth shape at stepped portions.

In addition, as mentioned earlier, the thickness of the BPSG film 33 at this time is such that if the thickness of the remaining film inside the recess 32 becomes too thick, the effect on improving the step coverage of the aluminum alloy, which will be the wiring formed in a later process, will be reduced. It is set with consideration to what will happen.

Thereafter, a heat treatment is performed at 90° C. for 60 minutes in a nitrogen atmosphere to cause the BPSG film 27 to flow and flatten the substrate surface [FIG. 1(g)].

The heat treatment sufficiently reduces the level difference in the recess 32 and the level difference due to the wiring, and prevents disconnection and bridging (electrical short circuit) of the aluminum alloy wiring in the next process.

Furthermore, an oxide film 2 is placed in the recess 32 before the BPSG film 33 is deposited.
Even if 6 does not remain, a contact hole can be formed in the next step by depositing the BPSG film 33.

However, when the oxide film 26 and gate oxide film 23 are completely removed, the BPSG film 33 is directly applied to the silicon substrate 2.
1, it is not good to remove the oxide film 26 and gate oxide film 3 in the recess 32 because a problem arises in that impurities are diffused into the silicon substrate 21 due to heat treatment when the BPSG film 33 is flowed.

Next, a photoresist 34 is applied on the BPSG film 33.
A predetermined pattern of photoresist 34 is formed by exposure and development [FIG. 1(h)].

This photoresist 34 is provided within the recess 32 . That is, it is set to be smaller than the opening width of the recess 32 in which the BPSG film 33 is formed, but it does not mean that the same effect can be obtained simply by making it smaller than the opening width.

To explain this, the circle A of th+ in Figure 1 is shown in Figure 2.
An enlarged cross-sectional view of the area is shown. In FIG. 2, "'L"' is the pattern width when the pattern of the photoresist 34 is wide;
"j?" is the pattern width when the pattern width of the photoresist 34 is narrow, "H" is the height of the side wall of the contact hole when the pattern width is "'L", and "h" is the pattern width when the pattern width is "l". It shows the height of the side wall of the contact hole when the angle is ”°.

If the pattern width of the photoresist 34 on the BPSG film 33 is too wide (width L in FIG. 2), the BPSG film 33
If etching is performed using such a pattern of the photoresist 34, the actual height of the contact portion will be H, although the sidewall portion of the contact portion will be removed to some extent. In the present invention, the height from the surface of the silicon substrate 21 to the BPSG film 33 is about 500 rim, but in this example it is 500 nm.
If the height exceeds that level, the step coverage of the aluminum alloy in the next step will be poor.

Furthermore, it is difficult to ensure an appropriate distance between the contact hole formed by the pattern of the photoresist 34 and the polycrystalline silicon gate layer 24a, but it becomes difficult to increase the density of the semiconductor device.

On the other hand, if the pattern width of the photoresist 34 on the BPSG film 33 is too narrow (width! in FIG. 2), the B
A pattern of photoresist 34 is formed on the flat part of the bottom surface of PSG film 33, and its height }] is about 5001 m, which is equal to the height from the surface of silicon substrate 21 to BPSG film 33. However, in this example, the pattern width is from photolens 1 to 34! Therefore, as the value of l becomes smaller, the aspect ratio in the contact hole increases, and the step coverage of the aluminum alloy in the next step deteriorates.

From the above, the pattern width of the photoresist 34 is at least about the thickness of the BPSG film 33, and at the maximum it is about the width of the recessed part 33.
The most effective width is obtained by subtracting about twice the thickness of the BPSG film 33 from the width of the BPSG film 33. That is, such a maximum,
Outside the minimum range, the effectiveness of the present invention decreases as the distance from each value increases.

Next, using the pattern of the photoresist 34 as a mask, the remaining BPSG film 27, oxide film 26, and gate oxide film 23 in the recess 32 are etched to form the contact 1/hole 35.
form a. At the same time, poly→node wiring layer 2
The BPSG film 33 and the BPSG film 30 in the area where the window is opened in the pattern of the foreground 34 formed to make contact with the hole 35b are etched to make contact with the hole 35b.
is formed [Fig. 1(i)].

Here, in the contact hole 35b, since the BPSG film 30.33 formed on the polycide wiring layer 29 is thin, the aspect ratio inside the contact hole 35b is low.

Finally, an aluminum alloy wiring layer 36 is formed on the entire surface of the silicon substrate 21, and a window is opened in a predetermined area using ordinary photolithography to form a pattern of the aluminum alloy wiring layer 36 [FIG. 1 (j)]. .

Here, the aluminum alloy wiring layer 36 is deposited to a thickness of 0.8 μm by Suhanota ring.

In addition, reactive ion etching is used for etching.

In the semiconductor device formed in the above embodiment, since the upper opening width of the contact hole (recess 32) can be made large, the doping effect (aspect ratio is reduced) that occurs when the aluminum alloy wiring layer 36 is deposited. In the case of a pattern having large, steep sidewalls, the phenomenon in which materials deposited from an oblique direction are deposited on the sidewalls and not deposited on the target substrate surface is reduced. Therefore, the coverage of the aluminum alloy wiring layer 36 on the side wall of the opening of the contact hole 35a is greatly improved, and contact resistance can be reduced and a highly reliable aluminum alloy wiring layer 36 can be formed at the contact portion.

Further, since the bottom surface of the contact hole 35a can be opened with high precision, even if the width of the contact hole 35a becomes narrow, the connection to the aluminum alloy wiring layer 36 can be ensured. Furthermore, even if semiconductor elements are integrated at high density, the contact holes 3
5a and the gate electrode 24 can be secured.

In the first embodiment, an example was shown in which the method of the present invention was applied to the case where the aluminum alloy/gold wiring layer 36 was in direct contact with the diffusion layer 25 formed in the silicon substrate 2.
The polycide wiring layer 29 and aluminum alloy wiring layer 36 formed on the BPSG layer 27 are connected to the contact hole 35.
In the case of connection via the BPSG film 30, 33 on the polycide wiring layer 29, the thickness of the BPSG film 30, 33 on the polycide wiring layer 29 is thin, so the reliability of the wiring can often be maintained even if a conventional formation method is used.

However, as the integration of MOS type semiconductor devices increases, the contact hole 35b becomes finer and the aspect ratio of the contact hole 35b becomes higher.As in the case of the conventional technique shown in FIG. It becomes difficult to form wiring with

In order to solve this problem, the method of the present invention may also be applied to the contact hole 35b for connecting the polycide wiring layer 29 and the aluminum alloy wiring layer 36.

FIG. 3 shows a second embodiment of the present invention in which the method of the present invention is used when bringing an aluminum alloy wiring layer 36 into contact with the diffusion layer 25 shown in FIG. A cross-sectional view of the element when it is also brought into contact with the wiring layer 29 is shown.

The drawing numbers assigned to FIG. 3 are the same as those in FIG. 1.

A polycide wiring layer 29 is formed on the BPSG film 27 at the same time as on the diffusion layer 25 formed on the silicon substrate 21.
If a contact hole is to be formed on the BPSG film 30, as shown in FIG.
1 is coated, exposed, and developed to open windows at the contact positions on the MOS type semiconductor element, that is, the diffusion layer 25 and the contact position on the polycide wiring layer 29. After that, the BPSG film 30 is dried using the photoresist pattern 31 as a mask. Remove by etching.

At this time, in the embodiment shown in FIG. 1, the BPSG film is
Dry etching is performed to leave approximately 300,400 nm including the thickness of the oxide film 26 from 1 to form the fourth part 32, or dry etching is performed under the same conditions on the polycide wiring layer 29 to form the recess 32. Since the polycide wiring layer 29 crosses the polycide wiring layer 29, a steep step is formed between the side wall of the polycide wiring layer 29 and the side wall of the recess, which deteriorates reliability. Therefore, dry etching for forming the recesses 32 is performed on the polycide wiring layer 29.
Stop before the top of the is exposed.

After that, as shown in FIG. 3, B is applied to the entire surface of the silicon substrate 21.
A PSG film 33 is formed. After this, a photoresist pattern 34 is formed on the BPSG film 33, and contact holes 35a and 35b are formed in the BPSG film 33 using dry etching.
is formed, and an aluminum alloy wiring layer 36 is formed thereon.

However, considering the degree of coverage of the aluminum alloy wiring layer 36 in the contact hole 35a, the BPSG film has a thickness of about 300 mm from the silicon substrate 21, including the thickness of the oxide film 26.
Since it is necessary to perform dry etching to form the recess 32 so that about -400 nm remains, it is recommended that the polycide wiring layer 29 be used when the polycide wiring layer 29 is located too high from the silicon substrate 21. This causes deterioration of the element as the film becomes thinner. For this reason, it is necessary to reduce the thickness of the oxide film 26 and the BPSG film 27 to provide the polycide wiring layer 29 closer to the silicon substrate 21, and to reduce the aspect ratio of the contact hole 35a on the surface of the silicon substrate 21. By increasing the width, or by increasing the width of B in the region of the BPSG film 30 or 33 that contacts the polycide wiring layer 29
By selectively increasing the thickness of the PSG films 30 and 33, the present invention can be realized without any problems and sufficient effects can be obtained.

FIG. 4 shows a third embodiment of the present invention in which when an aluminum alloy wiring layer 36 is brought into contact with the diffusion layer 25 shown in FIG. A cross-sectional view of the element when it is also brought into contact with 24b is shown. However, FIG. 4 shows a cross section of a portion where contact is made with the polycrystalline silicon gate layer 24b.

The drawing numbers assigned to FIG. 4 are the same as those in FIG. 1.

Here, since the polycrystalline silicon gate layers 24a and 24b each have a thickness of about 0.5 μm at most, the method shown in the first embodiment can be used as is and sufficient effects can be obtained.

In addition, in the embodiments shown in FIGS. 3 and 4, similarly to the embodiment shown in FIG.
(2) The opening width of the contact hole should be set at a minimum of about the thickness of the BPSG film 33, and at the maximum, the opening width of the recess minus twice the film thickness of the BPSG film 33. It is effective to set it to a certain degree.

In addition, in any of the embodiments shown in FIG. 1, FIG. 3, and FIG. (A s S G) may also be used.

Further, the etching process for forming the recesses and holes is not limited to dry etching, but may be anisotropic etching.

In addition, in any of the above embodiments, 1
Although the case where one contact hole is formed has been described, when the interval between the recesses is narrow, it is also possible to form a plurality of recesses with one four parts and form a plurality of contact holes on the bottom surface of the recess.

In addition, in the above explanation, the contact shape is a hole, but
Similar effects can be obtained even with a groove-like shape and as long as the number of wiring layers is two or more.

Effects of the Invention As explained above, according to the manufacturing method of the present invention, the degree of coverage of the wiring layer on the side wall of the contact hole is improved by increasing the opening size of the recess in the upper part of the contact hole. , contact resistance can be reduced and disconnection of wiring layers can be prevented, and the reliability of the semiconductor device can be improved.

[Brief explanation of drawings]

1 (al to fj) are step-by-step cross-sectional views showing the method for manufacturing a semiconductor device in the first embodiment of the present invention, FIG. 2 is an enlarged view of the main part of FIG. 1 (hl), and FIG. FIG. 4 is a sectional view of a semiconductor device obtained according to a second embodiment of the invention, FIG. 5 is a sectional view of a semiconductor device obtained according to a third embodiment of the invention, and FIG. It is a process order sectional view showing the manufacturing method of a semiconductor device. 21...Silicon substrate, 22...Selective oxide film, 23...Gate oxide film, 24a, 24
b...Polycrystalline silicon gate layer, 25...
・Diffusion layer, 26 oxide film, 27.30.33...
BPSG film, 29...Polycide wiring layer, 31
．． 34...Photoresist pattern, 32...
...Concave portion, 35a, 35b...Contact hole, 36...Aluminum alloy wiring layer. Name of agent Patent attorney Shigetaka Awano Haka 1 name i3 凋K Kuzuka'%N~q4 9 Gaito Ku Basha [＼

Claims (18)

[Claims] (1) Forming a first insulating film on the first wiring layer; Forming a recess in the first insulating film on the first wiring layer; forming a second insulating film on the surface of the insulating film; an opening smaller than the opening width of the recess that reaches the first wiring layer in the first and second insulating films at the bottom of the recess; A method for manufacturing a semiconductor device, comprising: forming a contact hole having a wide width; forming a second wiring layer on the surface of the second insulating film, in the recess, and in the contact hole. (2) The method for manufacturing a semiconductor device according to claim 1, wherein the opening width of the recess is set within a range of 1.5 μm to 5 μm. (3) The method for manufacturing a semiconductor device according to claim 1, wherein the first and second insulating films are formed of BPSG films. (4) Set the opening width of the contact hole to a minimum width equivalent to the thickness of the second insulating film, and a maximum width equal to the opening width of the recess minus twice the film thickness of the second insulating film. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the width is set within a range of . (5) The method for manufacturing a semiconductor device according to claim 1, wherein a plurality of contact holes are formed in the bottom surface of the recess. (6) Forming a first wiring layer made of an impurity diffusion layer in the semiconductor substrate; Forming a first insulating film on the semiconductor substrate; Forming a second wiring layer on the first insulating film forming a second insulating film on the first insulating film and on the second wiring layer; forming a second insulating film on the first and second wiring layers, respectively; forming a third insulating film on the second insulating film so as to cover the first and second recesses; forming a third insulating film on the bottom surface of the first recess; The first above,
forming a first contact hole in the second and third insulating films that reaches the first wiring layer and has an opening width smaller than the opening width of the first recess; on the bottom surface of the second recess; forming a second contact hole in the second and third insulating films that reaches the second wiring layer and has an opening width smaller than the opening width of the second recess; the third insulating film; A method for manufacturing a semiconductor device, comprising: forming a third wiring layer on a surface, in the first and second recesses, and in the first and second contact holes. (7) The method of manufacturing a semiconductor device according to claim 6, wherein the first insulating film is made thinner and the first and second contact holes are formed in the same step. (8) The opening width of the first contact hole is made larger than the opening width of the second contact hole, and the first and second contact holes are formed in the same process. A method for manufacturing a semiconductor device according to section 1. (9) A patent characterized in that the film thicknesses of the second and third insulating films in the formation region of the second contact hole are selectively increased, and the first and second contact holes are formed in the same process. A method for manufacturing a semiconductor device according to claim 6. (10) The opening width of the first and second recesses is 1.5 μm to 5 μm.
7. The method of manufacturing a semiconductor device according to claim 6, wherein the setting is within a range of μm. (11) The method for manufacturing a semiconductor device according to claim 6, wherein the second and third insulating films are formed of BPSG films. (12) The opening width of the first and second contact holes should be set to a minimum width approximately equal to the thickness of the third insulating film, and a maximum width ranging from the opening width of the recess to twice the thickness of the third insulating film. The width minus the value,
7. The method of manufacturing a semiconductor device according to claim 6, wherein the temperature is set within the range of . (13) Claim 6, characterized in that a plurality of contact holes are formed in the bottom surface of the first or second recess.
A method for manufacturing a semiconductor device according to section 1. (14) Forming a first wiring layer made of an impurity diffusion layer in the semiconductor substrate; Forming a first insulating film on the semiconductor substrate; Forming a second wiring layer on the first insulating film a step of forming a second insulating film on the first and second wiring layers; a step of forming a second insulating film on the first and second wiring layers; a step of forming a third insulating film on the second insulating film so as to cover the first and second recesses; a step of forming a third insulating film on the bottom of the first recess;
The third insulating film has the first wiring layer reaching the first wiring layer.
forming a first contact hole having an opening width smaller than the opening width of the recess; forming the contact hole in the second and third insulating films on the bottom surface of the second recess, reaching the second wiring layer; forming a second contact hole having an opening width smaller than the opening width of the second recess; on the surface of the third insulating film, in the first and second recesses, and in the first and second contact holes; A method for manufacturing a semiconductor device, comprising: forming a third wiring layer therein. (15) The opening width of the first and second recesses is 1.5 μm to 5 μm.
15. The method of manufacturing a semiconductor device according to claim 14, wherein the setting is within a range of μm. (16) The method for manufacturing a semiconductor device according to claim 14, wherein the second and third insulating films are formed of BPSG films. (17) Set the opening width of the first and second contact holes to a minimum width approximately equal to the thickness of the third insulating film, and a maximum width ranging from the opening width of the recess to twice the thickness of the third insulating film. The width minus the value,
15. The method of manufacturing a semiconductor device according to claim 14, wherein the temperature is set within the range of . (18) Claim 1, characterized in that a plurality of contact holes are formed in the bottom surface of the first or second recess.
4. The method for manufacturing a semiconductor device according to item 4.