JPS63253661A - Manufacture of semiconductor memory device - Google Patents
Manufacture of semiconductor memory deviceInfo
- Publication number
- JPS63253661A JPS63253661A JP62086780A JP8678087A JPS63253661A JP S63253661 A JPS63253661 A JP S63253661A JP 62086780 A JP62086780 A JP 62086780A JP 8678087 A JP8678087 A JP 8678087A JP S63253661 A JPS63253661 A JP S63253661A
- Authority
- JP
- Japan
- Prior art keywords
- contact
- cell plate
- cvdsio2
- memory device
- semiconductor memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 239000004065 semiconductor Substances 0.000 title claims description 10
- 238000000034 method Methods 0.000 claims abstract description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 12
- 239000003990 capacitor Substances 0.000 claims description 8
- 238000010438 heat treatment Methods 0.000 claims description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims 3
- 229910052814 silicon oxide Inorganic materials 0.000 claims 3
- 238000000059 patterning Methods 0.000 claims 2
- 239000000463 material Substances 0.000 abstract description 10
- 238000000206 photolithography Methods 0.000 abstract description 4
- 230000002093 peripheral effect Effects 0.000 abstract description 2
- 238000004544 sputter deposition Methods 0.000 abstract description 2
- 229910000838 Al alloy Inorganic materials 0.000 abstract 1
- 238000007493 shaping process Methods 0.000 abstract 1
- 238000009792 diffusion process Methods 0.000 description 5
- 229910045601 alloy Inorganic materials 0.000 description 4
- 239000000956 alloy Substances 0.000 description 4
- 239000005380 borophosphosilicate glass Substances 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000005194 fractionation Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000009499 grossing Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は、スタックト形キャパシタを持つ半導体記憶装
置の製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method of manufacturing a semiconductor memory device having a stacked capacitor.
（従来の技術）
従来、このような分野の技術としては、例えば、特公昭
６０−２７８４号、特開昭５９−１７５１５３号等が挙
げられる。(Prior Art) Conventional techniques in this field include, for example, Japanese Patent Publication No. 60-2784 and Japanese Patent Application Laid-Open No. 59-175153.
第２図は従来の半導体記憶装置の製造工程断面図である
。FIG. 2 is a cross-sectional view of the manufacturing process of a conventional semiconductor memory device.
以下、この図を用いて順を追って説明する。The following is a step-by-step explanation using this figure.
まず、第２図（ａ）はトランジスタキャパシタ等の素子
の形成が終了した状態を示す断面図であり、図中、１は
シリコン基板、２はそのシリコン基板上に選択的に形成
される素子分離用酸化膜、３はＭＯＳ ）ランジスタの
ゲート酸化膜、４は多結晶等のゲート電極、５はＷ−シ
リサイド等のゲート電極配線材料、６はＰＳＧ （ｐｈ
ｏｓｐｈｏ−ｓｉｌｉｃａｔｅ ｇｌａｓｓ）サイドウ
オール、７は？ＩＯＳ ）ランジスタのソース拡散層、
８はそのドレイン拡散層、９はセルコンタクト、１０は
ドープされないＣＶＤ５ｉ（ｈ等の中間絶縁層、１１は
多結晶シリコン等のキャパシタ電極、１２は窒化膜等の
キャパシタ電極、１３は多結晶シリコン等のセルプレー
トである。次に、その上に、第２図（ｂ）に示すように
、中間絶縁膜として常圧ＣＶＤ法によるＰＳＧもしくは
ＢＰＳＧ （リン及びボロンをドープしたＳｉＯ□）１
４を成長させる。次に、第２図（Ｃ）に示すように、Ｐ
ＳＧ、 ＢＰＳＧ（以下、ＣＶＤ５ｉＯ□と総称する）
ともに９００℃以上で粘性が低下する特性があるため、
フロー（平滑化のための熱処理）を行うことにより、凹
凸形状上に成長したＣＶＤ５ｉＯ□１４は裏面張力によ
り、滑らかな形状１４′となる。なお、ｐｓｃにおいて
は１８Ｗ％（Ｐ２Ｏ３）以上で、ＢＰＳＧにおいては９
Ｗ％（［＋２０３）、１３Ｗ％（ｈｏｓ）以上で図に示
したように完全に平らな表面を得ることができる。この
後、第２図（ｄ）に示すように、ホトリソ、エツチング
を経てコンタクト１５を形成する。次いで、第２図（ｅ
）に示すように、コンタクトフローを行い、コンタクト
の上部の角を滑らかな形状１５′にする。次いで、第２
図（ｆ）に示されるように、コンタクトホールに配線材
料であるＡ１合金１６をスパッタ法により被着する。な
お、第２図（ｅ）工程でのコンタクトフローは、このへ
１合金１６を被着する際にカバレンジ（Ｔ ２ ／ 丁
＋ ）を向上させる為に必要である。First, FIG. 2(a) is a cross-sectional view showing a state in which the formation of elements such as transistor capacitors has been completed. 3 is the gate oxide film of the MOS) transistor, 4 is the gate electrode such as polycrystal, 5 is the gate electrode wiring material such as W-silicide, 6 is PSG (ph
Ospho-silicate glass) side wall, 7? IOS) transistor source diffusion layer,
8 is its drain diffusion layer, 9 is a cell contact, 10 is an intermediate insulating layer such as undoped CVD5i (h), 11 is a capacitor electrode such as polycrystalline silicon, 12 is a capacitor electrode such as a nitride film, 13 is polycrystalline silicon, etc. Next, as shown in Fig. 2(b), PSG or BPSG (SiO□ doped with phosphorus and boron) 1 is deposited on top of it by atmospheric pressure CVD as an intermediate insulating film.
Grow 4. Next, as shown in FIG. 2(C), P
SG, BPSG (hereinafter collectively referred to as CVD5iO□)
Both have the characteristic that their viscosity decreases at temperatures above 900°C.
By performing flow (heat treatment for smoothing), the CVD5iO□ 14 grown on the uneven shape becomes a smooth shape 14' due to back surface tension. In addition, in psc, it is 18W% (P2O3) or more, and in BPSG, it is 9
At W% ([+203), 13 W% (hos) or higher, a completely flat surface can be obtained as shown in the figure. Thereafter, as shown in FIG. 2(d), contacts 15 are formed through photolithography and etching. Next, Figure 2 (e
), the contact flow is performed to form the upper corner of the contact into a smooth shape 15'. Then the second
As shown in Figure (f), A1 alloy 16, which is a wiring material, is deposited in the contact hole by sputtering. Note that the contact flow in the step of FIG. 2(e) is necessary in order to improve the coverage range (T 2 /T+) when applying the 1st alloy 16 to this.
（発明が解決しようとする問題点）
しかしながら、上記した中間絶縁膜成長からコンタクト
形成までの工程は、２５６ＫＤＲＡＭ等に用いられる２
Ｎ多結晶シリコンプロセスでは十分なものであるが、３
Ｎ多結晶シリコンプロセスでは最上層の多結晶シリコン
上にも十分な膜厚を保らｃｖｎＳｉＯ□の平坦化を行な
わなければならないので、コンタクトのアスペクト比が
大きくなり、それにより配線材であるアルミニューム（
Ａｊりのカバレンジが悪くなり（０〜３０％）、抵抗の
増加、断線等が起きやすくなる。ｆた、カバレンジを良
くするため、コンタクトフローを過度に行いコンタクト
のテーバ角を大きくすると最上層の多結晶シリコン上の
中間絶縁膜Ｋ （ＣＶＤ５ｉＯ□）が薄くなるため、Ａ
Ｉとの短路などが発生しやすくなると共に、回路にＣＭ
Ｏ５構造を用いた場合、Ｐチャネル側のコンタクトでは
ＣＶＤ５ｉＯ□の中からリンがＳｉ基板内に拡散してし
まい、コンタクト部の拡散層′の表面温度が低下し、抵
抗が増加しやすくなる。(Problems to be Solved by the Invention) However, the process from the growth of the intermediate insulating film to the formation of contacts described above is difficult to achieve with the 256K DRAM, etc.
N polycrystalline silicon process is sufficient, but 3
In the N-polycrystalline silicon process, it is necessary to maintain a sufficient film thickness on the top layer of polycrystalline silicon and planarize the cvnSiO□, so the aspect ratio of the contact becomes large, which causes the aluminum wiring material to be flattened. (
The coverage range of Aj is poor (0 to 30%), and resistance increases and wire breakage are more likely to occur. Furthermore, in order to improve the coverage, if the contact flow is excessively applied and the Taber angle of the contact is increased, the intermediate insulating film K (CVD5iO□) on the top layer of polycrystalline silicon becomes thinner.
Short circuits with I are more likely to occur, and CM is added to the circuit.
When an O5 structure is used, phosphorus from CVD5iO□ diffuses into the Si substrate at the contact on the P channel side, which lowers the surface temperature of the diffusion layer' in the contact portion and tends to increase the resistance.
（問題点を解決するための手段）
本発明は、上記問題点を解決するために、スクノクト形
キャパシタを有する半導体記憶装置の製造方法において
、セルプレート多結晶シリコンのパクニングをＣＶＤ５
ｉＯｚ成長後に行い、フローすることによりセルプレー
トが存在する部分のＣＶＤ５ｉＯ０を平坦化した後、再
びＣＶＤ５ｉＯｚを成長させ、コンタクトのパターニン
グを行い、コンタクトフローするようにしたものである
。(Means for Solving the Problems) In order to solve the above-mentioned problems, the present invention provides a method for manufacturing a semiconductor memory device having a Scnoct-type capacitor, in which the cell plate polycrystalline silicon is punctured by CVD.
After iOz growth, the CVD5iO0 in the area where the cell plate is present is planarized by flow, and then CVD5iOz is grown again and contacts are patterned to perform contact flow.
（作用）
本発明によれば、上記したように、セルプレトが存在す
る領域とコンタクト周辺部との中間絶縁膜の平坦化を別
工程で行うようにしたので、セルプレートが存在する領
域では中間絶縁膜の表面は略完全に平坦化され、コンタ
クト部分では滑らかに大きなテーパー角でコンタクトを
形成することができる。従って、後の工程で配線材を被
着する際に配線材のカバレンジの向上を図ることができ
る。(Function) According to the present invention, as described above, the intermediate insulating film between the region where the cell plate exists and the area around the contact is planarized in a separate process. The surface of the film is almost completely flattened, and a contact can be formed smoothly at a large taper angle at the contact portion. Therefore, the coverage of the wiring material can be improved when the wiring material is applied in a later step.
（実施例）
以下、本発明の実施例について図面を参照しながら詳細
に説明する。(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.
第１図は本発明の実施例を示す半導体記憶装置の製造工
程断面図である。FIG. 1 is a cross-sectional view of the manufacturing process of a semiconductor memory device showing an embodiment of the present invention.
まず、第１図（ａ）に示すように、多結晶シリコン等の
セルプレート１３上ニＣＶＤ５ｉＯｚ２１を（ｈＯｓｔ
１ｍ度１３ｗ％以上、Ｂｔ０３濃度９Ｗ％以上） ４０
００〜６０００人程度成長させる。なお、その他の点は
前記した第２図（ａ）及び（ｂ）と同様であり、説明は
省略する。First, as shown in FIG. 1(a), CVD5iOz21 (hOst
1m degree 13w% or more, Bt03 concentration 9w% or more) 40
00 to 6,000 people. The other points are the same as those shown in FIGS. 2(a) and 2(b), and the explanation will be omitted.
次に、第１図（ｂ）に示すように、セルプレートのパタ
ーニングの為のホトリソを行い、ＣＶＤ５ｉＯ□２１及
びセルプレート（多結晶シリコン）１３のエツチングを
行う。Next, as shown in FIG. 1(b), photolithography is performed to pattern the cell plate, and the CVD5iO□ 21 and the cell plate (polycrystalline silicon) 13 are etched.
次に、第１図（ｃ）に示すように、９００℃〜１０００
℃程度で約２０分フローを行い、エツチングされたコー
ナ部の丸め処理を行い、丸み部２２を形成する。Next, as shown in FIG. 1(c),
Flow is carried out for about 20 minutes at a temperature of about 0.degree. C., and the etched corner portions are rounded to form rounded portions 22.
次に、第１図（ｄ） ニ示すように、ＣＶＤ５ｉＯｚ２
３を２０００〜４０００人程度（ＢｚＯｉ全面ｐｚｏｓ
ｃ度５ｗ〜１５ｗ％程度）成長させる。Next, as shown in FIG. 1(d), CVD5iOz2
3 to about 2,000 to 4,000 people (BzOi full-scale pzos
5w to 15w%).
次に、第１図（ｅ）に示すように、コンタクトのホトリ
ソを行イＣＶＤ５ｉＯｚ２３及びＣＶＤ５ｉＯｚｌＯの
工７チングを行いコンタクトホール２４を形成する。Next, as shown in FIG. 1(e), contact photolithography is performed and CVD5iOz23 and CVD5iOzlO are etched to form a contact hole 24.
次に、第１図（ｒ）に示すように、コンタクトフローを
８００〜９５０℃程度で１０分〜２０分程度行いテーバ
２５をつける。Next, as shown in FIG. 1(r), contact flow is performed at about 800 to 950° C. for about 10 to 20 minutes to attach a taber 25.
次に、第１図（ｇ）に示すように、Ａ／合金２６をスバ
ンタ法により被着し、パターニングする。Next, as shown in FIG. 1(g), A/alloy 26 is deposited by the Svanta method and patterned.
この時のカバレッジ（７！／ＴＩ）は推定で４０〜７０
％の１直が可能である。The coverage at this time (7!/TI) is estimated to be 40-70
% of 1 shift is possible.
なお、本発明は上記実施例に限定されるものではなく、
本発明の趣旨に基づいて種々の変形が可能であり、これ
らを本発明の範囲から排除するものではない。Note that the present invention is not limited to the above embodiments,
Various modifications are possible based on the spirit of the present invention, and these are not excluded from the scope of the present invention.
（発明の効果）
以上、詳細に説明したように、本発明によれば、セルプ
レートが存在する領域とコンタクト周辺部との中間絶縁
膜の平坦化を別工程で行うようにしたので、セルプレー
トが存在する領域では中間絶縁膜の表面は完全に平坦化
され、コンタクト部分では滑らかに大きなテーバー角で
コンタクトを形成することができる。従って、後の工程
で配線材を被着する際に配線材のカバレッジの向上を図
ることができる。(Effects of the Invention) As described above in detail, according to the present invention, the planarization of the intermediate insulating film between the region where the cell plate exists and the peripheral area of the contact is performed in a separate process. In the region where , the surface of the intermediate insulating film is completely flattened, and a contact can be formed smoothly at a large Taber angle at the contact portion. Therefore, it is possible to improve the coverage of the wiring material when the wiring material is applied in a later step.
第１図は本発明の実施例を示す半導体記憶装置の製造工
程断面図、第２図は従来の半導体記憶装置の製造工程断
面図である。
ｌ・・・シリコン基板、２・・・素子分画用酸化膜、３
・・・ゲート酸化膜、４・・・ゲート１掻、５・・・ゲ
ート電極配線材料、６−ＰＳＧ（ｐｈｏｓｐｈｏ−ｓｉ
ｌｉｃａｔｅ ｇｌａｓｓ）サイドウオール、７・・・
ソ°−ス拡散層、８・・・ドレイン拡散層、９・・・セ
ルコンタクト、１０・・・中間鞄縁層（ＣＶＤ５ｉＯｚ
） 、１１・・・キャパシタ電極（多結晶シリコン）、
１２・・・キャパシタ誘電体（窒化膜）、１３・・・セ
ルプレート（多結晶シリコン） 、２１．２３・・・Ｃ
Ｖ［１Ｓｉｎ、、２２・・・丸み部、２４・・・コンタ
クトホール、２５・・・テーバ、２６・・・＾１合金。
特許出願人 沖電気工業株式会社
代 理 人 弁理士 清 水 ９第１ 図 （
ぞのり
第２ 図 （そのＩ）
第２図（その２）FIG. 1 is a cross-sectional view of the manufacturing process of a semiconductor memory device showing an embodiment of the present invention, and FIG. 2 is a cross-sectional view of the manufacturing process of a conventional semiconductor memory device. l...Silicon substrate, 2...Oxide film for element fractionation, 3
...Gate oxide film, 4...Gate 1 scratch, 5...Gate electrode wiring material, 6-PSG (phospho-si
licate glass) side wall, 7...
Source diffusion layer, 8... Drain diffusion layer, 9... Cell contact, 10... Intermediate bag edge layer (CVD5iOz
), 11... Capacitor electrode (polycrystalline silicon),
12... Capacitor dielectric (nitride film), 13... Cell plate (polycrystalline silicon), 21.23... C
V[1Sin, 22...Rounded portion, 24...Contact hole, 25...Taber, 26...^1 alloy. Patent applicant Oki Electric Industry Co., Ltd. Representative Patent attorney Shimizu 9 Figure 1 (
Zonoori Figure 2 (Part I) Figure 2 (Part 2)
Claims (2)
の製造方法において、 （ａ）中間絶縁膜となる第１のシリコン酸化膜とセルプ
レートとなる堆積膜を同時にパターニングする工程と、 （ｂ）熱処理を行い、セルプレートの存在する領域のみ
を平坦化する工程と、 （ｃ）第２のシリコン酸化膜を成長させる工程と、（ｄ
）コンタクトのパターニングを行い、そのコンタクトの
熱処理を行うことにより、テーパー角の大きなコンタク
トを形成する工程を順に施すことを特徴とする半導体記
憶装置の製造方法。(1) A method for manufacturing a semiconductor memory device having a stacked capacitor, which includes (a) simultaneously patterning a first silicon oxide film that will become an intermediate insulating film and a deposited film that will become a cell plate, and (b) performing heat treatment. , a step of planarizing only the region where the cell plate exists; (c) a step of growing a second silicon oxide film; and (d) a step of growing a second silicon oxide film.
) A method for manufacturing a semiconductor memory device, characterized in that the steps of patterning a contact and heat-treating the contact to form a contact with a large taper angle are sequentially performed.
であることを特徴とする半導体記憶装置の製造方法。(2) A method for manufacturing a semiconductor memory device, wherein the deposited film in step (a) is polycrystalline silicon.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62086780A JPS63253661A (en) | 1987-04-10 | 1987-04-10 | Manufacture of semiconductor memory device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62086780A JPS63253661A (en) | 1987-04-10 | 1987-04-10 | Manufacture of semiconductor memory device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63253661A true JPS63253661A (en) | 1988-10-20 |
Family
ID=13896268
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62086780A Pending JPS63253661A (en) | 1987-04-10 | 1987-04-10 | Manufacture of semiconductor memory device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63253661A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02290044A (en) * | 1989-02-17 | 1990-11-29 | Matsushita Electron Corp | Manufacture of semiconductor device |
| US5025301A (en) * | 1986-03-26 | 1991-06-18 | Hitachi, Ltd. | DRAM which uses MISFETS in the peripheral circuit |
| EP0449000A2 (en) * | 1990-03-08 | 1991-10-02 | Fujitsu Limited | Layer structure having contact hole for fin-shaped capacitors in DRAMS and method of producing the same |
| US5362666A (en) * | 1992-09-18 | 1994-11-08 | Micron Technology, Inc. | Method of producing a self-aligned contact penetrating cell plate |
| US6482689B2 (en) | 2000-11-09 | 2002-11-19 | Micron Technology, Inc. | Stacked local interconnect structure and method of fabricating same |
-
1987
- 1987-04-10 JP JP62086780A patent/JPS63253661A/en active Pending
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5025301A (en) * | 1986-03-26 | 1991-06-18 | Hitachi, Ltd. | DRAM which uses MISFETS in the peripheral circuit |
| JPH02290044A (en) * | 1989-02-17 | 1990-11-29 | Matsushita Electron Corp | Manufacture of semiconductor device |
| US6528369B1 (en) | 1990-03-08 | 2003-03-04 | Fujitsu Limited | Layer structure having contact hole and method of producing same |
| US5705420A (en) * | 1990-03-08 | 1998-01-06 | Fujitsu Limited | Method of producing a fin-shaped capacitor |
| US6144058A (en) * | 1990-03-08 | 2000-11-07 | Fujitsu Limited | Layer structure having contact hole, method of producing the same, fin-shaped capacitor using the layer structure, method of producing the fin-shaped capacitor and dynamic random access memory having the fin-shaped capacitor |
| EP0449000A2 (en) * | 1990-03-08 | 1991-10-02 | Fujitsu Limited | Layer structure having contact hole for fin-shaped capacitors in DRAMS and method of producing the same |
| US5362666A (en) * | 1992-09-18 | 1994-11-08 | Micron Technology, Inc. | Method of producing a self-aligned contact penetrating cell plate |
| USRE36644E (en) * | 1992-09-18 | 2000-04-04 | Micron Technology, Inc. | Tapered via, structures made therewith, and methods of producing same |
| US6482689B2 (en) | 2000-11-09 | 2002-11-19 | Micron Technology, Inc. | Stacked local interconnect structure and method of fabricating same |
| US6498088B1 (en) | 2000-11-09 | 2002-12-24 | Micron Technology, Inc. | Stacked local interconnect structure and method of fabricating same |
| US6544881B2 (en) | 2000-11-09 | 2003-04-08 | Micron Technology, Inc. | Stacked local interconnect structure and method of fabricating same |
| US6555478B2 (en) | 2000-11-09 | 2003-04-29 | Micron Technology, Inc. | Stacked local interconnect structure and method of fabricating same |
| US6831001B2 (en) | 2000-11-09 | 2004-12-14 | Micron Technology, Inc. | Method of fabricating a stacked local interconnect structure |
| US6858525B2 (en) | 2000-11-09 | 2005-02-22 | Micron Technology, Inc. | Stacked local interconnect structure and method of fabricating same |
| US7314822B2 (en) | 2000-11-09 | 2008-01-01 | Micron Technology, Inc. | Method of fabricating stacked local interconnect structure |
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