JPS6196755A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPS6196755A JPS6196755A JP59217723A JP21772384A JPS6196755A JP S6196755 A JPS6196755 A JP S6196755A JP 59217723 A JP59217723 A JP 59217723A JP 21772384 A JP21772384 A JP 21772384A JP S6196755 A JPS6196755 A JP S6196755A
- Authority
- JP
- Japan
- Prior art keywords
- film
- resistor
- semiconductor device
- insulating film
- interlayer insulating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 24
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 238000000034 method Methods 0.000 claims abstract description 16
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 12
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 9
- 239000012535 impurity Substances 0.000 claims abstract description 9
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 9
- 239000010703 silicon Substances 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 238000002230 thermal chemical vapour deposition Methods 0.000 claims abstract description 5
- 229920005591 polysilicon Polymers 0.000 claims description 11
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- 150000002500 ions Chemical class 0.000 claims description 4
- 238000000059 patterning Methods 0.000 claims description 4
- 239000011229 interlayer Substances 0.000 abstract description 9
- 238000005268 plasma chemical vapour deposition Methods 0.000 abstract description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 4
- 229910052681 coesite Inorganic materials 0.000 abstract 2
- 229910052906 cristobalite Inorganic materials 0.000 abstract 2
- 238000002161 passivation Methods 0.000 abstract 2
- 239000000377 silicon dioxide Substances 0.000 abstract 2
- 235000012239 silicon dioxide Nutrition 0.000 abstract 2
- 229910052682 stishovite Inorganic materials 0.000 abstract 2
- 229910052905 tridymite Inorganic materials 0.000 abstract 2
- 239000010410 layer Substances 0.000 description 11
- 230000007423 decrease Effects 0.000 description 4
- 238000000151 deposition Methods 0.000 description 4
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 229910052739 hydrogen Inorganic materials 0.000 description 3
- 239000001257 hydrogen Substances 0.000 description 3
- 239000005360 phosphosilicate glass Substances 0.000 description 3
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 241000282326 Felis catus Species 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 229910001415 sodium ion Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Non-Adjustable Resistors (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置９％に抵抗体を有する半導体装置及
びその製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device having a resistor in 9% of the semiconductor device, and a method for manufacturing the same.
従来、半導体装置に形成される抵抗体に、例えば第４図
に示す工うに形成されてい友。丁なわち。Conventionally, resistors formed in semiconductor devices have been formed, for example, as shown in FIG. Ding nawachi.
半導体素子等が形成されたシリコン基板１上のフィール
ド酸化膜２（８ｉ０ｚ膜）上に、不純物イオンが注入さ
れ規定の抵抗値を有するポリシリコン層からなる抵抗体
３ｔ−形成する。次に、この抵抗体３上に絶縁膜として
２例えばリンシリケートガラス膜（Ｐ２Ｏ膜）４七形成
し九のち、抵抗体３の両端上のＰ２Ｏ膜に開孔部５會形
成する。続いて。Impurity ions are implanted onto a field oxide film 2 (8iOz film) on a silicon substrate 1 on which semiconductor elements and the like are formed to form a resistor 3t made of a polysilicon layer having a prescribed resistance value. Next, a phosphosilicate glass film (P2O film) 47, for example, is formed as an insulating film on the resistor 3, and after that, openings 5 are formed in the P2O film on both ends of the resistor 3. continue.
この開孔部５全通して抵抗体３と接続するＡｔ配線６を
形成する。次にパッジベージ曹ン膜及び層間絶縁膜とし
てＡｔ配線６ケ含めた表面にプラズマＣＶＤ （Ｃｈｅ
ｍｉ ｃａｔＶａｐｏｒ Ｄｅｐｏｓ ｉ ｔ ｉ ｏ
ｎ）法ニヨるシリコン窒化膜（以下Ｐ−８ｉＮ膜という
）が形成される。An At wiring 6 is formed through the entire opening 5 to be connected to the resistor 3. Next, plasma CVD (Che
mi cat Vapor Depos itio
n) A silicon nitride film (hereinafter referred to as P-8iN film) is formed.
一般に、Ｐ−８ｉＮ膜は、湿気やＮａ イオンに対する
バリヤ性の点及び段差被覆性の点で優れており、パッジ
ページ冒／膜及び層間絶縁膜に適しており多用されてい
る。In general, P-8iN films are excellent in barrier properties against moisture and Na ions and in terms of step coverage, and are suitable and widely used as pad page film and interlayer insulating films.
しかしながら、Ｐ−８ｉＮ膜を絶縁膜上に堆積しｔ場合
、抵抗体の抵抗値が減少し信頼性が著しく損われるとい
う欠点がある。特にＰ−８ｉＮＪｌｌｌ：ｉ形成したの
ちＡｔのコンタクｌｔ−とる九めの熱処理全行うと抵抗
値の低下は著しいものとなる。この原因としては、Ｐ−
８ｉＮ膜を堆積する時の下地絶縁膜の損傷及びＰ−８ｉ
Ｎ膜中に含まれる水素等の影響と考えられる。However, when a P-8iN film is deposited on an insulating film, the resistance value of the resistor decreases, resulting in a significant loss of reliability. In particular, if the ninth heat treatment is performed after forming the P-8iNJlll:i and removing the At contact, the resistance value will drop significantly. The cause of this is P-
Damage to base insulating film and P-8i when depositing 8iN film
This is thought to be due to the influence of hydrogen contained in the N film.
本発明の目的は、上記欠点を除去し、上１部にプラズマ
ＣＶＤ法によるシリコン窒化膜を形成し；
ても抵抗値の低下しない信頼性の高い抵抗体を有する
半導体装置及びその製造方法で提供することにある。The object of the present invention is to eliminate the above-mentioned drawbacks and form a silicon nitride film on the upper part by plasma CVD method;
An object of the present invention is to provide a semiconductor device having a highly reliable resistor whose resistance value does not decrease even when the resistance value is lowered even when the semiconductor device is used, and a method for manufacturing the same.
〔問題勿解決する九めの手段〕
本発明の半導体装置は、シリコン基板表面の酸化膜上に
形成され九ポリシリコン層からなる抵抗体と、該抵抗体
上に形成されｍ絶Ｒ膜と、該絶縁膜上に形成され几熱Ｃ
ＶＤ法によるシリコン窒化Ｍ（以下熱８ｉ３Ｎ４膜とい
う）と〒含んで構成される。[Ninth means for solving the problem] The semiconductor device of the present invention includes a resistor formed on an oxide film on the surface of a silicon substrate and made of a polysilicon layer, a resistor formed on the resistor, The thermal C formed on the insulating film
It is composed of silicon nitride M (hereinafter referred to as thermal 8i3N4 film) formed by the VD method.
また本発明の半導体装置の製造方法は、シリコン基板表
面の酸化膜上にポリシリコン層を形成する工程と、該ポ
リシリコン層に不純物イオン全注入し所定の抵抗値余有
する抵抗体層を形成する工程と、該抵抗体層全バターニ
ングし所定形状の抵抗体全形成する工程と、該抵抗体上
ＶＣ絶縁膜全形成する工程と、該絶縁膜上に熱ＣＶＤ法
に＝クシリコン窒化膜を形成する工程と？含んで精成さ
れる。Further, the method for manufacturing a semiconductor device of the present invention includes the steps of forming a polysilicon layer on an oxide film on the surface of a silicon substrate, and completely implanting impurity ions into the polysilicon layer to form a resistor layer having a predetermined resistance value. a step of patterning the entire resistor layer and forming the entire resistor in a predetermined shape; a step of forming the entire VC insulating film on the resistor; and forming a silicon nitride film on the insulating film by thermal CVD. What is the process? Contains and refines.
本発明に工れば、抵抗体上の絶縁膜が緻密な熱８ｉ３Ｎ
４膜に覆われるため、この上にＰ−８ｉＮ膜が形成され
ても、プラズマ発生による荷電粒子等が絶縁膜に損傷勿
与えることがなく、又Ｐ−８ｉＮ膜中の水素等の影響で
下層の抵抗体の抵抗値上低下させることはない。If the present invention is used, the insulating film on the resistor will have a dense thermal 8i3N
4 film, even if a P-8iN film is formed on top of the P-8iN film, charged particles caused by plasma generation will not damage the insulating film, and hydrogen in the P-8iN film will damage the underlying layer. There is no decrease in the resistance value of the resistor.
次に本発明の実施例を図面上用いて説明する。 Next, embodiments of the present invention will be described with reference to the drawings.
第１図は本発明の半導体装置の一実施例の断面図でめる
。FIG. 1 is a cross-sectional view of one embodiment of the semiconductor device of the present invention.
第１因において、シリコン基板１表面には１例えばフィ
ールド酸化膜としての３ｉＱｚ膜２が形成されている。In the first factor, a 3iQz film 2, for example, as a field oxide film, is formed on the surface of the silicon substrate 1.
そして、この８１０ｘ膜２上ＩＣｉ、不純物を高濃度に
含むポリシリコン層からなる抵抗体３が形成されている
。この抵抗体３に含まれる不純物ＨＰ、Ａｓ、Ｂ等の元
素でるり、その抵抗値全規定している。A resistor 3 made of ICi and a polysilicon layer containing a high concentration of impurities is formed on this 810x film 2. Elements such as impurities HP, As, and B contained in this resistor 3 completely determine its resistance value.
この抵抗体３の上面には層間絶縁膜として２例えばＰＩ
Ｇ膜４が、そしてその上面には熱８ｉ３Ｎ４膜８が形成
されている。The upper surface of this resistor 3 has an interlayer insulating film of 2, for example, PI.
A G film 4 is formed, and a thermal 8i3N4 film 8 is formed on its upper surface.
抵抗体３の両端部上の熱８ｉ３Ｎ４膜Ｂ、４ｐｓｏ膜４
にに開孔部５が形成され、この開孔部５ｔとおして抵抗
体３に接続する凝配線６が形成されている。Heat 8i3N4 film B, 4pso film 4 on both ends of resistor 3
An opening 5 is formed in the opening 5t, and a wire 6 connected to the resistor 3 is formed through the opening 5t.
このＬうに溝底された半導体装置においては。In this L-groove semiconductor device.
Ａｔ配線６を含む表面全体にバッジページ曹ン膜又は層
間絶縁膜としてのＰ−８ｉＮ膜７が形成されてもその影
響は抵抗体３に布達することにない。Even if the badge page carbon film or the P-8iN film 7 as an interlayer insulating film is formed on the entire surface including the At wiring 6, its influence does not reach the resistor 3.
すなわち、ＰＥＧ膜４上に形成された熱８ｉ３Ｎ４膜８
は、ＬＯＣＯ８構造に用いられているように、緻密性に
優れているため、Ｐ−８ｉＮ膜を堆積する時の下地絶縁
膜の損傷及び、Ｐ−８ｉＮ腹中の水素等の影響を少なく
し、抵抗体３の抵抗値を低下させることはない。That is, the thermal 8i3N4 film 8 formed on the PEG film 4
As used in the LOCO8 structure, it has excellent density, so it reduces damage to the underlying insulating film and the effects of hydrogen in the P-8iN film when depositing the P-8iN film. The resistance value of the resistor 3 is not reduced.
次に本発明の半導体装置の製造方法について説明する。Next, a method for manufacturing a semiconductor device according to the present invention will be explained.
第２図（ａ）〜（Ｃ）は本発明の半導体装置の製造方法
の一実施例全説明する友めの工程断面図でらる。FIGS. 2(a) to 2(C) are cross-sectional views illustrating an embodiment of the semiconductor device manufacturing method of the present invention.
１ず第２図（ａ）に示すように、フィールド酸化膜とし
ての８ｉ０ｚ膜２の形成され几シリコン基板１の上面に
、ＣＶＤ法によりポリシリコン層３ａ’２約４００ＯＡ
の厚さに堆積させたのち、不純物としてＰｋｌ Ｘ １
０〜Ｉ Ｘ １０ ／ａｎ２ の割合でイオン注入する
。この作業にエリポリシリコン層３ａは約Ｉ Ｘ １０
（Ω・ｃｎ）の抵抗値を有する抵抗体となる。1. As shown in FIG. 2(a), a polysilicon layer 3a'2 of about 400 OA is deposited by CVD on the upper surface of the silicon substrate 1 on which the 8i0z film 2 as a field oxide film is formed.
After depositing Pkl X 1 as an impurity,
Ions are implanted at a ratio of 0 to I x 10 /an2. In this operation, the polysilicon layer 3a is approximately I x 10
It becomes a resistor having a resistance value of (Ω·cn).
次に第２図（ｂ）に示すように、ポリシリコン層３ａ？
バターニングし規定寸法の抵抗体３を形成したのち、そ
の上面に厚さ０．５〜１．０μｍのＰＥＧ膜４全４全Ｃ
ＶＤ法フ形成する。Next, as shown in FIG. 2(b), polysilicon layer 3a?
After patterning and forming a resistor 3 with specified dimensions, a PEG film 4 with a thickness of 0.5 to 1.0 μm is placed on its upper surface.
Form by VD method.
次に第２図（Ｃ）に示すように、ＰＳＧ膜４上に熱８ｉ
３Ｎ４膜８ｒ３０００Ａ以上の厚さに堆積する。この熱
８ｉ３Ｎ４膜８は、８ｉＨ４とＮＨ３と金用い約９００
℃の温度でのＣＶＤ法に工り形成される。続いて抵抗体
３の両端部上の熱８ｉ、Ｎシ膜８及びＰＥＧ膜４に１反
応性イオンエツチング（ＲＩＥ）法により開孔部５を形
成する。Next, as shown in FIG. 2(C), heat 8i is applied on the PSG film 4.
3N4 film 8r is deposited to a thickness of 3000A or more. This thermal 8i3N4 film 8 is made of 8iH4, NH3 and gold with approximately 900%
It is formed by a CVD method at a temperature of .degree. Subsequently, openings 5 are formed in the heat 8i, N film 8 and PEG film 4 on both ends of the resistor 3 by reactive ion etching (RIE).
以下１表面ＶｃＡｊｔ−堆積させｋのち、パターニング
し、抵抗体３に接続するＭ配線６金形成することによ？
）第１図に示す半導体装置が得られる。After depositing VcAjt on one surface, patterning is performed to form a 6-gold M wiring connected to the resistor 3.
) The semiconductor device shown in FIG. 1 is obtained.
第３図はこの工うにして形成した半導体装置の抵抗体の
抵抗値全従来のものと比較してプロットし友ものでるり
、縦軸に抵抗率（Ω・口）七、そして横軸に試料（抵抗
体）の状態？示し友。Figure 3 plots the resistance values of the resistor of the semiconductor device formed in this way compared with the conventional one. Condition of the sample (resistor)? Show friend.
同図に示される工うに、従来は、抵抗体上にＰ８Ｇ膜全
形成した時の抵抗率がＩ×１００・■でめっ７’Ｃもの
が（ａ）、その上にパッシベーション度としてＰ−８ｉ
Ｎ膜が形成されるとその値にＩ Ｘ １０ Ω・■とな
り、更にこれを４００〜５００℃１０分間熱処理すると
、抵抗率は約１０・口に１で低下した。As shown in the figure, conventionally, when a P8G film is entirely formed on a resistor, the resistivity is I × 100 . 8i
When the N film was formed, its value was I x 10 Ω·■, and when this was further heat-treated at 400 to 500°C for 10 minutes, the resistivity decreased to about 1 in 10.
しかるＫｌ上記実施例の工５ｉＣ，ＰＳＧ膜上に熱Ｓｉ
３Ｎ４膜勿形底し次場合も（ｂ２） 、又これｔ熱処理
し次場合も（Ｃ２ハ共に抵抗率の値にほとんど変化しな
かった。従って本発明の半導体装置の抵抗体は、第２図
（ａ）に示した工程において注入される不純物のｆＩＣ
エリその抵抗値が定フるため、ばらつきの少ない、信頼
性の高いものとなる。However, in the process 5iC of the above example, thermal Si was applied on the PSG film.
There was almost no change in the resistivity value in both cases (b2) when the 3N4 film was formed without forming the bottom, and also when it was heat-treated (C2).Therefore, the resistivity of the semiconductor device of the present invention is fIC of impurities implanted in the step shown in (a)
Since the resistance value of the resistor is constant, it has little variation and is highly reliable.
以上詳細に説明したように９本発明によれば。 As described in detail above, according to the present invention.
層間絶縁膜上に熱ＣＶＤ法によるＳｉａＮ４ｆｆｇ’に
形成することにエク、パッジページ冒ン膜及び層間絶縁
膜としてプラズマＣＶＤ法によるＰ−８ｉＮ膜全形成し
ても、抵抗値の低下しない信頼性の高い抵抗体ｔＶする
半導体及びその製造方法が得られるのでその効果は大き
い。It is difficult to form SiaN4ffg' on the interlayer insulating film by thermal CVD, and even if the entire P-8iN film is formed by plasma CVD as a Padgepage film and interlayer insulating film, the resistance value does not decrease. The effect is great because a semiconductor with a high resistor tV and a method for manufacturing the same can be obtained.
第４図は本発明の半導体装置の一実施例の断面図、第２
図（ａ）〜（Ｃ）は本発明の半導体装置の製造方法の一
実施例全説明するための工程断面図、第３図は本発明の
半導体装置の抵抗体の抵抗値全従来のものと比較してプ
ロットし九図、第４図は従来の半導体装置の一例の断面
図でおる。
１・・・シリコン基板、２・・・５ｉＯｚ膜、３・・・
抵抗体。
４・・・Ｐｂ０膜、５・・・開孔部、６・・・Ａｔ配線
、７・・・Ｐ−８ｉＮ膜、８・・・熱Ｓｉ３Ｎ４膜。
第１圀FIG. 4 is a sectional view of one embodiment of the semiconductor device of the present invention;
Figures (a) to (C) are process cross-sectional views for fully explaining one embodiment of the method for manufacturing a semiconductor device of the present invention, and Figure 3 shows all resistance values of the resistor of the semiconductor device of the present invention compared to conventional ones. For comparison, Figure 9 and Figure 4 are cross-sectional views of an example of a conventional semiconductor device. 1... Silicon substrate, 2... 5iOz film, 3...
resistor. 4... Pb0 film, 5... Opening portion, 6... At wiring, 7... P-8iN film, 8... Thermal Si3N4 film. 1st area
Claims (2)
リコン層からなる抵抗体と、該抵抗体上に形成された絶
縁膜と、該絶縁膜上に形成された熱ＣＶＤ法によるシリ
コン窒化膜とを含むことを特徴とする半導体装置。(1) A resistor made of a polysilicon layer formed on an oxide film on the surface of a silicon substrate, an insulating film formed on the resistor, and a silicon nitride film formed by thermal CVD on the insulating film. A semiconductor device comprising:
形成する工程と、該ポリシリコン層に不純物イオンを注
入し所定の抵抗値を有する抵抗体層を形成する工程と、
該抵抗体層をパターニングし所定形状の抵抗体を形成す
る工程と、該抵抗体上に絶縁膜を形成する工程と、該絶
縁膜上に熱ＣＶＤ法にとりシリコン窒化膜を形成する工
程とを含むことを特徴とする半導体装置の製造方法。(2) a step of forming a polysilicon layer on the oxide film on the surface of the silicon substrate; a step of implanting impurity ions into the polysilicon layer to form a resistor layer having a predetermined resistance value;
The method includes the steps of patterning the resistor layer to form a resistor in a predetermined shape, forming an insulating film on the resistor, and forming a silicon nitride film on the insulating film by thermal CVD. A method for manufacturing a semiconductor device, characterized in that:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59217723A JPS6196755A (en) | 1984-10-17 | 1984-10-17 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59217723A JPS6196755A (en) | 1984-10-17 | 1984-10-17 | Semiconductor device and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6196755A true JPS6196755A (en) | 1986-05-15 |
Family
ID=16708726
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59217723A Pending JPS6196755A (en) | 1984-10-17 | 1984-10-17 | Semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6196755A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0463174A1 (en) * | 1989-12-26 | 1992-01-02 | Sony Corporation | Method of manufacturing semiconductor device |
| US11495452B2 (en) | 2019-03-06 | 2022-11-08 | Tohku University | Method for producing silicon nitride film |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5240082A (en) * | 1975-09-25 | 1977-03-28 | Nec Corp | Resistor element and process for production of same |
| JPS59159544A (en) * | 1983-03-03 | 1984-09-10 | Nec Corp | Semiconductor device and manufacture thereof |
-
1984
- 1984-10-17 JP JP59217723A patent/JPS6196755A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5240082A (en) * | 1975-09-25 | 1977-03-28 | Nec Corp | Resistor element and process for production of same |
| JPS59159544A (en) * | 1983-03-03 | 1984-09-10 | Nec Corp | Semiconductor device and manufacture thereof |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0463174A1 (en) * | 1989-12-26 | 1992-01-02 | Sony Corporation | Method of manufacturing semiconductor device |
| US11495452B2 (en) | 2019-03-06 | 2022-11-08 | Tohku University | Method for producing silicon nitride film |
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