JP3225879B2 - Silicon oxide film forming method and multilayer wiring forming method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a silicon oxide film using a hydrogen silsesquioxane resin, and more particularly to a method for converting a preceramic silicon oxide film into a ceramic silicon oxide film. The content of silicon-bonded hydrogen atoms (hereinafter abbreviated as "Si-H") in the hydrogen silsesquioxane resin is 30% less than the content of Si-H in the ceramic silicon oxide film.
%, It is possible to form a silicon oxide film which is hard to be peeled off by performing oxidation until it becomes not more than%.

[0002]

2. Description of the Related Art Conventionally, as a method for forming a silicon oxide film using a hydrogen silsesquioxane resin, a hydrogen silsesquioxane resin film is formed flat on a substrate,
The resin film is heat-treated in an inert gas atmosphere to form a preceramic silicon oxide film, and the silicon oxide film is further subjected to an oxygen (O ₂ ) gas (or a mixed gas of O ₂ gas and an inert gas) atmosphere. To form a ceramic silicon oxide film, and in the heat treatment for ceramicization, the Si—H content in the ceramic silicon oxide film becomes 80% or less of the Si—H content in the resin film. Heat treatment is known up to, for example, Japanese Patent Application Laid-Open No. 6-181.
No. 204). The silicon oxide film thus formed is used, for example, as an interlayer film of a semiconductor device such as an IC (integrated circuit) or an insulating film such as a protective film.

[0003]

According to the study by the inventor, it has been found that the above-mentioned prior art has a problem that the adhesive strength of the ceramic silicon oxide film is weak and the film is easily peeled off.

An object of the present invention is to provide a novel silicon oxide film forming method capable of forming a silicon oxide film which is difficult to peel off.

[0005]

According to the present invention, there is provided a method for forming a silicon oxide film, comprising: forming a hydrogen silsesquioxane resin film on an insulating film covering a substrate in a flat shape; A step of heat-treating the hydrogen silsesquioxane resin film to form a preceramic silicon oxide film, and setting the heat treatment atmosphere to an oxidizing atmosphere containing nitrogen gas.
After the silicon oxide by heat-treating the silicon oxide film is changed to an oxidizing atmosphere containing no nitrogen gas
A step of forming the film into a ceramic silicon oxide film, wherein the content of silicon atom-bonded hydrogen atoms in the hydrogen silsesquioxane resin film is changed with respect to the content of silicon atom-bonded hydrogen atoms in the ceramic silicon oxide film. Heat treatment is performed until the content of is reduced to 30% or less.

[0006] In the method of this invention, the heat treatment in an oxidizing atmosphere, for example, (i) O ₂ gas or O ₂ gas and heated in a mixed gas of an inert gas, (ii) O ₂ Heating in plasma (in the presence of O ₂ ions or O ₂ radicals), (c) light irradiation or heating in an ozone (O ₃ ) atmosphere, or (d) heating in an atmosphere containing water vapor It may be.

According to the method of the present invention, the content of Si—H in the ceramic silicon oxide film is reduced by 30 with respect to the content of Si—H in the hydrogen silsesquioxane resin film in the heat treatment for ceramic formation. % Oxidation. The inventors' research has shown that a silicon oxide film that is difficult to peel off can be obtained in this manner.
Details will be described later.

[0008]

1 to 9 show a method of forming a multilayer wiring according to an embodiment of the present invention. Steps (1) to (9) corresponding to the respective drawings will be sequentially described.

(1) A field insulating film 12 is formed on the surface of a semiconductor substrate 10 such as silicon by a known selective oxidation method. The insulating film 12 is made of, for example, a silicon oxide film having a thickness of 400 nm and has a large number of element holes (not shown).
Having. After a circuit element (not shown) such as a MOS transistor is formed in each element hole of the insulating film 12, the insulating film 12
Then, an insulating film 14 is formed to cover each circuit element. As the insulating film 14, a 750-nm-thick BPSG (boron-phosphorus-silicate glass) film is formed by a normal pressure CVD (chemical vapor deposition) method. The film forming conditions at this time were: substrate temperature: 400 ° C. source gas: SiH ₄ (46.25 sccm) + PH ₃
(8.75 sccm) + B ₂ H ₆ (7.5 sccm) +
O ₂ (7000 sccm) + N ₂ (50,000 scc
m). Further, the BPSG film is subjected to lamp annealing for the purpose of densification. The processing conditions at this time can be set as follows: substrate temperature: 850 ° C. Heating time up to 850 ° C .: 10 seconds Maintaining time at 850 ° C .: 10 seconds

(2) After forming a connection hole (not shown) for the above-mentioned circuit element in the insulating film 14 by well-known photolithography and selective dry etching, a wiring material is applied on the upper surface of the substrate. The wiring layer 16 is formed by patterning the deposition layer by photolithography and selective dry etching. The wiring layer 16 is connected to a predetermined circuit element via a predetermined connection hole. As wiring materials, Ti (20 nm) and TiON (100 n
m), Al alloy (for example, Al-Si-Cu alloy: 400)
nm), Ti (10 nm) and TiN (40 nm) can be deposited by sputtering. The dry etching conditions are as follows: etching gas: Cl ₂ (30 sccm) + BCl ₃
(30 sccm) The pressure in the etching chamber can be set to 10 mTorr.

(3) An insulating film 18 is formed on the insulating film 14 so as to cover the wiring layer 16. The insulating film 18 has a thickness of 1
A 50 nm silicon oxide film is formed by a plasma CVD method. The film forming conditions at this time were as follows: substrate temperature: 400 ° C. source gas: SiH ₄ (240 sccm) + N ₂ O (50
00 sccm) + N ₂ (2800 sccm) Reaction chamber pressure: 2.2 Torr.

(4) A silicon oxide film 20 is formed on the upper surface of the substrate so as to cover the wiring layer 16 with the insulating film 18 interposed therebetween. As an example, hydrogen silsesquioxane resin is
A solution dissolved in BK (methyl isobutyl ketone) is applied to the upper surface of the substrate using a spin coater to a thickness of 500 nm, and the applied resin film is heat-treated in an inert gas atmosphere to form a preceramic. A silicon oxide film is formed, and the silicon oxide film is heat-treated in an oxidizing atmosphere to form a ceramic silicon oxide film 20. Here, the heat treatment condition for preceramic formation is nitrogen (N
₂ ) 150 ° C for 1 minute + 200 ° C for 1 minute + 300 in a gas atmosphere
° C for 1 minute. Further, the heat treatment condition for ceramicization can be 30 minutes in an atmosphere containing O ₂ gas and N ₂ gas + 30 minutes in an atmosphere containing O ₂ gas. How to set the heat treatment conditions for ceramicization will be described later.

(5) The insulating film 2 is formed on the upper surface of the substrate so as to cover the wiring layer 16 with the insulating film 18 and the silicon oxide film 20 interposed therebetween.
Form 2 As the insulating film 22, TEOS (Tetra
Ethyl Ortho Silicate [Si (OC ₂ H ₅ ) ₄ ]) and O ₂ as raw materials by plasma CVD to a thickness of 300 n.
m silicon oxide film is formed. The film forming conditions at this time can be set as follows: substrate temperature: 400 ° C. source gas: TEOS (1.8 cc / min [supplied as liquid]) + O ₂ (8000 sccm) reaction chamber pressure: 2.2 Torr. Insulating film 18, silicon oxide film 20
The stack of the insulating films 22 is used as an interlayer insulating film 24.

(6) After forming a resist layer 26 having holes corresponding to desired connection holes on the interlayer insulating film 24 by photolithography, a wiring layer is formed by selective dry etching using the resist layer 26 as a mask. A connection hole 28 reaching 16 is formed in the interlayer insulating film 24. After that, the resist layer 26 is removed by a known method such as ashing.

(7) A wiring material is applied on the interlayer insulating film 24 so as to cover the connection hole 28, and the deposited layer is patterned by selective dry etching to form the connection hole 2
Then, a wiring layer 30 connected to the wiring layer 16 via 8 is formed. As the wiring material, Ti (20 nm), A
1 alloy (for example, Al-Si-Cu alloy: 1000 nm)
And TiN (40 nm) can be applied by a sputtering method. The dry etching conditions are as follows: etching gas: Cl ₂ (30 sccm) + BCl ₃
(30 sccm) The pressure in the etching chamber can be set to 10 mTorr.

Thereafter, in order to reduce process damage, the wiring structure shown in FIG. 7 is subjected to hydrogen annealing. The annealing condition at this time is, for example, N ₂ + H ₂ (20
%) 400 ° C. for 30 minutes in a gas atmosphere.

(8) An insulating film 32 is formed on the interlayer insulating film 24 so as to cover the wiring layer 30. As the insulating film 32, a 150-nm-thick silicon oxide film is formed by a plasma CVD method. The film forming conditions at this time were as follows: substrate temperature: 400 ° C. source gas: SiH ₄ (240 sccm) + N ₂ O (50
00 sccm) + N ₂ (2800 sccm) Reaction chamber pressure: 2.2 Torr.

(9) An insulating film 34 is formed on the upper surface of the substrate so as to cover the wiring layer 30 with the insulating film 32 interposed therebetween. Insulating film 34
A silicon nitride film having a thickness of 1000 nm is formed by a plasma CVD method. The film forming conditions at this time were as follows: substrate temperature: 400 ° C. source gas: SiH ₄ (300 sccm) + NH ₃ (18
00 sccm) + N ₂ (1000 sccm) Reaction chamber pressure: 2.6 Torr. The lamination of the insulating films 32 and 34 is used as the protective film 36.

Thereafter, the substrate 10 is divided into individual IC chips by scribing for each IC unit. Then, each IC chip is assembled as shown in FIGS. 10 and 11 by a well-known method, sealed with a resin, and QFP (Quad Flat Packa).
ge) Type IC device.

In the IC device shown in FIGS.
An IC chip 40 is fixed to one main surface of the support member 42. Each lead electrode (bonding pad) on the IC chip 40 is connected to an inner lead portion of a corresponding lead 46 by a corresponding bonding wire 44. The IC chip 40, the support member 42, the bonding wires 44, and the inner lead portions of the leads 46 are formed such that the outer lead portions of the leads 46 are led out of the resin body 48 as shown in FIG. Is molded. The outer lead portion of each lead 46
As shown in FIG. 10, it is bent to the back side of the resin body 48.

In order to confirm the effect of the present invention, FIGS.
5 types of QFP by the same method as described above for 1
A type IC device was manufactured as an evaluation sample. These samples were manufactured in the same manner except that the heat treatment conditions for ceramicization were changed as shown in Table 1 below when forming the silicon oxide film 20 in the step of FIG. .

[0022]

[Table 1] The heat treatment for ceramicization was performed in any of the samples 1 to 5 in a vertical heat treatment furnace. In this heat treatment, the temperature is increased, the treatment time is extended, or N
₍₂₎ Reducing the flow rate promotes ceramification.

In each sample, the size of the IC chip 40 is 12 mm × 12 mm, and the number of leads 46 is 1
28 (128 pins). The material of the resin body 48 is epoxy resin (thermal expansion coefficient α = 2.0 × 10 ^−5).
° C. ^-1, a Young's modulus E = 1400kg / mm ²⁾ was used.

Samples 1 to 5 were subjected to a temperature cycle test. In this temperature cycle test, 500 cycles of temperature fluctuation were given to the samples 1 to 5 with the temperature cycle shown in the following equation 1 as one cycle.

[0025]

(Equation 1) As a result of the temperature cycle test, peeling of the interlayer insulating film was observed in the vicinity of the chip corner (X in FIG. 11) where the shear stress was concentrated in Samples 1 and 2, but in Samples 3 to 5, the peeling of the interlayer insulating film was observed. No peeling was observed. As shown in FIG. 9, the peeling of the interlayer insulating film was observed by SEM (scanning electron microscope).
It has been found that this occurs at the interface Y with the interface.

A predetermined number of 2 for each IC chip of each sample
The presence or absence of peeling of the interlayer insulating film was examined at five observation points, and the number of observation points with peeling was taken as Q, and the peeling rate was Q / 2.
Table 2 below shows the results obtained for No. 5.

[0027]

[Table 2] Table 2 shows that the residual Si-H content K ′ /
K or _I'SiH / _ISiH . FIG. 12 shows how the peeling rate depends on K ′ / K, and marks S _{1 to} S ₅ correspond to samples 1 to 5, respectively.

The residual Si-H content K '/ K is determined as follows. That is, the peak (1100 cm) due to SiOSi in the hydrogen silsesquioxane resin film formed on the upper surface of the substrate was measured by an infrared spectrophotometer.
^-1 vicinity) obtains the intensity _{I SiH} peak (2250 cm around ^-1) by the intensity _{I SiOSi} and SiH, and obtains both of the ratio _K = _{I SiH / I SiOSi.} Next, a peak (1100 cm) due to SiO 2 Si in the ceramic silicon oxide film (20 in FIG. 4) formed on the upper surface of the substrate is formed.
Seeking a _SiH 'intensity I of a peak (2250 cm around ^-1) by _SiOSi and SiH' intensity I ^-1 vicinity)
The ratio K '= _I'SiH / _{I'SiOSi of both} is determined.
Then, the ratio K '/ K of the two ratios obtained above is obtained. Note that the ratio I ′ _SiH / I _SiH is represented by the absolute amount of Si—H.
The i-H content residual ratio is defined.

According to Table 2 and FIG.
When the residual ratio K ′ / K is set to 30% or less (50% or less for I ′ _SiH / I _SiH ), it can be seen that peeling of the interlayer insulating film in the temperature cycle test can be prevented. That is, the preceramic silicon oxide film is heat-treated in an oxidizing atmosphere to form a ceramic silicon oxide film 20 in FIG.
K ′ / K is. By performing the heat treatment until the temperature becomes 30% or less, it is possible to realize the silicon oxide film 20 that does not easily peel off to the extent that it can withstand the above-described temperature cycle test.

[0030]

As described above, according to the present invention, in the heat treatment for ceramic formation, the Si-H content in the ceramic silicon oxide film is controlled with respect to the Si-H content in the hydrogen silsesquioxane resin. Since the oxidation is performed until the content becomes 30% or less, an effect is obtained in which a silicon oxide film having strong adhesive strength and hard to peel off can be formed.

When the present invention is applied to the formation of an interlayer insulating film when forming a multilayer wiring, an interlayer insulating film that is difficult to peel can be formed, and the effect of realizing a highly reliable multilayer wiring can be obtained.

[Brief description of the drawings]

FIG. 1 is a sectional view of a substrate showing an insulating film forming step in a multilayer wiring forming method according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view of a substrate showing a wiring forming step following the step of FIG. 1;

FIG. 3 is a cross-sectional view of a substrate showing an insulating film forming step following the step of FIG. 2;

FIG. 4 is a cross-sectional view of the substrate showing a silicon oxide film forming step following the step of FIG. 3;

FIG. 5 is a cross-sectional view of the substrate showing an insulating film forming step following the step of FIG. 4;

FIG. 6 is a cross-sectional view of the substrate showing a connection hole forming step following the step of FIG. 5;

FIG. 7 is a cross-sectional view of a substrate showing a wiring forming step following the step of FIG. 6;

FIG. 8 is a cross-sectional view of a substrate showing an insulating film forming step following the step of FIG. 7;

FIG. 9 is a cross-sectional view of the substrate showing an insulating film forming step following the step of FIG. 8;

FIG. 10 illustrates a method of dividing the substrate of FIG.
It is sectional drawing which shows the state which sealed the C chip with resin.

11 is a plan view showing a package corner and a chip corner of the IC device of FIG. 10;

FIG. 12 shows that the peeling rate of the interlayer insulating film in the temperature cycle test indicates the residual Si—H content in the ceramic heat treatment.
It is a graph which shows a mode depending on existence ratio K '/ K.

[Explanation of symbols]

10: semiconductor substrate, 12: field insulating film, 14, 1
8, 22, 32, 34: insulating film, 16, 30: wiring layer,
20: silicon oxide film, 24: interlayer insulating film, 26: resist layer, 28: connection hole, 36: protective film.

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/312-21/316

Claims (2)

(57) [Claims] A step of forming a hydrogen silsesquioxane resin film flat on an insulating film covering a substrate; and a step of heat-treating the hydrogen silsesquioxane resin film in an inert gas atmosphere to form a preceramic. After the step of forming a silicon oxide film and setting the heat treatment atmosphere to an oxidizing atmosphere containing nitrogen gas,
A step of converting the silicon oxide film into a ceramic silicon oxide film by heat-treating the silicon oxide film in an oxidizing atmosphere containing no nitrogen gas , wherein the hydrogen silsesquioxane resin The content of silicon-bonded hydrogen atoms in the ceramic silicon oxide film is 30% of the content of silicon-bonded hydrogen atoms in the film.
A method of forming a silicon oxide film including performing a heat treatment until the temperature becomes below. 2. A step of forming a first wiring layer on a first insulating film covering a substrate, and forming a second insulating film covering the first insulating film and the first wiring layer. Forming a hydrogen silsesquioxane resin film so as to cover the first wiring layer via the second insulating film, and forming the hydrogen silsesquioxane resin film in an inert gas atmosphere. Heat treating the sun resin film to form a first ceramic oxide first silicon oxide film, and setting the heat treatment atmosphere to an oxidizing atmosphere containing nitrogen gas,
Change in an oxidizing atmosphere containing no nitrogen gas the first oxide by heat treating the first silicon oxide film
A step of converting the silicon film into a ceramic-like second silicon oxide film, wherein the second content of the silicon-bonded hydrogen atoms in the hydrogen silsesquioxane resin film is reduced.
Performing a heat treatment until the content of silicon-bonded hydrogen atoms in the silicon oxide film becomes 30% or less; and forming the first wiring layer via the second insulating film and the second silicon oxide film. Forming a third insulating film so as to cover the first insulating film; and forming a second wiring layer on the interlayer insulating film including the second insulating film, the second silicon oxide film, and the third insulating film. Forming a multilayer wiring.