JP3498619B2 - Semiconductor device and its manufacturing method. - Google Patents
Semiconductor device and its manufacturing method.Info
- Publication number
- JP3498619B2 JP3498619B2 JP03407599A JP3407599A JP3498619B2 JP 3498619 B2 JP3498619 B2 JP 3498619B2 JP 03407599 A JP03407599 A JP 03407599A JP 3407599 A JP3407599 A JP 3407599A JP 3498619 B2 JP3498619 B2 JP 3498619B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- silicon oxide
- oxide film
- silicon nitride
- nitride film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
Description
【発明の詳細な説明】Detailed Description of the Invention
【０００１】[0001]
【発明の属する技術分野】この発明は、ＬＳＩ等の半導
体装置とその製法に関し、特に表面保護膜（パッシベー
ション膜）としての窒化シリコン膜の下に水素シルセス
キオキサン樹脂膜をセラミック化した酸化シリコン膜を
形成した半導体装置において、酸化シリコン膜と窒化シ
リコン膜との間に密着性酸化シリコン膜を介在配置した
ことにより窒化シリコン膜のはがれ耐性を向上させたも
のである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device such as an LSI and a method of manufacturing the same, and more particularly to a silicon oxide film in which a hydrogen silsesquioxane resin film is ceramicized under a silicon nitride film as a surface protection film (passivation film). In the film-formed semiconductor device, the peeling resistance of the silicon nitride film is improved by disposing the adhesive silicon oxide film between the silicon oxide film and the silicon nitride film.
【０００２】[0002]
【従来の技術】従来、表面保護膜として窒化シリコン膜
を有する半導体装置としては、窒化シリコン膜の下地膜
として塗布絶縁膜を用いることにより平坦化を図ったも
のが知られている（例えば、特開昭６３−２４４６２８
号公報、特開平３−２０３３２８号公報、特開平９−２
０５１４２号公報等参照）。2. Description of the Related Art Conventionally, as a semiconductor device having a silicon nitride film as a surface protection film, there has been known a device which is planarized by using a coating insulating film as a base film of a silicon nitride film (for example, a special feature) Kaisho 63-244628
Japanese Patent Application Laid-Open No. 3-203328, Japanese Patent Application Laid-Open No. 9-2
No. 05142, etc.).
【０００３】また、窒化シリコン膜の下地膜としてポリ
イミド膜等の低誘電率材料膜を用いることにより配線間
容量を低減することも知られている（例えば、特開昭６
３−２４４６２８号公報参照）。It is also known to reduce the capacitance between wirings by using a low dielectric constant material film such as a polyimide film as a base film of a silicon nitride film (see, for example, Japanese Patent Laid-Open No. Sho 6-66).
3-244628).
【０００４】[0004]
【発明が解決しようとする課題】先に引用した特開平９
−２０５１４２号公報に示される半導体装置にあって
は、窒化シリコン膜の下地膜として水素シルセスキオキ
サン樹脂膜をセラミック化した酸化シリコン膜を用いて
いる。水素シルセスキオキサン樹脂膜は、回転塗布法に
より塗布された後、熱処理によりセラミック状の酸化シ
リコン膜に変換される。従って、窒化シリコン膜は、平
坦性良好な酸化シリコン膜の上に形成されるので、被覆
性が向上し、耐湿性が改善される。また、水素シルセス
キオキサン樹脂膜をセラミック化した酸化シリコン膜の
誘電率は、３前後であり、プラズマＣＶＤ（化学気相堆
積）法で形成した窒化シリコン膜の誘電率（約７．５）
に比べて小さいので、配線間容量が低減され、回路の高
速化及び動作マージンの拡大が可能となる。DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
In the semiconductor device disclosed in Japanese Patent Laid-Open No. 205142, a silicon oxide film obtained by ceramicizing a hydrogen silsesquioxane resin film is used as a base film of a silicon nitride film. The hydrogen silsesquioxane resin film is applied by a spin application method and then converted into a ceramic silicon oxide film by heat treatment. Therefore, since the silicon nitride film is formed on the silicon oxide film having good flatness, the coverage is improved and the moisture resistance is improved. Further, the dielectric constant of the silicon oxide film obtained by ceramicizing the hydrogen silsesquioxane resin film is about 3, and the dielectric constant of the silicon nitride film formed by the plasma CVD (chemical vapor deposition) method (about 7.5).
Since it is smaller than that of (1), the inter-wiring capacitance is reduced, and it is possible to speed up the circuit and expand the operation margin.
【０００５】しかしながら、このような半導体装置を温
度サイクル試験にかけたところ、窒化シリコン膜につい
て実用上十分なはがれ耐性が得られないことが判明し
た。すなわち、窒化シリコン膜と下地膜としての酸化シ
リコン膜との密着性が十分でなく、窒化シリコン膜のは
がれにより信頼性の低下を招くおそれがあることがわか
った。However, when such a semiconductor device was subjected to a temperature cycle test, it was found that a practically sufficient peeling resistance cannot be obtained for a silicon nitride film. That is, it has been found that the adhesion between the silicon nitride film and the silicon oxide film as the base film is not sufficient, and peeling of the silicon nitride film may lead to a decrease in reliability.
【０００６】この発明の目的は、表面保護膜としての窒
化シリコン膜の下に水素シルセスキオキサン樹脂膜をセ
ラミック化した酸化シリコン膜を形成した半導体装置に
おいて、窒化シリコン膜のはがれ耐性を向上させること
にある。An object of the present invention is to improve the peeling resistance of a silicon nitride film in a semiconductor device in which a silicon oxide film formed by ceramicizing a hydrogen silsesquioxane resin film is formed under a silicon nitride film as a surface protection film. Especially.
【０００７】[0007]
【課題を解決するための手段】この発明に係る半導体装
置は、半導体基板を覆う絶縁膜の上に複数の配線層を形
成すると共に該複数の配線層を覆って水素シルセスキオ
キサン樹脂膜をセラミック化した酸化シリコン膜を形成
し、該酸化シリコン膜を覆って表面保護膜としての窒化
シリコン膜を形成した半導体装置において、前記酸化シ
リコン膜及び前記窒化シリコン膜のいずれに対しても密
着性を有する密着性酸化シリコン膜を前記酸化シリコン
膜と前記窒化シリコン膜との間に介在配置したことを特
徴とするものである。A semiconductor device according to the present invention has a plurality of wiring layers formed on an insulating film covering a semiconductor substrate and a hydrogen silsesquioxane resin film covering the plurality of wiring layers. In a semiconductor device in which a ceramicized silicon oxide film is formed and a silicon nitride film as a surface protection film is formed so as to cover the silicon oxide film, adhesion to both the silicon oxide film and the silicon nitride film is provided. The adhesive silicon oxide film has an interposition between the silicon oxide film and the silicon nitride film.
【０００８】この発明の構成によれば、酸化シリコン膜
及び窒化シリコン膜のいずれに対しても密着性を有する
密着性酸化シリコン膜を酸化シリコン膜と窒化シリコン
膜との間に介在配置したので、酸化シリコン膜と密着性
酸化シリコン膜との密着性が良好になると共に密着性酸
化シリコン膜と窒化シリコン膜との密着性が良好とな
り、窒化シリコン膜のはがれ耐性が向上する。According to the structure of the present invention, since the adhesive silicon oxide film having adhesiveness to both the silicon oxide film and the silicon nitride film is disposed between the silicon oxide film and the silicon nitride film, Adhesion between the silicon oxide film and the adhesive silicon oxide film is improved, adhesion between the adhesive silicon oxide film and the silicon nitride film is improved, and peeling resistance of the silicon nitride film is improved.
【０００９】この発明において、密着性酸化シリコン膜
及び窒化シリコン膜は、いずれもプラズマＣＶＤ法によ
り形成するのが好ましい。プラズマＣＶＤ法により形成
した酸化シリコン膜は、水素シルセスキオキサン樹脂膜
をセラミック化した酸化シリコン膜と、プラズマＣＶＤ
法により形成した窒化シリコン膜とのいずれに対しても
実用上十分な密着性を有することが確認されている。In the present invention, both the adhesive silicon oxide film and the silicon nitride film are preferably formed by the plasma CVD method. The silicon oxide film formed by the plasma CVD method includes a silicon oxide film formed by converting a hydrogen silsesquioxane resin film into a ceramic film and a plasma CVD film.
It has been confirmed that it has practically sufficient adhesion to any of the silicon nitride films formed by the method.
【００１０】[0010]
【発明の実施の形態】図１〜６は、この発明の一実施形
態に係る半導体装置の製法を示すもので、各々の図に対
応する工程（１）〜（６）を順次に説明する。1 to 6 show a method of manufacturing a semiconductor device according to an embodiment of the present invention, and steps (1) to (6) corresponding to the respective drawings will be sequentially described.
【００１１】（１）図１は、半導体基板１０の表面に形
成される複数のチップ領域のうちの１つのチップ領域Ｃ
Ｐにおいてスクライブ領域ＳＢの近傍の配線形成状態を
示すものであり、Ｌは、領域ＣＰ，ＳＢ間の境界を示
す。チップ領域ＣＰの表面には、基板１０を構成するシ
リコンを選択酸化するなどしてフィールド絶縁膜１２を
形成する。絶縁膜１２の素子孔（図示せず）には、トラ
ンジスタ等の回路素子を周知の方法により形成する。(1) FIG. 1 shows one chip area C of a plurality of chip areas formed on the surface of the semiconductor substrate 10.
In P, the wiring formation state near the scribe region SB is shown, and L shows the boundary between the regions CP and SB. On the surface of the chip region CP, the field insulating film 12 is formed by selectively oxidizing the silicon forming the substrate 10. A circuit element such as a transistor is formed in an element hole (not shown) of the insulating film 12 by a known method.
【００１２】絶縁膜１２の上には、ポリサイド（ポリシ
リコン上にシリサイドを積層したもの）等の１層目の配
線層を形成する。１４は、これらの配線層のうちの１つ
の配線層である。On the insulating film 12, a first wiring layer such as polycide (polysilicon layered with silicide) is formed. Reference numeral 14 is one of these wiring layers.
【００１３】絶縁膜１２の上には、図示しないトランジ
スタ等の回路素子及び１４等の１層目配線層を覆ってＢ
ＰＳＧ（ボロン・リン・ケイ酸ガラス）等の層間絶縁膜
１６を形成する。絶縁膜１６には、１４等の１層目配線
層との接続を可能にする接続孔と、スクライブ領域ＳＢ
を露呈するスクライブ孔とを周知のホトリソグラフィ及
び選択エッチング処理により形成する。On the insulating film 12, a circuit element such as a transistor (not shown) and a first wiring layer such as 14 are covered to form B.
An interlayer insulating film 16 such as PSG (boron / phosphorus / silicate glass) is formed. The insulating film 16 has a connection hole that enables connection with a first wiring layer such as 14 and a scribe region SB.
And a scribe hole exposing the film are formed by well-known photolithography and selective etching processing.
【００１４】基板上面にＡｌ合金等の配線材を被着して
その被着層をホトリソグラフィ及び選択エッチング処理
によりパターニングすることにより絶縁膜１６の上に１
８，２０ａ〜２０ｃ，２２Ａ等の２層目配線層と、２２
等の端子電極層（ボンディングパッド）とを形成する。
１４等の１層目配線層及び１８，２０ａ〜２０ｃ等の２
層目配線層により前述したトランジスタ等の回路素子を
相互接続することによりチップ領域ＣＰ内の集積回路が
構成される。端子電極層２２は、配線層２２Ａ，１４，
１８を介してチップ領域ＣＰ内の回路に接続される。配
線層２０ａ〜２０ｃは、配線層１４の上方を配線層１４
に交差して延長する配線層である。A wiring material such as an Al alloy is deposited on the upper surface of the substrate, and the deposited layer is patterned by photolithography and selective etching to form one layer on the insulating film 16.
A second wiring layer such as 8, 20a to 20c, 22A;
And terminal electrode layers (bonding pads).
1st wiring layer such as 14 and 2 such as 18, 20a to 20c
An integrated circuit in the chip region CP is configured by interconnecting the circuit elements such as the transistors described above by the second wiring layer. The terminal electrode layer 22 includes wiring layers 22A, 14,
It is connected to the circuit in the chip area CP via 18. The wiring layers 20a to 20c are arranged above the wiring layer 14 by the wiring layer 14
Is a wiring layer that intersects and extends.
【００１５】（２）絶縁膜１６の上に１８，２０ａ〜２
０ｃ，２２Ａ等の２層目の配線層及び２２等の端子電極
層を覆って水素シルセスキオキサン樹脂膜をセラミック
状にした酸化シリコン膜３２を形成する。このために
は、まず、水素シルセスキオキサン樹脂膜をＭＩＢＫ
（メチル・イソブチル・ケトン）で溶解した溶液を回転
塗布法により基板上面に塗布して平坦状に樹脂膜を形成
する。そして、樹脂膜に不活性ガス雰囲気中で熱処理を
施すことにより樹脂膜をプレセラミック状の酸化シリコ
ン膜にする。プレセラミック状の酸化シリコンは、セラ
ミック状の酸化シリコンの前駆体であり、セラミック状
の酸化シリコンよりも架橋が進行しておらず、しかも有
機溶剤に対して不溶なものである。この後、プレセラミ
ック状の酸化シリコン膜に酸化性雰囲気（例えばＯ２ガ
スを含むか又はＯ２ガス及び不活性ガスを含むもの）中
で熱処理を施すことによりプレセラミック状の酸化シリ
コン膜をセラミック状の酸化シリコン膜３２にする。こ
のような方法によれば、１μｍ程度の厚い酸化シリコン
膜をクラックなしに形成できる。酸化シリコン膜３２と
しては、３００〜６００ｎｍ（例えば５００ｎｍ）の厚
さのものを形成すればよい。(2) 18, 20a-2 on the insulating film 16
0c, 22A and other second wiring layers and 22 and other terminal electrode layers are covered to form a ceramic silicon oxide film 32 of hydrogen silsesquioxane resin film. For this purpose, first, the hydrogen silsesquioxane resin film is set to MIBK.
A solution dissolved in (methyl isobutyl ketone) is applied to the upper surface of the substrate by a spin coating method to form a flat resin film. Then, the resin film is heat-treated in an inert gas atmosphere to form the resin film into a preceramic silicon oxide film. The preceramic silicon oxide is a precursor of the ceramic silicon oxide, is less cross-linked than the ceramic silicon oxide, and is insoluble in organic solvents. Thereafter, ceramics preceramic silicon oxide film by heat treatment in an oxidizing atmosphere (e.g., O 2 as including or O 2 gas and an inert gas containing a gas) into preceramic silicon oxide film Form a silicon oxide film 32. According to such a method, a thick silicon oxide film of about 1 μm can be formed without cracks. As the silicon oxide film 32, a film having a thickness of 300 to 600 nm (for example, 500 nm) may be formed.
【００１６】（３）酸化シリコン膜３２を覆ってプラズ
マＣＶＤ法により酸化シリコン膜３３を形成する。酸化
シリコン膜３３は、酸化シリコン膜３２に対して実用上
十分な密着性を有する。プラズマＣＶＤ法により酸化シ
リコン膜３３を形成する場合、一例として、
基板温度：４００℃
原料ガス：ＳｉＨ４（２４０ｓｃｃｍ）＋Ｎ２Ｏ（５０
００ｓｃｃｍ）＋Ｎ２（２８００ｓｃｃｍ）
反応室内圧力：２．２Ｔｏｒｒ
とし、酸化シリコン膜３３の厚さは、５０ｎｍとするこ
とができる。(3) A silicon oxide film 33 is formed so as to cover the silicon oxide film 32 by the plasma CVD method. The silicon oxide film 33 has practically sufficient adhesion to the silicon oxide film 32. When the silicon oxide film 33 is formed by the plasma CVD method, as an example, the substrate temperature: 400 ° C. source gas: SiH 4 (240 sccm) + N 2 O (50
00 sccm) + N 2 (2800 sccm) Reaction chamber pressure: 2.2 Torr, and the thickness of the silicon oxide film 33 can be 50 nm.
【００１７】 （４）酸化シリコン膜３３を覆ってプラ
ズマＣＶＤ法により窒化シリコン膜３４を形成する。窒
化シリコン膜３４は、表面保護膜として役立つものであ
り、下地膜としての酸化シリコン膜３３に対して実用上
十分な密着性を有する。プラズマＣＶＤ法により窒化シ
リコン膜３４を形成する場合、成膜条件は、一例とし
て、
基板温度：４００℃
原料ガス：ＳｉＨ４，ＮＨ３，Ｎ２
反応室内圧力：２．５Ｔｏｒｒ
とし、窒化シリコン膜３４の厚さは、５００ｎｍとする
ことができる。(4) A silicon nitride film 34 is formed so as to cover the silicon oxide film 33 by a plasma CVD method. The silicon nitride film 34 serves as a surface protection film, and has practically sufficient adhesion to the silicon oxide film 33 as a base film. When the silicon nitride film 34 is formed by the plasma CVD method, the film forming conditions are, for example, a substrate temperature: 400 ° C., a source gas: SiH 4 , NH 3 , and N 2 reaction chamber pressure: 2.5 Torr. Can have a thickness of 500 nm.
【００１８】（５）窒化シリコン膜３４の上に周知のホ
トリソグラフィ処理によりボンディング孔に対応する孔
３６ａとスクライブ孔に対応する孔とを有するレジスト
層３６を形成する。(5) A resist layer 36 having a hole 36a corresponding to a bonding hole and a hole corresponding to a scribe hole is formed on the silicon nitride film 34 by a well-known photolithography process.
【００１９】（６）レジスト層３６をマスクとする選択
的ドライエッチング処理により膜３２，３３，３４の積
層にボンディング孔３４ａとスクライブ領域ＳＢを露呈
するスクライブ孔とを形成する。そして、レジスト層３
６を除去する。(6) A bonding hole 34a and a scribe hole exposing the scribe region SB are formed in the laminated film 32, 33, 34 by selective dry etching using the resist layer 36 as a mask. And the resist layer 3
Remove 6.
【００２０】この後は、スクライブ領域ＳＢに沿って基
板１０をスクライビングすることによりチップ領域ＣＰ
に相当するＬＳＩチップが得られる。ＬＳＩチップに
は、ボンディングワイヤ３８をボンディングしたり、樹
脂封止を施したりすることができる。After this, the substrate 10 is scribed along the scribe region SB to obtain the chip region CP.
An LSI chip corresponding to is obtained. A bonding wire 38 may be bonded to the LSI chip, or resin sealing may be performed.
【００２１】図６の半導体装置によれば、酸化シリコン
膜３２と酸化シリコン膜３３との密着性及び酸化シリコ
ン膜３３と窒化シリコン膜３４との密着性がいずれも実
用上十分であるので、窒化シリコン膜３４のはがれ耐性
が向上し、温度サイクル試験でも満足な結果が得られ
た。また、酸化シリコン膜３２により平坦性を向上させ
た面に窒化シリコン膜３４を形成するので、窒化シリコ
ン膜３４の被覆性が良好であり、耐湿性が改善される。
さらに、配線層１８，２０ａ〜２０ｃ等を覆う酸化シリ
コン膜３２の誘電率が３程度で低いので、配線間容量が
低減され、回路の高速化及び動作マージンの拡大が可能
となる。According to the semiconductor device of FIG. 6, the adhesion between the silicon oxide film 32 and the silicon oxide film 33 and the adhesion between the silicon oxide film 33 and the silicon nitride film 34 are both practically sufficient. The peeling resistance of the silicon film 34 was improved, and satisfactory results were obtained in the temperature cycle test. Further, since the silicon nitride film 34 is formed on the surface of which the flatness is improved by the silicon oxide film 32, the coverage of the silicon nitride film 34 is good and the moisture resistance is improved.
Furthermore, since the dielectric constant of the silicon oxide film 32 covering the wiring layers 18, 20a to 20c and the like is as low as about 3, the capacitance between wirings is reduced, and the circuit speed can be increased and the operation margin can be expanded.
【００２２】[0022]
【発明の効果】以上のように、この発明によれば、水素
シルセスキオキサン樹脂膜をセラミック化した酸化シリ
コン膜と窒化シリコン膜との間に密着性酸化シリコン膜
を介在配置する構成にしたので、窒化シリコン膜のはが
れ耐性が向上し、高信頼の半導体装置を実現できる効果
が得られる。また、この発明の構成では、窒化シリコン
膜の被覆性向上により耐湿性が改善される効果及び配線
間容量の低減により回路の高速化及び動作マージンの拡
大が可能になる効果は、従来通り維持される。As described above, according to the present invention, the adhesive silicon oxide film is arranged between the silicon oxide film and the silicon nitride film, which are ceramicized hydrogen silsesquioxane resin films. Therefore, the peeling resistance of the silicon nitride film is improved, and the effect of realizing a highly reliable semiconductor device is obtained. Further, in the configuration of the present invention, the effect of improving the moisture resistance by improving the coverage of the silicon nitride film and the effect of increasing the circuit speed and expanding the operation margin by reducing the capacitance between wirings are maintained as before. It
【００２３】その上、密着性酸化シリコン膜及び窒化シ
リコン膜をいずれもプラズマＣＶＤ法で形成するように
したので、実用上十分な密着性が得られる効果もある。In addition, since both the adhesive silicon oxide film and the silicon nitride film are formed by the plasma CVD method, there is an effect that sufficient adhesiveness can be obtained in practical use.
【図１】 この発明の一実施形態に係る半導体装置の製
法における配線形成工程を示す基板断面図である。FIG. 1 is a substrate cross-sectional view showing a wiring forming step in a method for manufacturing a semiconductor device according to an embodiment of the present invention.
【図２】 図１の工程に続く第１の酸化シリコン膜形成
工程を示す基板断面図である。FIG. 2 is a substrate cross-sectional view showing a first silicon oxide film forming step following the step of FIG.
【図３】 図２の工程に続く第２の酸化シリコン膜形成
工程を示す基板断面図である。FIG. 3 is a substrate cross-sectional view showing a second silicon oxide film forming step following the step of FIG.
【図４】 図３の工程に続く窒化シリコン膜形成工程を
示す基板断面図である。4 is a substrate cross-sectional view showing a silicon nitride film forming step following the step of FIG.
【図５】 図４の工程に続くレジスト層形成工程を示す
基板断面図である。FIG. 5 is a substrate cross-sectional view showing a resist layer forming step following the step of FIG.
【図６】 図５の工程に続く選択エッチング工程を示す
基板断面図である。FIG. 6 is a substrate cross-sectional view showing a selective etching step that follows the step of FIG.
１０：半導体基板、１２，１６：絶縁膜、１４，１８，
２０ａ〜２０ｃ，２２Ａ：配線層、２２：端子電極層、
３２，３３：酸化シリコン膜、３４：窒化シリコン膜、
３６：レジスト層、３８：ボンディングワイヤ、ＣＰ：
チップ領域、ＳＢ：スクライブ領域。10: semiconductor substrate, 12, 16: insulating film, 14, 18,
20a to 20c, 22A: wiring layer, 22: terminal electrode layer,
32 and 33: silicon oxide film, 34: silicon nitride film,
36: Resist layer, 38: Bonding wire, CP:
Chip area, SB: scribe area.
フロントページの続き (56)参考文献 特開 平４−181733（ＪＰ，Ａ) 特開 昭63−77139（ＪＰ，Ａ) 特開 平８−111458（ＪＰ，Ａ) 特開 平10−223627（ＪＰ，Ａ) 特開 平６−29282（ＪＰ，Ａ) 特開 平10−74755（ＪＰ，Ａ) 特開 平９−36116（ＪＰ，Ａ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 21/312 H01L 21/314 H01L 21/316 H01L 21/318 H01L 21/768 Continuation of front page (56) Reference JP-A-4-181733 (JP, A) JP-A-63-77139 (JP, A) JP-A-8-111458 (JP, A) JP-A-10-223627 (JP , A) JP-A-6-29282 (JP, A) JP-A-10-74755 (JP, A) JP-A-9-36116 (JP, A) (58) Fields investigated (Int.Cl. 7 , DB) Name) H01L 21/312 H01L 21/314 H01L 21/316 H01L 21/318 H01L 21/768
Claims (2)
線層を形成すると共に該複数の配線層を覆って水素シル
セスキオキサン樹脂膜をセラミック化した酸化シリコン
膜を形成し、該酸化シリコン膜を覆って表面保護膜とし
ての窒化シリコン膜を形成した半導体装置であって、 前記酸化シリコン膜及び前記窒化シリコン膜のいずれに
対しても密着性を有する密着性酸化シリコン膜を前記酸
化シリコン膜と前記窒化シリコン膜との間に介在配置し
たことを特徴とする半導体装置。1. A plurality of wiring layers are formed on an insulating film covering a semiconductor substrate, and a silicon oxide film obtained by ceramicizing a hydrogen silsesquioxane resin film is formed so as to cover the plurality of wiring layers and the oxidation is performed. A semiconductor device in which a silicon nitride film as a surface protection film is formed to cover a silicon film, wherein an adhesive silicon oxide film having adhesiveness to both the silicon oxide film and the silicon nitride film is used as the silicon oxide film. A semiconductor device characterized in that it is disposed between a film and the silicon nitride film.
シリコン膜をいずれもプラズマ化学気相堆積法により形
成することを特徴とする請求項１記載の半導体装置の製
法。2. The method for manufacturing a semiconductor device according to claim 1, wherein both the adhesive silicon oxide film and the silicon nitride film are formed by a plasma chemical vapor deposition method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP03407599A JP3498619B2 (en) | 1999-02-12 | 1999-02-12 | Semiconductor device and its manufacturing method. |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP03407599A JP3498619B2 (en) | 1999-02-12 | 1999-02-12 | Semiconductor device and its manufacturing method. |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2000232100A JP2000232100A (en) | 2000-08-22 |
| JP3498619B2 true JP3498619B2 (en) | 2004-02-16 |
Family
ID=12404152
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP03407599A Expired - Fee Related JP3498619B2 (en) | 1999-02-12 | 1999-02-12 | Semiconductor device and its manufacturing method. |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3498619B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7202563B2 (en) | 2004-03-25 | 2007-04-10 | Kabushiki Kaisha Toshiba | Semiconductor device package having a semiconductor element with resin |
| KR101123522B1 (en) * | 2008-03-24 | 2012-03-12 | 후지쯔 가부시끼가이샤 | Wiring board, semiconductor device, and process for producing semiconductor device |
-
1999
- 1999-02-12 JP JP03407599A patent/JP3498619B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JP2000232100A (en) | 2000-08-22 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100421826B1 (en) | Semiconductor device and its production process | |
| US20030020165A1 (en) | Semiconductor device, and method for manufacturing the same | |
| JP3631076B2 (en) | Semiconductor device structure | |
| JPH06244185A (en) | Wiring structure and its manufacture | |
| JP3435186B2 (en) | Semiconductor device | |
| JP3498619B2 (en) | Semiconductor device and its manufacturing method. | |
| JP3125781B2 (en) | Semiconductor device manufacturing method | |
| JP2904110B2 (en) | Method for manufacturing semiconductor device | |
| JPH06291202A (en) | Manufacture of semiconductor device | |
| JP3493863B2 (en) | Semiconductor device and its manufacturing method. | |
| JP3259363B2 (en) | Method of forming bonding pad structure for semiconductor device | |
| JPH06267935A (en) | Manufacture of semiconductor device | |
| JPH0629294A (en) | Manufacture of semiconductor device | |
| JP2850341B2 (en) | Method for manufacturing semiconductor device | |
| JPH05234991A (en) | Semiconductor device | |
| JP3103912B2 (en) | Street structure of semiconductor wafer and method of manufacturing the same | |
| JPH09148326A (en) | Semiconductor device and method for manufacturing the same | |
| JP3688335B2 (en) | Semiconductor integrated circuit device, manufacturing method thereof, and semiconductor wafer | |
| JP3149169B2 (en) | Method for manufacturing semiconductor device | |
| JP2900718B2 (en) | Semiconductor device and manufacturing method thereof | |
| JP2727605B2 (en) | Semiconductor device and manufacturing method thereof | |
| JPS5974651A (en) | Semiconductor device | |
| JPH05175196A (en) | Wiring structure of semiconductor device | |
| JP3225879B2 (en) | Silicon oxide film forming method and multilayer wiring forming method | |
| JPS6248381B2 (en) |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20071205 Year of fee payment: 4 |
|
| S531 | Written request for registration of change of domicile |
Free format text: JAPANESE INTERMEDIATE CODE: R313532 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20071205 Year of fee payment: 4 |
|
| R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20081205 Year of fee payment: 5 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20081205 Year of fee payment: 5 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20091205 Year of fee payment: 6 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20101205 Year of fee payment: 7 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20101205 Year of fee payment: 7 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20111205 Year of fee payment: 8 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20111205 Year of fee payment: 8 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20121205 Year of fee payment: 9 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20131205 Year of fee payment: 10 |
|
| LAPS | Cancellation because of no payment of annual fees |