JPH03149820A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH03149820A JPH03149820A JP28948289A JP28948289A JPH03149820A JP H03149820 A JPH03149820 A JP H03149820A JP 28948289 A JP28948289 A JP 28948289A JP 28948289 A JP28948289 A JP 28948289A JP H03149820 A JPH03149820 A JP H03149820A
- Authority
- JP
- Japan
- Prior art keywords
- protective insulating
- insulating film
- film
- silicon oxide
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 27
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 230000001681 protective effect Effects 0.000 claims abstract description 35
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 24
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 24
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 21
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 21
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims abstract 2
- 238000000034 method Methods 0.000 claims description 15
- 238000010438 heat treatment Methods 0.000 claims description 12
- 238000005530 etching Methods 0.000 claims description 5
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 229910052760 oxygen Inorganic materials 0.000 claims description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims 1
- 238000000605 extraction Methods 0.000 claims 1
- 239000001301 oxygen Substances 0.000 claims 1
- 229910000077 silane Inorganic materials 0.000 claims 1
- 229910052751 metal Inorganic materials 0.000 abstract description 23
- 239000002184 metal Substances 0.000 abstract description 23
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 abstract description 5
- 230000000694 effects Effects 0.000 description 8
- 239000007789 gas Substances 0.000 description 8
- 239000010410 layer Substances 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 239000010703 silicon Substances 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- 230000007774 longterm Effects 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 229910052799 carbon Inorganic materials 0.000 description 2
- 238000011109 contamination Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 230000005012 migration Effects 0.000 description 2
- 238000013508 migration Methods 0.000 description 2
- 238000012858 packaging process Methods 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 206010007559 Cardiac failure congestive Diseases 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 101001015052 Zea mays Trypsin/factor XIIA inhibitor Proteins 0.000 description 1
- 239000007864 aqueous solution Substances 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000009563 continuous hemofiltration Methods 0.000 description 1
- 230000008602 contraction Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 238000010137 moulding (plastic) Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 239000012071 phase Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
【産業上の利用分野１
本発明は、積層構造の保護絶縁膜を有する半導体装置の
製造方法に関する。
【従来の技術１
従来、ＬＳＩ等に用いる半導体装置の最終金属配線上の
保護絶縁膜は、コンタミネーションや水分の侵入を防ぐ
為に、低温の電相成長（ＣＶＤ）によるプラズマシリコ
ン窒化膜が用いられ、又３〜９ＸＩＯ”ｄｙｎ／ｃｍ婁
もあるシリコン窒化膜のストレスを緩和する為、一般に
は、下層にＣＶＤによるシリコン酸化膜あるいはそのＰ
ＳＧ膜（リンガラス）を敷いた構造が用いられている。
従来の半導体装置の製造方法は、例えば、第３図に示す
如（半導体素子が作り込まれたシリコン基板１仕のフィ
ールド絶縁膜１２や層間絶縁膜１３を介してＡＩやその
合金で厚みが１．Ｏｕｍ前後の金属配線１４上に、第１
の保護膜１５として４００℃以下の比較的低温でＳ ｉ
ＨａとＯ，もしくはこれにＰ Ｈｓを反応させて気相
成長した３０００〜６０００Ａ程度のシリコン酸化膜も
しくはＰＳＧ膜と、更に第２の保護膜１６として同じ（
低温でＳ ｉ ＨａとＮ ＨｓあるいはＮ、とを高周波
プラズマ中で電相成長したシリコン窒化膜を約０、５〜
１．０ｇｍ積層、させ（第３図（ａ））。
その後バターニングしたフォトレジストをマスクにし、
まずシリコン窒化請，続いてシリコン酸化膜等をＣＦ−
，ＣＨＦｓ 、Ｃｍ ＦＩＩの様なフロン系ガス等を用
いてドライエッチングし、外部電極取り出し用のボンデ
ィングパッド１８を開孔している（第３図（ｂ））。
【発明が解決しようとする課題ｌ
しかしながら従来技術では、以下の様に多くの問題点を
有している。集積回路の様にチップ化された半導体装置
は、プリント基板等紀組み込み易くする為にパッケージ
されるが、ワイヤーボンディング、ダイボンディングや
プラスチックモールドが施される工程の加熱によって、
保護絶縁膜と金属配線のストレスバランスの変化、伸縮
により第４図の如く、ポン、ディングパッド領域や電源
ラインの様に幅が数十ｇｍ以上の比較的太い金属配線Ｉ
４にＶ形をしたノツチ１９が入ってしまい、初期断線不
良やマイグレーション特性を含めた長期信頼性に問題が
生じていた。保護絶縁膜がシリコン窒化膜−層であると
きは、数ｕｍ以下の細い金属配線のみにノツチが発生す
る。又、金属配線上に形成するシリコン酸化膜やＰＳＧ
膜の気相成長条件は、絶縁膜自身のクラックを発生させ
ない様に、減圧反応を用いるが、成長速度が４０〜１０
０人／ｍｉｎと遅いことからバッチ処理をしている。こ
の結果、減圧やデポ時間が長くなりＡＩヒロックの成長
を促し、特にサブミクロン程度に微細化された金属配線
スペース間には横方向の七ロックが成長し、リークや信
頼性のー題となっていた。更に、金属配線の形成はドラ
イエッチング化され、一断面形状が急峻化されると共に
１スペクト比（段差／スペース）が大きくなる為、シリ
コン酸化謹あるいはＰＳＧ膜のカスビングによって、金
属配線１４のスペースにはボイド２１が形成され、コン
タミネーシコントラツプとなる上、金属配線１４の側壁
部や底面部のシリコン窒化膜が、金属配線１４上に比較
して薄く、耐温性やバシベーシ効果がなくな−り半導体
装置の長期信頼性に問題があった。
本発明はかかる問題点を解決するものて、保護絶縁膜の
品質に関わる信頼性の向上を図り、微細半導体装置の安
定供給を目的としたものである。
ｆ課題を解決するための手ａ】
本発明の半導体装置の製造方法は、半導体装置の最終金
属配線上に、少なくとも第１の保護絶縁膜としてシリコ
ン酸化膜瘉形成する工程、該シリコン酸化膜の形成温度
より高い温度で熱処理を施す工程、第２の保護絶縁膜と
してプラズマ反応によるシリコン窒化膜を形成する工程
、外部電極取り出し用のボンディングパッドを開孔する
工程を具備したことを特徴とする特
末、本発明の半導体装置の製造方法は、半導体装置の最
終金属配線上に、少なくとも第１の保護絶縁膜としてシ
リコン酸化膜を形成する工程、該シリコン酸化膜の形成
温度より高い温度で熱処理を施す工程、該シリコン酸化
膜をエッチングし第１のボンディングパッドを開孔する
工程、第２の保護絶縁膜としてプラズマ反応によるシリ
コン窒化膜を形成する工程、該シリゴン窒化膜をエッチ
ングし第２のボンディングパッドを開孔する工程を具備
したことを特徴とする特
ｖ実 施 例１
第”１図は本発明の半導体装置の製造方法の一実施例に
ついて説明する為の概略断面図であり、ＳｉゲートＣＭ
ＯＳメモリーの絶縁保護膜に適用した場合を示している
。シリコン基板１１には、ＭＯＳ）ランジスタ、抵抗や
容量等の半導体素子が形成され、フィールド絶縁膜１２
や層間絶縁膜１３を介して不純物層１７等からのコンタ
クトホールが開孔され、ＳｉＪｌ′）Ｃｕを約１％含ん
だＡｔを約１．０ｇｍスパッタリングした後、フォトリ
ソ工程で最小間隔が０．８〜１．２３ｍにパターン形成
した後、Ｃ２２系のガスでドライエッチングしほぼ垂直
に側面が形成された金属配線１４を施しである。この上
に約３８０℃でロードロック枚葉式ＣＶＤ装置により３
７０〜３８０℃、１０ｔｏｒｒ以下の圧力でＴＥＯＳ
［Ｓｉ （Ｃ，Ｈ。
０）４】と０８をプラズマ反応させシリコン酸化膜を約
３０００人成長させ第１の保護絶縁膜１５とした。この
時膜成長開始までの加熱時間は２０秒、成長速度は約３
０００人成長であり全処理時間は３分以内でＡＩヒルロ
ックの成長は極少ない、次に４５０℃の３％ＨａのＡｒ
雰囲気中で２０〜３０分熱処理を施した（第１図（ａ）
）。
この時も、金属配線１４の表面はシリコン酸化膜で覆わ
れておりＡＩヒルロックの成長はほとんどない、更にＳ
Ｉ Ｈ４、Ｎ ＨｓとＮ３を含むガス中の平行平板３
７０℃、５ｔＯｒｒで、プラズマ反応させたシリコン窒
化膜を約６０００人積層させ第２の保護絶縁膜１６とし
た（第１図（ｂ））。
続いて、パターニングセされたフォトレジストをマスク
にし、シリコン窒化膜はＣＦ、で、又シリコン酸化膜は
ＣＨＦＩとＣＦ、の混合ガスを用いてドライエッチング
し、外部電極取り出し用のボンディングパッド１８を開
孔しである（第１図（ｃ））。
このようにしてなる半導体装置は、従来の様にパッケー
ジ工程で金属配線１４にＶ形のノツチがはいることもな
くなり、又ヒロックによる不良も激減した。更に、第１
の保護絶縁膜１５としたシリコン酸化膜を従来のＳｉｎ
、に替えてＴＥＯＳを用いた為にカスビングがなくなり
、金属配線間のシリコン窒化膜の回り込みも良好になり
耐湿性の向上を図る事ができた。又Ｈａ ／ Ａ ｒ混
合ガスを用いる熱処理は、門値電圧や高抵抗値を安定化
する意味もあるが、耐ノツチ効果としては、単独ガスや
この他のＮｍ、Ｏｍ、Ｈｅ等の単独もしくはこれらの混
合ガスを用いても良い、又第１の保護絶縁膜１５として
付き回りを良くする為ＴＥＯＳを反応させたシリコン酸
化膜を用いたが、熱処理による耐ノツチ効果は、Ｓｉ−
Ｈ４で反応させたシリコン酸化膜のものにも効果はある
。
他の実施例として、第１の保護絶縁膜１５として、ＴＥ
ＯＳ、０２にＰ （ＯＣＨ）１を反応させたｐｓａｍを
適用したが、ストレス緩和効果も大きく、又前記実施例
と同様な改善効果もあった。
更に他の実施例として、第２図の如く、半導体素子が形
成されシリコン基板１１のフィールド絶縁１１１１２や
層間絶縁膜１３を介してコンタクトホールが開孔され、
Ｓｉ、Ｃｕを１％程度含んだＡ１を約１．０ｇｍスパッ
タリングした後、フォトリソ工程で最小間隔が０６８〜
１．２ｇｍにパターン形成し、Ｃｌ！系のガスでドライ
エッチングし、はぼ垂直に側面が形成された金属配線１
４を施しである。この上にロードロック枚葉式ＣＶＤ装
置により３７０〜３８０℃、１０ｔｏｒｒ以下の圧力で
ＴＥＯＳ （Ｓｉ （Ｃ，Ｈ，Ｏ） ４］、０２とＰ
（ＯＣＨ）、をプラズマ反応させＰＳＧ膜を約３０００
人成長させ第１の保護絶縁膜１５とした。次に約４５０
℃の３％Ｈ２のＡｒ雰囲眞中で２０〜３０分熱処理を施
した後、バターニングされたフォトレジストをマスクに
、ＨＦとＮＨ，Ｆ等の混合水溶液で、該ＰＳＧ膜に第１
のボンディングパッド１８”をオーバーエッチ気味に開
孔しく第２図（ａ））た。ここで、ＰＳＧ膜に第１のボ
ンディングパッド１８″を開孔してから熱処理をしても
良いが、開孔部にヒロックが発生し易い、次にＳｉＨ，
、ＮＨｍとＮ８を含むガス中で平行平板を用い、３７０
℃、５ｔｏｒｒでプラズマ反応させたシリコン窒化膜を
約６０００人積層させて、第２の保護絶縁膜１６とした
（第２図（ｂ））、次に、前記のバッド開孔と同じガラ
スマスクを用いてバターニングされたフォトレジストを
エッチングマスクにして、該シリコン窒化膜をＣＦ、で
ほぼ等方的にドライエッナングし、外部電極取り出し用
の第２のボンディングパッド１８を再び開孔した（第２
図（Ｃ））、この結果ボンディングパッド１８の開孔断
面酪こ於いては、ＰＳＧ膜がシリコン窒化膜で完全に覆
われてあり、ＰＳＧｌ［の＠湿が抑えられ、前記実施例
と同様な改善効果の他に半導体装置の耐湿性が更に向上
した。ここで、第２のボンディングパッド領域を第１の
ボンディングパッド領域の内側に形成する方法として、
ＰＳＧ膜のウェットエッチングを用いたが、この他の方
法として、ボンディングパッド寸法を変えたガラスマス
クを用いるか、第２のボンディングパッドを開孔する峙
番こフォトレジストをオーバーベイクフローして、開孔
寸法を小さくする方法も良いが、工数、再現性やコスト
の面で課題もある。
尚本発明は、ＭＯＳ−ＬＳＩの保護絶縁膜に限らず、バ
イポーラやＤＭＯＳ及びこれらを組み合わせたＬＳＩＩ
こも適用でき、金属配線としてはＡＩとＳｉやＣｕとの
合金に限られず、Ｔｉ。
Ｐｔ、Ｍｇ等を含むものや、ヒロック、コンタクトバリ
アの為にＴｉ、Ｗ、Ｐｔ、Ｍｏ等の高融点金属やその窒
化物、ケイ化物あるいはこれらの合金を上下に積層構造
としたもの、あるいは多層配線の半導体装置にも応用可
能である。
【発明の効果］
以上の様に本発明によれば、より微細化されたＭＯＳＬ
ＳＩ等の半導体装置に於ける保護絶縁膜のストレスバラ
ンス、構造や付き回りを改善し。
耐湿性、金属配線の耐マイグレーション特性や耐ヒルロ
ック特性等長期信頼性に係わる品質改善効果があり、工
程的にも容易に適用でき、より集積化、多機能化半導体
装置の安定供給紀寄与できるものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application 1] The present invention relates to a method for manufacturing a semiconductor device having a protective insulating film having a laminated structure. [Conventional technology 1] Conventionally, the protective insulating film on the final metal wiring of semiconductor devices used in LSI etc. is a plasma silicon nitride film produced by low-temperature galvanic phase growth (CVD) to prevent contamination and moisture intrusion. In order to alleviate the stress of the silicon nitride film, which has a thickness of 3 to 9 XIO" dyn/cm, a silicon oxide film or its P layer is generally used as the lower layer by CVD.
A structure in which an SG film (phosphorus glass) is laid is used. A conventional method for manufacturing a semiconductor device is, for example, as shown in FIG. .The first wire is placed on the metal wiring 14 before and after Oum.
As the protective film 15 of Si
The same film (
A silicon nitride film grown at low temperature by electrophase growth of SiHa and N Hs or N in high frequency plasma is deposited at about 0.5~
1.0 gm lamination (Fig. 3(a)). Then use the buttered photoresist as a mask.
First, silicon nitride is applied, then silicon oxide film, etc. is formed using CF-
, CHFs, Cm FII, etc., to form a bonding pad 18 for taking out the external electrode (FIG. 3(b)). Problems to be Solved by the Invention 1 However, the conventional technology has many problems as described below. Semiconductor devices made into chips such as integrated circuits are packaged to make it easier to integrate them into printed circuit boards, but due to the heating during wire bonding, die bonding, and plastic molding processes,
Due to changes in the stress balance between the protective insulating film and the metal wiring, as well as expansion and contraction, as shown in Figure 4, relatively thick metal wiring I with a width of several tens of gm or more is created, such as in pad areas and power supply lines.
4 had a V-shaped notch 19, which caused problems in long-term reliability including initial disconnection and migration characteristics. When the protective insulating film is a silicon nitride film layer, notches occur only in thin metal wirings of several micrometers or less. In addition, silicon oxide film or PSG formed on metal wiring
The vapor phase growth conditions for the film include a reduced pressure reaction so as not to cause cracks in the insulating film itself, but the growth rate is 40-10
Batch processing is used because it is slow at 0 people/min. As a result, depressurization and deposition times become longer, promoting the growth of AI hillocks, and especially lateral locks grow between submicron-sized metal wiring spaces, causing leakage and reliability problems. was. Furthermore, the metal wiring is formed by dry etching, which makes the cross-sectional shape steeper and increases the aspect ratio (step/space). In addition, voids 21 are formed, resulting in a contamination trap, and the silicon nitride film on the side walls and bottom surface of the metal wiring 14 is thinner than that on the metal wiring 14, so that the temperature resistance and the vacuum effect are lost. - There were problems with the long-term reliability of semiconductor devices. The present invention is intended to solve these problems, and aims to improve the reliability related to the quality of the protective insulating film, and to stably supply fine semiconductor devices. A method for manufacturing a semiconductor device according to the present invention includes a step of forming a silicon oxide film as at least a first protective insulating film on a final metal wiring of a semiconductor device, and a step of forming a silicon oxide film as at least a first protective insulating film. A special feature characterized by comprising the steps of performing heat treatment at a temperature higher than the formation temperature, forming a silicon nitride film by plasma reaction as a second protective insulating film, and forming a hole for a bonding pad for taking out an external electrode. Finally, the method for manufacturing a semiconductor device of the present invention includes the step of forming a silicon oxide film as at least a first protective insulating film on the final metal wiring of the semiconductor device, and performing heat treatment at a temperature higher than the formation temperature of the silicon oxide film. a step of etching the silicon oxide film to open a first bonding pad, a step of forming a silicon nitride film by plasma reaction as a second protective insulating film, a step of etching the silicon nitride film and forming a second bonding pad. EXAMPLE 1 FIG. CM
The case where it is applied to an insulating protective film of an OS memory is shown. Semiconductor elements such as MOS transistors, resistors, and capacitors are formed on the silicon substrate 11, and a field insulating film 12 is formed on the silicon substrate 11.
Contact holes are opened from the impurity layer 17 and the like through the interlayer insulating film 13, and after sputtering about 1.0 g of At containing about 1% SiJl')Cu, a minimum spacing of 0.8 is formed in a photolithography process. After forming a pattern with a thickness of ~1.23 m, dry etching was performed using a C22 gas to form a metal wiring 14 with substantially vertical side surfaces. On top of this, 3
TEOS at 70-380℃ and pressure below 10torr
[Si (C, H. 0) 4] and 08 were subjected to a plasma reaction to grow a silicon oxide film of about 3,000 layers to form the first protective insulating film 15. At this time, the heating time until the start of film growth was 20 seconds, and the growth rate was approximately 3
000 people growth and the total processing time is within 3 minutes, and the growth of AI hillock is extremely small.
Heat treatment was performed in an atmosphere for 20 to 30 minutes (Fig. 1(a)
). At this time as well, the surface of the metal wiring 14 is covered with a silicon oxide film, and there is almost no growth of AI hillocks.
Parallel plate 3 in a gas containing I H4, N Hs and N3
Approximately 6,000 silicon nitride films subjected to plasma reaction at 70° C. and 5 tOrr were laminated to form the second protective insulating film 16 (FIG. 1(b)). Next, using the patterned photoresist as a mask, the silicon nitride film is dry-etched using CF, and the silicon oxide film is dry-etched using a mixed gas of CHFI and CF to open the bonding pad 18 for taking out the external electrode. It is a hole (Fig. 1(c)). In the semiconductor device manufactured in this manner, V-shaped notches are no longer formed in the metal wiring 14 during the packaging process as in the conventional packaging process, and defects due to hillocks are also drastically reduced. Furthermore, the first
The silicon oxide film used as the protective insulating film 15 of
Since TEOS was used instead of , there was no cussing, and the silicon nitride film was able to wrap around between the metal wirings well, making it possible to improve moisture resistance. Heat treatment using a Ha/Ar mixed gas also has the meaning of stabilizing the gate voltage and high resistance value, but for the notch resistance effect, heat treatment using a single gas or other gases such as Nm, Om, He, etc. alone or these Alternatively, a silicon oxide film reacted with TEOS was used as the first protective insulating film 15 to improve coverage, but the notch resistance effect due to heat treatment is
A silicon oxide film reacted with H4 is also effective. As another example, as the first protective insulating film 15, TE
psam, in which P (OCH) 1 was reacted with OS, 02, was applied, and it had a great stress relieving effect, and also had the same improvement effect as in the previous example. In yet another embodiment, as shown in FIG. 2, a semiconductor element is formed and a contact hole is opened through the field insulation 11112 of the silicon substrate 11 and the interlayer insulation film 13.
After sputtering about 1.0 gm of A1 containing about 1% of Si and Cu, the minimum spacing is 0.68~
Patterned to 1.2gm, Cl! Metal wiring 1 with nearly vertical sides formed by dry etching with a system gas
4 is alms. On top of this, TEOS (Si (C, H, O) 4], 02 and P
(OCH), is subjected to a plasma reaction to form a PSG film of about 3000
The first protective insulating film 15 was grown. Next about 450
After heat treatment for 20 to 30 minutes in a 3% H2 Ar atmosphere at ℃, the PSG film is first coated with a mixed aqueous solution of HF, NH, F, etc. using the patterned photoresist as a mask.
The first bonding pad 18'' was opened in a slightly over-etched manner (Fig. 2(a)).Here, heat treatment may be performed after the first bonding pad 18'' is opened in the PSG film. Hillocks are likely to occur in the hole, followed by SiH,
, using a parallel plate in a gas containing NHm and N8, 370
About 6,000 silicon nitride films subjected to plasma reaction at 5 Torr were laminated to form the second protective insulating film 16 (Figure 2(b)). Using the patterned photoresist as an etching mask, the silicon nitride film was dry-etched almost isotropically with CF, and the second bonding pad 18 for taking out the external electrode was opened again (second
As a result, in the cross-section of the opening of the bonding pad 18, the PSG film is completely covered with the silicon nitride film, and the moisture of PSGl is suppressed, similar to the previous embodiment. In addition to the improvement effect, the moisture resistance of the semiconductor device was further improved. Here, as a method for forming the second bonding pad region inside the first bonding pad region,
Wet etching of the PSG film was used, but other methods include using a glass mask with different bonding pad dimensions or overbake-flowing the same photoresist that opens the second bonding pad. A method of reducing the hole size is also good, but there are problems in terms of man-hours, reproducibility, and cost. The present invention is applicable not only to the protective insulating film of MOS-LSI, but also to bipolar, DMOS, and LSII that combines these.
This can also be applied, and the metal wiring is not limited to alloys of AI and Si or Cu, but also Ti. Those containing Pt, Mg, etc., those with a stacked structure of high melting point metals such as Ti, W, Pt, Mo, their nitrides, silicides, or their alloys for hillocks and contact barriers, or multilayers. It can also be applied to wiring semiconductor devices. [Effects of the Invention] As described above, according to the present invention, a finer MOSL
Improves the stress balance, structure, and coverage of protective insulating films in semiconductor devices such as SI. It has quality improvement effects related to long-term reliability such as moisture resistance, migration resistance of metal wiring, and hillock resistance, and can be easily applied in terms of process, contributing to the stable supply of more integrated and multifunctional semiconductor devices. It is.
第１図（ａ）〜（Ｃ）、及び第２図（ａ）〜（ｃ）は本
発明による半導体装置の製造方法の実施例を示す概略断
面図である。
第３ｅｌ （ａ）、（ｂ）及び第４図は、従来の半導体
装置の製造方法に係わる概略断面図である、 −１１・
・−シリコン基板
１２・・・フロールド絶縁膿
１３・・・層間絶縁膜
１４・−・金属配線
１５・・・第１の保護絶縁膜
１６・・・第２の保護絶縁膜
１７・・・不純物層
１８・・・ボンディングパッド
１９・・・ノツチ
２０・・・集積回路チップ
２１・・・ボイド
以上
−出願人 セイコーエブソツ株式会社
代理人 弁理士 鈴 木 喜三部（他１名）、，４ｔ３FIGS. 1(a) to (C) and FIGS. 2(a) to (c) are schematic cross-sectional views showing an embodiment of the method for manufacturing a semiconductor device according to the present invention. 3el (a), (b) and FIG. 4 are schematic cross-sectional views related to a conventional method for manufacturing a semiconductor device. -11.
・-Silicon substrate 12... Fluord insulating film 13... Interlayer insulating film 14... Metal wiring 15... First protective insulating film 16... Second protective insulating film 17... Impurity layer 18...Bonding pad 19...Notch 20...Integrated circuit chip 21...Void or more - Applicant Seiko Ebsotsu Co., Ltd. Agent Patent attorney Kizobe Suzuki (1 other person), 4t3
Claims (4)
の保護絶縁膜としてシリコン酸化膜を形成する工程、該
シリコン酸化膜の形成温度より高い温度で熱処理を施す
工程、第２の保護絶縁膜としてプラズマ反応によるシリ
コン窒化膜を形成する工程、外部電極取り出し用のボン
ディングパッドを開孔する工程を具備したことを特徴と
する半導体装置の製造方法。(1) At least the first
a process of forming a silicon oxide film as a protective insulating film, a process of performing heat treatment at a temperature higher than the formation temperature of the silicon oxide film, a process of forming a silicon nitride film by plasma reaction as a second protective insulating film, and an external electrode extraction process. 1. A method for manufacturing a semiconductor device, comprising the step of opening a bonding pad for use in a semiconductor device.
マ反応させたシリコン酸化膜でなることを特徴とする請
求項１記載の半導体装置の製造方法。(2) The method of manufacturing a semiconductor device according to claim 1, wherein the first protective insulating film is made of a silicon oxide film obtained by subjecting organic silane and oxygen to a plasma reaction.
の保護絶縁膜としてシリコン酸化膜を形成する工程、該
シリコン酸化膜の形成濃度より高い温度で熱処理を施す
工程、該シリコン酸化膜をエッチングし第１のボンディ
ングパッドを開孔する工程、第２の保護絶縁膜としてプ
ラズマ反応によるシリコン窒化膜を形成する工程、該シ
リコン窒化膜をエッチングし第２のボンディングパッド
を開孔する工程を具備したことを特徴とする半導体装置
の製造方法。(3) At least the first
a step of forming a silicon oxide film as a protective insulating film; a step of performing heat treatment at a temperature higher than the formation concentration of the silicon oxide film; a step of etching the silicon oxide film to open a first bonding pad; A method for manufacturing a semiconductor device, comprising the steps of forming a silicon nitride film as a protective insulating film by plasma reaction, and etching the silicon nitride film to open a second bonding pad.
ンディングパッドの開孔領域より内側に形成されている
ことを特徴とする請求項３記載の半導体装置の製造方法
。(4) The method of manufacturing a semiconductor device according to claim 3, wherein the second bonding pad opening area is formed inside the opening area of the first bonding pad.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28948289A JP3149169B2 (en) | 1989-11-07 | 1989-11-07 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28948289A JP3149169B2 (en) | 1989-11-07 | 1989-11-07 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03149820A true JPH03149820A (en) | 1991-06-26 |
| JP3149169B2 JP3149169B2 (en) | 2001-03-26 |
Family
ID=17743850
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP28948289A Expired - Lifetime JP3149169B2 (en) | 1989-11-07 | 1989-11-07 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3149169B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP6598504B2 (en) | 2015-05-07 | 2019-10-30 | キヤノン株式会社 | Manufacturing method of semiconductor device |
-
1989
- 1989-11-07 JP JP28948289A patent/JP3149169B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JP3149169B2 (en) | 2001-03-26 |
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