JPS63157443A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS63157443A JPS63157443A JP30573686A JP30573686A JPS63157443A JP S63157443 A JPS63157443 A JP S63157443A JP 30573686 A JP30573686 A JP 30573686A JP 30573686 A JP30573686 A JP 30573686A JP S63157443 A JPS63157443 A JP S63157443A
- Authority
- JP
- Japan
- Prior art keywords
- organic silicon
- thin film
- oxide film
- silicon thin
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 24
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 239000010408 film Substances 0.000 claims abstract description 35
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 32
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 32
- 239000010703 silicon Substances 0.000 claims abstract description 32
- 239000010409 thin film Substances 0.000 claims abstract description 24
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 238000000034 method Methods 0.000 claims abstract description 19
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical class O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 13
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 13
- 125000000524 functional group Chemical group 0.000 claims abstract description 4
- 239000010410 layer Substances 0.000 abstract description 21
- 239000011229 interlayer Substances 0.000 abstract description 12
- 229910052782 aluminium Inorganic materials 0.000 abstract description 10
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 10
- 239000007788 liquid Substances 0.000 abstract description 10
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 abstract description 6
- 229910052760 oxygen Inorganic materials 0.000 abstract description 6
- 239000001301 oxygen Substances 0.000 abstract description 6
- 238000010438 heat treatment Methods 0.000 abstract description 4
- 238000009792 diffusion process Methods 0.000 abstract description 2
- 238000005530 etching Methods 0.000 abstract description 2
- 238000005468 ion implantation Methods 0.000 abstract description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 2
- 229920005591 polysilicon Polymers 0.000 abstract description 2
- 238000007669 thermal treatment Methods 0.000 abstract 1
- 229910052751 metal Inorganic materials 0.000 description 8
- 239000002184 metal Substances 0.000 description 8
- 239000011521 glass Substances 0.000 description 5
- 150000001875 compounds Chemical class 0.000 description 3
- 238000005336 cracking Methods 0.000 description 3
- 238000009413 insulation Methods 0.000 description 3
- 125000000217 alkyl group Chemical group 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、信頼性の高い多層配線構造を持つ半導体装置
を製造する方法に関する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method of manufacturing a semiconductor device having a highly reliable multilayer wiring structure.
従来の技術
半導体装置において、信頼性の高い多層配線構造を得る
だめには、金属配線層間の層間膜を平坦化する必要があ
る。従来この平坦化には、エッチバック法やリフトオフ
法が用いられてきた。これらの方法は層間膜が金属配線
間のすきまを完全に埋めることが前提となっている。と
ころが近年、半導体装置の高集積化に伴い、金属配線間
のすきまが狭くなり、そのすきまに絶縁膜を埋め込むこ
とが困難になった。よって上記の方法では平坦化が難し
い。近年、金属配線間の細いすきまにも絶縁膜を埋め込
むことできるバイアススパッタ法が開発されたが、バイ
アススパッタ法には、基板上に形成された素子にダメー
ジを与えるという欠点がある。そこで現在注目を浴びて
いるのがスピンオングラス法と呼ばれる方法である。こ
れは、無機または有機シリコン含有液を基板上に塗布し
熱処理を加えて無機または有機シリコン薄膜を形成する
ものであり、液体の塗布で絶縁膜を形成するために金属
配線間の細いすきまも埋めて平坦化することが可能とな
る。しかし、スピンオングラス法で形成したシIJ ”
1ン酸化膜にはクラックや剥離が生じやすいという欠点
があり、スピンオングラス法で形成した有機シリコン薄
膜には、クランクや剥離は生じにくいが絶縁特性が十分
でないという欠点があった。In conventional semiconductor devices, in order to obtain a highly reliable multilayer wiring structure, it is necessary to planarize the interlayer film between metal wiring layers. Conventionally, an etch-back method or a lift-off method has been used for this planarization. These methods are based on the premise that the interlayer film completely fills the gaps between metal wirings. However, in recent years, as semiconductor devices have become more highly integrated, the gaps between metal interconnects have become narrower, making it difficult to fill the gaps with insulating films. Therefore, flattening is difficult with the above method. In recent years, a bias sputtering method has been developed that can fill insulating films even into narrow gaps between metal wiring lines, but the bias sputtering method has the drawback of damaging elements formed on a substrate. Therefore, a method called the spin-on glass method is currently attracting attention. This involves applying an inorganic or organic silicon-containing liquid onto a substrate and applying heat treatment to form an inorganic or organic silicon thin film.In order to form an insulating film by applying the liquid, it also fills the narrow gaps between metal wiring. This makes it possible to flatten the surface. However, the IJ formed by the spin-on glass method
The 1N oxide film has the drawback of being prone to cracking and peeling, and the organic silicon thin film formed by the spin-on glass method has the drawback of not being susceptible to cracking and peeling, but does not have sufficient insulating properties.
発明が解決しようとする問題点
信頼性の高い多層配線構造を有する半導体装置を得るた
めには、配線金属層間の層間膜を平坦化する必要がある
。ところが前述の通り、素子の微細化が進んだ現在、従
来の平坦化法では限界にきている。そこで本発明者は従
来の方法の諸欠点を鑑み、今後さらに素子の微細化が進
んでも対応の可能なスピンオングラス法に注目し、スピ
ンオングラス法を用いて平坦化を行うとともに、シリコ
ン酸化膜、有機シリコン薄膜両方の長所を組み合わせて
、絶縁性が高くしかもクラックや剥離が生じない方法を
種々考案研究した結果、本発明を完問題1解決するため
の手段
表面に凹凸含有する半導体基板上に有機シリコン含有液
を塗布し、熱処理を加えた後基板を酸素プラズマ中にさ
らして有機シリコン薄膜表面の有機官能基をはずしシリ
コン酸化膜層と有機シリコン薄膜層の2層構造に変える
。Problems to be Solved by the Invention In order to obtain a semiconductor device having a highly reliable multilayer wiring structure, it is necessary to flatten the interlayer film between wiring metal layers. However, as mentioned above, as elements become increasingly miniaturized, conventional planarization methods are reaching their limits. Therefore, in view of the various drawbacks of the conventional methods, the present inventors focused on the spin-on glass method, which can be used even if elements become further miniaturized in the future. As a result of devising and researching various methods that combine the advantages of both organic silicon thin films and have high insulating properties without causing cracks or peeling, the present invention is a means for solving problem 1. After applying a silicon-containing liquid and applying heat treatment, the substrate is exposed to oxygen plasma to remove the organic functional groups on the surface of the organic silicon thin film, changing it to a two-layer structure of a silicon oxide film layer and an organic silicon thin film layer.
作用
有機シリコン薄膜を形成後、酸素プラズマにさらしてシ
リコン酸化膜層と有機シリコン薄膜層の2層構造にする
と、下部に有機シリコン薄膜層が存在するためにクラン
クや剥離等が生じにくくなる。また、上部金属配線と接
しているのはシリコン酸化膜なので絶縁特性は十分ある
。このようにして信頼性の高い多層配線構造を持つ半導
体装置が得られる。After forming a functional organic silicon thin film, if it is exposed to oxygen plasma to form a two-layer structure of a silicon oxide film layer and an organic silicon thin film layer, cranking and peeling are less likely to occur because of the presence of the organic silicon thin film layer below. Furthermore, since the silicon oxide film is in contact with the upper metal wiring, it has sufficient insulation properties. In this way, a semiconductor device having a highly reliable multilayer wiring structure can be obtained.
実施例
以下、図面に基づいて本発明について更に詳しく説明す
る。EXAMPLES The present invention will be explained in more detail below based on the drawings.
第1図から第4図は、本発明にかかる半導体装置の製造
方法の一実施例の工程を示す部分拡大断面図である。1 to 4 are partially enlarged cross-sectional views showing steps of an embodiment of the method for manufacturing a semiconductor device according to the present invention.
第1図において半導体基板1上に選択酸化法を用いてフ
ィールド酸化膜2を形成した後、ゲート岐化膜3、ポリ
7リコンゲート4を順に形成し、イオン打ち込み法によ
りソース、ドレイン領域に拡散層5を設ける。次に、ボ
ロンリンガラスなどの第1層間絶縁膜6全形成し、異方
性エツチングによりコンタクトホール7を形成する。こ
の上に1μ厚の第1アルミ配線8を形成し、第2層間絶
縁膜9を約5ooo人形成する。第2層間絶縁膜9とし
ては、プラズマCVD法で形成したシリコン酸化膜など
が適している。次に有機シリコン含有液を約3000人
塗布する。有機シリコン含有液としては(C6H5)n
S1(OH)4−nの構造を持つ化合物を含む溶液を用
いる。有機シリコン含有液は細い溝部にも入り込むので
、塗布前にあった基板上の凹凸はほとんどなくすことが
できる。次に半導体基板1に熱処理(室温から数段階に
分けて温度を上げ、最終460°Cで30分)を施し有
機シリコン薄膜10を形成する(第2図)。この後半導
体基板1を酸素プラズマ中に10分間さらすと、有機シ
リコン薄膜10の有機官能基が所定の深さまではずれ、
シリコン酸化膜に変化する。よって、最初に形成した有
機シリコン薄膜10の膜厚が薄いところはほとんどシリ
コン酸化膜11に変化し、膜厚が厚いところだけがシリ
コン酸化膜11と有機シリコン薄膜1oの2層構造にな
る(第3図)。In FIG. 1, after a field oxide film 2 is formed on a semiconductor substrate 1 using a selective oxidation method, a gate branching film 3 and a poly 7 recon gate 4 are formed in this order, and then diffused into the source and drain regions using an ion implantation method. Layer 5 is provided. Next, the first interlayer insulating film 6 made of borophosphorus glass or the like is entirely formed, and a contact hole 7 is formed by anisotropic etching. A first aluminum wiring 8 having a thickness of 1 μm is formed thereon, and a second interlayer insulating film 9 is formed by about 500 times. As the second interlayer insulating film 9, a silicon oxide film formed by a plasma CVD method or the like is suitable. Next, approximately 3,000 people applied a liquid containing organic silicon. As an organic silicon-containing liquid, (C6H5)n
A solution containing a compound having the structure S1(OH)4-n is used. Since the organic silicon-containing liquid enters even the narrow grooves, it is possible to almost eliminate the unevenness on the substrate that existed before application. Next, the semiconductor substrate 1 is subjected to a heat treatment (the temperature is increased in several steps from room temperature, and the final temperature is 460° C. for 30 minutes) to form an organic silicon thin film 10 (FIG. 2). When the semiconductor substrate 1 is then exposed to oxygen plasma for 10 minutes, the organic functional groups of the organic silicon thin film 10 are detached to a predetermined depth.
Changes to silicon oxide film. Therefore, most of the thinner parts of the initially formed organic silicon thin film 10 change to the silicon oxide film 11, and only the thicker parts become a two-layer structure of the silicon oxide film 11 and the organic silicon thin film 1o (see Figure 3).
基板上に配線層間のスルーホール12を設け、第2アル
ミ配線13を形成する(第4図)。基板上に有機シリコ
ン含有液?塗布して平坦化を施しであるため、第2アル
ミ配線13は断線やショートが起こりに〈〈なっている
。しかも第2アルミ配線13と直接液しているのはシリ
コン酸化膜11なので絶縁特性は十分ある。また、第1
アルミ配a8と第2アルミ配線13の層間膜の厚いとこ
ろはシリコン酸化膜と有機シリコン薄膜の2層構造にな
っており、下層に有機シリコン薄膜層があるためクラッ
クなどが入りにくい。A through hole 12 between wiring layers is provided on the substrate, and a second aluminum wiring 13 is formed (FIG. 4). Organic silicon-containing liquid on the substrate? Since it is coated and flattened, the second aluminum wiring 13 is prone to disconnections and short circuits. Moreover, since the silicon oxide film 11 is in direct contact with the second aluminum wiring 13, it has sufficient insulation properties. Also, the first
The thick part of the interlayer film between the aluminum wiring a8 and the second aluminum wiring 13 has a two-layer structure of a silicon oxide film and an organic silicon thin film, and cracks are difficult to occur because there is an organic silicon thin film layer underneath.
本発明による製造方法に用いる有機シリコン含iiはR
n5i(OH)4−n(R、アルキル基)の構造または
5i(OR)4(R:アルキル基)の構造を持った化合
物を含むことが望ましく、中でも本実施例で用いた(C
6H5)nSi(OH)4−n’を含む浴液が極めて優
れた特性を示す。The organosilicon containing ii used in the manufacturing method according to the present invention is R
It is desirable to include a compound having the structure n5i(OH)4-n(R, alkyl group) or 5i(OR)4(R: alkyl group), and among them, the compound used in this example (C
A bath solution containing 6H5)nSi(OH)4-n' exhibits extremely excellent properties.
発明の効果
本発明による製造方法ゲ用いると、簡単な工程により配
線金属層間の層間膜を平坦化することができる。しかも
シリコン酸化膜と有機シリコン薄膜全組み合わせている
ため、絶縁性が高くクラックや剥離音生じにくぐ、信頼
性の高い半導体装置金得ることができる。Effects of the Invention By using the manufacturing method according to the present invention, it is possible to flatten the interlayer film between wiring metal layers through a simple process. Furthermore, since the silicon oxide film and the organic silicon thin film are all combined, it is possible to obtain a highly reliable semiconductor device with high insulation properties and no cracking or peeling noise.
本発明による製造方法は、液体の塗布で平坦化を行って
いるため、今後さらに素子の微細化が進んでも対応でき
る。このような製造方法は他にはなく、極めて産業上価
値の高いものである。Since the manufacturing method according to the present invention performs flattening by applying a liquid, it can cope with even further progress in element miniaturization in the future. There is no other manufacturing method like this, and it is of extremely high industrial value.
第1図から第4図は本発明により半導体装置全製造する
場合の一実施例の工程を示し、第1図は本発明にかかる
製造方法に用いる半導体基板の部分拡大断面図、第2図
は有機シリコン薄膜形成後の半導体基板の部分拡大断面
図、第3図は半導体基板を酸素プラズマにさらした後の
半導体基板の部分拡大断面図、第4図は本発明にかかる
製造方法を用いた後第2アルミ配線全形成した後の半導
体基板の部分拡大断面図でるる。
1・・・・・・半導体基板、2・・・・・・フィールド
酸化膜、3・・・・・・ゲート酸化膜、4・・・・・・
ポリシリコンゲート、6・・・・・拡散層、6・・・・
・・第1層間絶縁膜、7・・・・・・コンタクトホール
、8°°゛パ第1アルミ配線、9・・・・・・第2層間
絶縁膜、1o・・・・・・有機シリコン薄膜、11・・
・・・・シリコンi化J11!、12・・・・・・スル
ーホール、13・・・・・第2アルミ配線。
代理人の氏名 弁理士 中 尾 敏 男 ほか1名第1
図
4、ボリシソコンゲー) Qv−邦し箇第2図
第3図
第4図1 to 4 show the steps of an embodiment of manufacturing a semiconductor device according to the present invention, FIG. 1 is a partially enlarged sectional view of a semiconductor substrate used in the manufacturing method according to the present invention, and FIG. FIG. 3 is a partial enlarged cross-sectional view of the semiconductor substrate after the organic silicon thin film has been formed. FIG. 3 is a partial enlarged cross-sectional view of the semiconductor substrate after the semiconductor substrate has been exposed to oxygen plasma. FIG. This is a partially enlarged sectional view of the semiconductor substrate after the second aluminum wiring is completely formed. 1...Semiconductor substrate, 2...Field oxide film, 3...Gate oxide film, 4...
Polysilicon gate, 6...diffusion layer, 6...
...First interlayer insulating film, 7...Contact hole, 8°° first aluminum wiring, 9...Second interlayer insulating film, 1o...Organic silicon Thin film, 11...
...Silicon i version J11! , 12...Through hole, 13...Second aluminum wiring. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 4, Borisisokonge) Qv-Koshika Figure 2 Figure 3 Figure 4
Claims (1)
有機シリコン薄膜の有機官能基を表面から所定の深さま
ではずす工程により、半導体基板上にシリコン酸化膜層
と有機シリコン薄膜層の2層構造を形成することを特徴
とする半導体装置の製造方法。a step of forming an organic silicon thin film on a semiconductor substrate;
A method for manufacturing a semiconductor device, comprising forming a two-layer structure of a silicon oxide film layer and an organic silicon thin film layer on a semiconductor substrate by a step of removing organic functional groups of the organic silicon thin film from the surface to a predetermined depth.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP30573686A JPS63157443A (en) | 1986-12-22 | 1986-12-22 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP30573686A JPS63157443A (en) | 1986-12-22 | 1986-12-22 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS63157443A true JPS63157443A (en) | 1988-06-30 |
Family
ID=17948725
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP30573686A Pending JPS63157443A (en) | 1986-12-22 | 1986-12-22 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS63157443A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04197957A (en) * | 1990-11-28 | 1992-07-17 | Fuji Tekkosho:Kk | Sheet like material speed difference absorbing accumulator |
US6719919B1 (en) | 1998-12-23 | 2004-04-13 | Micron Technology, Inc. | Composition of matter |
US7067414B1 (en) | 1999-09-01 | 2006-06-27 | Micron Technology, Inc. | Low k interlevel dielectric layer fabrication methods |
US7235499B1 (en) | 1999-01-20 | 2007-06-26 | Micron Technology, Inc. | Semiconductor processing methods |
-
1986
- 1986-12-22 JP JP30573686A patent/JPS63157443A/en active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04197957A (en) * | 1990-11-28 | 1992-07-17 | Fuji Tekkosho:Kk | Sheet like material speed difference absorbing accumulator |
US6719919B1 (en) | 1998-12-23 | 2004-04-13 | Micron Technology, Inc. | Composition of matter |
US7235499B1 (en) | 1999-01-20 | 2007-06-26 | Micron Technology, Inc. | Semiconductor processing methods |
US7067414B1 (en) | 1999-09-01 | 2006-06-27 | Micron Technology, Inc. | Low k interlevel dielectric layer fabrication methods |
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