JPH02125449A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH02125449A JPH02125449A JP16593389A JP16593389A JPH02125449A JP H02125449 A JPH02125449 A JP H02125449A JP 16593389 A JP16593389 A JP 16593389A JP 16593389 A JP16593389 A JP 16593389A JP H02125449 A JPH02125449 A JP H02125449A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- forming
- contact hole
- resist pattern
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 26
- 238000004519 manufacturing process Methods 0.000 title claims description 21
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 11
- 238000000034 method Methods 0.000 claims description 26
- 238000010438 heat treatment Methods 0.000 claims description 18
- 239000005360 phosphosilicate glass Substances 0.000 claims description 18
- 238000009792 diffusion process Methods 0.000 claims description 10
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 9
- 229910052796 boron Inorganic materials 0.000 claims description 9
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 8
- 239000005388 borosilicate glass Substances 0.000 claims description 8
- 229910052698 phosphorus Inorganic materials 0.000 claims description 8
- 239000011574 phosphorus Substances 0.000 claims description 8
- 239000011521 glass Substances 0.000 claims description 5
- 230000002093 peripheral effect Effects 0.000 claims 1
- 239000005380 borophosphosilicate glass Substances 0.000 abstract description 28
- 229910052710 silicon Inorganic materials 0.000 abstract description 13
- 239000010703 silicon Substances 0.000 abstract description 13
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 12
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 11
- 238000001312 dry etching Methods 0.000 abstract description 6
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 abstract description 4
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 abstract description 4
- 229910001873 dinitrogen Inorganic materials 0.000 abstract description 4
- 229910001882 dioxygen Inorganic materials 0.000 abstract description 4
- 229910052751 metal Inorganic materials 0.000 abstract description 4
- 239000002184 metal Substances 0.000 abstract description 4
- 239000010410 layer Substances 0.000 description 26
- 229910052782 aluminium Inorganic materials 0.000 description 10
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 9
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 210000004709 eyebrow Anatomy 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、多層配線を得るのに好適な半導体装置の製造
方法に関する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method of manufacturing a semiconductor device suitable for obtaining multilayer wiring.
従来の技術
超ＬＳＩプロセスにおいて、ボロンリンけい酸ガラス（
以下、ＢＰＳＧ膜と略す）は、多層配線の層間絶縁膜に
利用されている。眉間絶縁膜として使われる場合、ＢＰ
ＳＧ膜は通常２つの高温プロセス工程（フローとりフロ
ー）を経て、下層配線の凹凸を平坦化したり、コンタク
ト孔をスロープ化する。Conventional technology In the VLSI process, boron phosphosilicate glass (
A BPSG film (hereinafter abbreviated as BPSG film) is used as an interlayer insulating film for multilayer wiring. When used as an insulating film between the eyebrows, BP
The SG film usually undergoes two high-temperature process steps (flow control) to flatten the unevenness of the underlying wiring and to make the contact hole slope.
ＢＰＳＧ膜のフローとりフローを採用した従来のＭＯＳ
型半導体装置の製造方法を第３図ａ−Ｃの工程図を参照
して説明する。この製造方法では、先ず、シリコン基板
１の一方の主面側に選択酸化（ＬＯＧＯＳ）膜２、ゲー
ト酸化１ｌＩ３、多結晶シリコンゲート層４、拡散層５
を形成し、さらに基板表面全域に窒化シリコン膜６を堆
積する。Conventional MOS that uses BPSG film flow
A method for manufacturing a type semiconductor device will be described with reference to process diagrams of FIGS. 3a-3c. In this manufacturing method, first, on one main surface side of a silicon substrate 1, a selective oxidation (LOGOS) film 2, a gate oxide layer 1lI3, a polycrystalline silicon gate layer 4, a diffusion layer 5
A silicon nitride film 6 is further deposited over the entire surface of the substrate.
次に、例えば、ボロン濃度３重量％、リン濃度４重量％
のＢＰＳＧ膜７を堆積し、表面を平坦にするため酸素ガ
ス中、９００℃で６０分間の熱処理（フロー処理）を施
す。引き続きＢＰＳＧ膜膜７膜量７シリコン膜６にコン
タクト孔８を開孔する［第３図ａ］。次に、窒素ガス中
で、９００℃の熱処理（リフロー処理）を３０分間にわ
たり施す。Next, for example, the boron concentration is 3% by weight and the phosphorus concentration is 4% by weight.
A BPSG film 7 is deposited, and heat treatment (flow treatment) is performed at 900° C. for 60 minutes in oxygen gas to flatten the surface. Subsequently, a contact hole 8 is formed in the silicon film 6 by 7 layers of the BPSG film [FIG. 3a]. Next, heat treatment (reflow treatment) at 900° C. is performed for 30 minutes in nitrogen gas.
この熱処理により急峻であったコンタクト孔２８の段差
部の形状２８ａが丸みを帯びる［第３図ｂ］。By this heat treatment, the shape 28a of the step portion of the contact hole 28, which had been steep, becomes rounded [FIG. 3b].
Ｒ１後に、上層配線としてアルミニウム配線３０を形成
することによりＭＯＳ型トランジスタが完成する［第３
図Ｃ］。After R1, a MOS transistor is completed by forming an aluminum wiring 30 as an upper layer wiring [Third
Figure C].
発明が解決しようとする課題
しかしながら、この場合はＢＰＳＧ膜２７膜間７した微
小なコンタクト孔２８がりフロー工程の熱処理の際にコ
ンタクト孔２８の側壁部でオーバーハングが生じる。こ
のオーバーハングによって、コンタクト孔内のアルミニ
ウム配線２０のステップカバレージが悪化し、アルミニ
ウム電極の断線やエレクトロマイグレーションなどにつ
ながる不都合が生じる。Problems to be Solved by the Invention However, in this case, an overhang occurs on the side wall of the contact hole 28 during the heat treatment of the flow process over the small contact hole 28 between the BPSG films 27 . This overhang deteriorates the step coverage of the aluminum wiring 20 within the contact hole, causing problems such as disconnection of the aluminum electrode and electromigration.
ＢＰＳＧ膜２７膜間７ン濃度やリン濃度を低くし、リフ
ローの程度を抑えることでコンタクト孔のオーバーハン
グを軽減できるが、この場合にはフロー工程においてＢ
ＰＳＧ膜２７膜間７に平坦化することができない。一方
、ＢＰＳＧｌｌＩ２７のオーバーハングを抑えるために
リフロー工程の熱処理温度を下げることや熱処理時間を
短（した場合、コンタクト孔２８の開口端縁２８ａにお
ける丸みやスロープができずアルミニウム配線のステッ
プカバレージが改善されないという問題が生じる。The overhang of the contact hole can be reduced by lowering the interlayer concentration and phosphorus concentration of the BPSG film 27 and suppressing the degree of reflow.
It is not possible to flatten the PSG film 27 between the films 7. On the other hand, if the heat treatment temperature in the reflow process is lowered or the heat treatment time is shortened in order to suppress the overhang of the BPSGllI27, the step coverage of the aluminum wiring cannot be improved because the opening edge 28a of the contact hole 28 cannot be rounded or sloped. A problem arises.
課題を解決するための手段
本発明の製造方法の特徴は開孔されたコンタクト孔に絶
縁膜を形成するか、または開孔時にコンタクト孔の底面
に絶縁膜を残して熱処理（リフロー）を施し、コンタク
ト孔にスロープを付与するところにある。Means for Solving the Problems The manufacturing method of the present invention is characterized by forming an insulating film in the opened contact hole, or performing heat treatment (reflow) while leaving an insulating film on the bottom of the contact hole when the contact hole is opened. The point is to give a slope to the contact hole.
作用
本発明の製造方法によれば、アスペクト比の高いコンタ
クト孔にも適当なスロープを形成することができる。Effect: According to the manufacturing method of the present invention, an appropriate slope can be formed even in a contact hole having a high aspect ratio.
実施例
本発明にかかる半導体装置の製造方法の第１の実施例を
図面を参照して説明する。第１図ａ−ｅは、ＭＯＳ型集
積回路の製造工程図であり、簡明化のために１個のＭＯ
Ｓ型トランジスタ部を拡大して示した。Embodiment A first embodiment of the method for manufacturing a semiconductor device according to the present invention will be described with reference to the drawings. Figures 1a to 1e are manufacturing process diagrams of MOS type integrated circuits.
The S-type transistor section is shown enlarged.
本発明の製造方法でも、先ず、シリコン基板１の一方の
主面側に選択酸化（ＬＯＧＯ８）膜２、ゲート酸化膜３
、多結晶シリコンゲート層４、拡散層５からなるＭＯＳ
型素子を形成した後基板表面全域に窒化シリコン膜６を
堆積する。次に、例えばボロン濃度３重量％、リン濃度
４重量％の第１ＢＰＳＧｌｌＩ７を堆積し、表面を平坦
化するためたとえば酸素ガス中で９００℃、６０分間の
熱処理（フロー処理）を施す。引き続き、レジストパタ
ーンをマスクとしてドライエツチング処理を施し、第１
のＢＰＳＧ膜７と窒化シリコン膜６にコンタクト孔８を
開孔する［第１図ａ］。Also in the manufacturing method of the present invention, first, a selective oxidation (LOGO8) film 2 and a gate oxide film 3 are formed on one main surface side of the silicon substrate 1.
, a polycrystalline silicon gate layer 4, and a diffusion layer 5.
After forming the mold elements, a silicon nitride film 6 is deposited over the entire surface of the substrate. Next, a first BPSGllI7 having a boron concentration of 3% by weight and a phosphorus concentration of 4% by weight, for example, is deposited, and heat treatment (flow treatment) is performed at 900° C. for 60 minutes in oxygen gas, for example, to flatten the surface. Next, a dry etching process is performed using the resist pattern as a mask, and the first
A contact hole 8 is formed in the BPSG film 7 and the silicon nitride film 6 [FIG. 1a].
次に、レジストパターンを除き、例えばボロン濃度４重
量％、リン濃度２重量％の第２のＢＰＳＧ膜９を１５０
ｎｍ堆積する［第１図ｂ１゜次にたとえば窒素ガス中で
９００℃３０分間の熱処理（リフロー処理）を施す。こ
の工程で第１．第２のＢＰＳＧ膜７．９が溶融してコン
タクト孔の側壁部８ａにスロープが形成される。第１図
Ｃはリフロー処理が施された後の形状を示す図である。Next, the resist pattern is removed, and a second BPSG film 9 with a boron concentration of 4% by weight and a phosphorus concentration of 2% by weight, for example, is deposited at a temperature of 150%.
[FIG. 1b1°] Next, heat treatment (reflow treatment) is performed at 900° C. for 30 minutes in nitrogen gas, for example. In this process, the first step. The second BPSG film 7.9 is melted and a slope is formed on the side wall portion 8a of the contact hole. FIG. 1C is a diagram showing the shape after the reflow treatment.
このリフロー処理でコンタクト孔にテーパ形状のスロー
プが形成されるのは、第２８ＰＳＧ膜９が第１ ＢＰＳ
Ｇ膜７のオーバーハングを埋めるためであると考えられ
る。従来のように第１ＢＰＳＧ膜７のみでは、コンタク
ト孔の底面と第１ＢＰＳＧ膜７とで界面張力が作用して
オーバーハングが生じる。第２８ＰＳＧ膜９には、この
界面張力を小さくする効果もある。The reason why a tapered slope is formed in the contact hole by this reflow process is that the 28th PSG film 9 is
It is thought that this is to fill the overhang of the G film 7. If only the first BPSG film 7 is used as in the prior art, interfacial tension acts between the bottom of the contact hole and the first BPSG film 7, resulting in overhang. The 28th PSG film 9 also has the effect of reducing this interfacial tension.
次に、コンタクト孔８の底面にある第２８ＰＳＧ膜９を
ドライエツチング（ＣＨＦ３．０２ガス）で１分間はど
異方性エツチングして除去する［第１図０１゜
次に、従来の方法と同様に周知の方法でアルミニウム配
線１０を形成する［第１図ｅ］。以上の工程を経て二層
配線をもつＭＯＳ型集積回路が形成される。Next, the 28th PSG film 9 on the bottom surface of the contact hole 8 is removed by anisotropic dry etching (CHF3.02 gas) for 1 minute. Aluminum wiring 10 is formed by a well-known method [FIG. 1e]. Through the above steps, a MOS type integrated circuit with two-layer wiring is formed.
本発明の製造方法で形成した半導体装置を従来の方法で
形成した半導体装置と比較すると、コンタクト孔の開口
寸法１．４Ｘ１．４μ−においてアルミニウム配線のス
テップカバレージが６％から３４％へと顕著に改善され
る。Comparing the semiconductor device formed by the manufacturing method of the present invention with the semiconductor device formed by the conventional method, the step coverage of the aluminum wiring was significantly increased from 6% to 34% when the opening size of the contact hole was 1.4×1.4μ. Improved.
第２のＢＰＳＧ膜９のリン濃度を８％重量％以上に増加
させると次工程における熱処理（リフロー処理）でコン
タクト孔部の拡散層５に高濃度のリンが拡散される。When the phosphorus concentration of the second BPSG film 9 is increased to 8% by weight or more, a high concentration of phosphorus is diffused into the diffusion layer 5 in the contact hole portion in the heat treatment (reflow treatment) in the next step.
同様に第２図に第２の実施例を説明するためのＭＯ３型
集積回路の製造工程図を示す。Similarly, FIG. 2 shows a manufacturing process diagram of an MO3 type integrated circuit for explaining the second embodiment.
先ず、第２図ａに示すように、シリコン基板１１の一方
の主面側に選択酸化（ＬＯＧＯ８）膜１２、ゲート酸化
膜１３、多結晶シリコンゲート層１４、拡散層１５から
なるＭＯ３型素子を形成した後基板表面全域に窒化シリ
コン膜１６を堆積する。そして、この窒化シリコン膜１
６の上に、たとえばボロン濃度３重量％、リン濃度４重
量％のＢＰＳＧ膜１７を１μ°ｍ堆積し、表面を平坦化
するため、たとえば酸素ガス中で９００℃６０分間の熱
処理（フロー処理）を施す。そして、引き続き、レジス
トパターンをマスクとしてドライエツチング処理を施し
、多結晶シリコンゲート層１４上のＢＰＳＧ膜１７にコ
ンタクト孔１８を形成すると同時に窒化シリコン膜１６
にコンタクト孔１９を形成する。このとき、拡散層１５
上のコンタクト孔の底面にＢＰＳＧ膜１７膜上７窒化シ
リコン膜１６を残す状態でドライエツチング処理を終了
し、レジストパターンを除去する。First, as shown in FIG. 2a, an MO3 type element consisting of a selective oxidation (LOGO8) film 12, a gate oxide film 13, a polycrystalline silicon gate layer 14, and a diffusion layer 15 is formed on one main surface side of a silicon substrate 11. After the formation, a silicon nitride film 16 is deposited over the entire surface of the substrate. Then, this silicon nitride film 1
6, a BPSG film 17 having a boron concentration of 3% by weight and a phosphorus concentration of 4% by weight is deposited to a thickness of 1 μm, and heat treatment (flow treatment) at 900° C. for 60 minutes in oxygen gas, for example, is performed to flatten the surface. administer. Subsequently, a dry etching process is performed using the resist pattern as a mask to form a contact hole 18 in the BPSG film 17 on the polycrystalline silicon gate layer 14, and at the same time, the silicon nitride film 16 is etched.
A contact hole 19 is formed in. At this time, the diffusion layer 15
The dry etching process is completed with the silicon nitride film 16 on the BPSG film 17 remaining at the bottom of the upper contact hole, and the resist pattern is removed.
次に第２図すに示すように、窒素ガス中で９００℃３０
分間の熱処理（リフロー）を施す。この工程でＢＰＳＧ
膜１７膜上７してコンタクト孔１９の側壁部１９ａにス
ロープが形成される。この処理においてアスペクト比の
高いコンタクト孔１９に上下端部で丸みをもつテーパ状
のスロープが形成されるのは、従来において生じていた
コンタクト孔１９の下端部と窒化シリコン膜１６もしく
は拡散層１５との界面がなくなり、コンタクト孔１９の
下端部におけるＢＰＳＧ膜１７膜上７張力が小さくなっ
て、ＢＰＳＧ膜１７膜上７が適切に行われるためと考え
られる。このように、コンタクト孔１９のオーバーハン
グを防止することでコンタクト孔１９内の金属配線のカ
バレージを向上できる。また、多結晶シリコンゲート層
１４上のコンタクト孔１８は、若干のオーバーハングと
なるがアスペクト比が低いためコンタクト孔１８内の金
属配線のカバレージは満足できるものとなる。Next, as shown in Figure 2, the temperature was 30°C at 900°C in nitrogen gas.
Perform heat treatment (reflow) for 1 minute. In this process, BPSG
A slope is formed on the side wall portion 19a of the contact hole 19 above the film 17. In this process, a tapered slope with roundness at the upper and lower ends is formed in the contact hole 19 having a high aspect ratio because the lower end of the contact hole 19 and the silicon nitride film 16 or the diffusion layer 15 are It is thought that this is because the interface between the BPSG film 17 and the BPSG film 17 at the lower end of the contact hole 19 is eliminated, and the tension on the BPSG film 17 at the lower end of the contact hole 19 is reduced, so that the BPSG film 17 is properly formed. In this way, by preventing the contact hole 19 from overhanging, the coverage of the metal wiring within the contact hole 19 can be improved. Further, although the contact hole 18 on the polycrystalline silicon gate layer 14 has a slight overhang, since the aspect ratio is low, the coverage of the metal wiring within the contact hole 18 is satisfactory.
次に、第２図Ｃに示すように、アスペクト比の高いコン
タクト孔１９の底面にある膜厚２００ｎｍ程度のＢＰＳ
ＧＩｌ１１１７と窒化シリコン膜１６を基板表面全面に
わたるドライエツチングにて除去する。Next, as shown in FIG.
The GIl 1117 and the silicon nitride film 16 are removed by dry etching over the entire surface of the substrate.
次に、第１図ｄに示すように、従来の方法と同様に周知
の方法を用いてアルミニウム配線２０を形成する。以上
の工程を経て二層配線をもつＭＯＳ型集積回路が形成さ
れる。Next, as shown in FIG. 1d, aluminum wiring 20 is formed using a well-known method similar to the conventional method. Through the above steps, a MOS type integrated circuit with two-layer wiring is formed.
なお、本第１．第２の実施例ではＢＰＳＧ膜１７膜上７
て説明したが、リンけい酸ガラス（ＰＳＧ）、硼けい酸
ガラス（ＢＳＧ）および砒けい酸ガラス（ＡＳＳＧ）が
用いられる半導体装置にこの方法を実施しても同じ効果
があることを確認した。In addition, this book No. 1. In the second embodiment, 7 on the BPSG film 17
However, it has been confirmed that the same effect can be obtained even when this method is applied to semiconductor devices using phosphosilicate glass (PSG), borosilicate glass (BSG), and arsosilicate glass (ASSG).
また、本実施例はＭＯＳ集積回路の製造を例示して説明
したが、本発明はガラスリフローが必要な半導体装置全
般に応用できるものである。Further, although this embodiment has been described by exemplifying the manufacture of a MOS integrated circuit, the present invention can be applied to all semiconductor devices requiring glass reflow.
発明の詳細
な説明したように、本発明の製造方法によればコンタク
ト孔の適当な形状を得ることができるため、ＢＰＳＧ膜
等の絶縁膜上の金属配線の断線を防止することができ、
半導体装置の信頼性を大幅に向上させる効果がある。As described in detail of the invention, according to the manufacturing method of the present invention, it is possible to obtain a contact hole with an appropriate shape, so that disconnection of metal wiring on an insulating film such as a BPSG film can be prevented.
This has the effect of significantly improving the reliability of semiconductor devices.
第１図ａ−ｅは本発明にかかる半導体装置の製造方法の
第１の実施例を示す工程断面図、第２図ａ−ｄは本発明
の第２９実施例を示す工程断面図、第３図ａ−Ｃは従来
例の工程断面図である。
１・・・・・・シリコン基板、２・・・・・・ＬＯＣＯ
５膜、３・・・・・・ゲート酸化膜、４・・・・・・多
結晶シリコンゲート層、５・・・・・・拡散層、６・・
・・・・窒化シリコン膜、７・・・・・・第１ ＢＰＳ
Ｇ膜、８・・・・・・コンタクト孔、８ａ・・・・・・
Ｂ 、Ｐ Ｓ Ｇ腹側壁、９・・・・・・第２ＢＰＳＧ
膜、ｌＯ・・・・・・アルミニウム配線、１１・・・・
・・シリコン基板、１２・・・・・・ＬＯＣＯ８膜、１
３・・・・・・ゲート酸化膜、１４・・・・・・多結晶
シリコンゲート層、１５・・・・・・拡散層、１６・・
・・・・窒化シリコン膜、１７・・・・・・第１ＢＰＳ
Ｇ膜、１８．１９・・・・・・コンタクト孔、１９ａ・
・・・・・ＢＰＳＧ膜側壁、２０・・・・・・アルミニ
ウム配線。
代理人の氏名 弁理士 粟野重孝 ばか１名／ −−−
シリコン基板
２−・・ｔＯｔＯ５＊
３−・ゲート酸化縁
４・−手繕晶シリコンブート漕
５・−＄数層
６・−窒化シソコン獲
７・・−＊１のＢＰＳ（ｒ項
８°“フンタクト孔
９°−＠ ２ Ｆ３ｒＳｅ ｆｆ臭
１０・−・アルミニエフム四己優艮、
Ｕ−−シリコン基本次、
１２・−ｔｏｔｏｓ ａｌＩ
１３・−ゲート験化喚
１４− 少ｔｌｊＮ品シリコンゲート層１５−瓢敢層
１６− 菫化シリコン頃５
１７−ＢＰＳ（ｒ項
ｆδ°“フンタクト為1A to 1E are process sectional views showing the first embodiment of the method for manufacturing a semiconductor device according to the present invention, FIGS. 2A to 2D are process sectional views showing the 29th embodiment of the present invention, and FIGS. Figures a-C are process sectional views of a conventional example. 1...Silicon substrate, 2...LOCO
5 film, 3... gate oxide film, 4... polycrystalline silicon gate layer, 5... diffusion layer, 6...
...Silicon nitride film, 7...1st BPS
G film, 8...Contact hole, 8a...
B, PSG ventral wall, 9...2nd BPSG
Film, lO... Aluminum wiring, 11...
...Silicon substrate, 12...LOCO8 film, 1
3... Gate oxide film, 14... Polycrystalline silicon gate layer, 15... Diffusion layer, 16...
...Silicon nitride film, 17...1st BPS
G film, 18.19...Contact hole, 19a.
...BPSG film side wall, 20... Aluminum wiring. Name of agent: Patent attorney Shigetaka Awano One idiot / ---
Silicon substrate 2--tOtO5* 3--Gate oxidation edge 4--Typical silicon boot layer 5--Several layer 6--Nitride silicon layer 7...-*1 BPS (r term 8° "Funtact") Hole 9° - @ 2 F3rSe ff odor 10 - Aluminum Fum Shiki Yusuke, U - Silicon basic next, 12 - totos alI 13 - Gate experimentation 14 - Small tljN product silicon gate layer 15 - Hyoran Layer 16 - Polymerized silicon layer 5 17 - BPS (r term fδ°
Claims (7)
絶縁膜を形成する工程、前記第１の絶縁膜に第１の熱処
理を施して前記第１の絶縁膜の表面を平坦化する工程、
前記第１の絶縁膜上に所定のレジストパターンを形成す
る工程、前記レジストパターンをマスクにして前記第１
の絶縁膜にコンタクト孔を開孔する工程、前記レジスト
パターンを除去する工程、前記全工程を経た前記半導体
基板上にその表面形状にそった第２の絶縁膜を形成する
工程、第２の熱処理によって前記コンタクト孔の開口部
周縁および側壁部にスロープを形成する工程、前記コン
タクト孔の底部にある前記第２の絶縁膜を除去する工程
、を有することを特徴とする半導体装置の製造方法。(1) A step of forming a first insulating film on a semiconductor substrate on which a semiconductor element is built, and flattening the surface of the first insulating film by subjecting the first insulating film to a first heat treatment. process,
forming a predetermined resist pattern on the first insulating film; using the resist pattern as a mask, forming the first resist pattern on the first insulating film;
a step of forming a contact hole in the insulating film, a step of removing the resist pattern, a step of forming a second insulating film along the surface shape of the semiconductor substrate after passing through all the steps, and a second heat treatment. A method for manufacturing a semiconductor device, comprising the steps of: forming a slope on the opening periphery and sidewall of the contact hole; and removing the second insulating film at the bottom of the contact hole.
ラス（ＢＰＳＧ）、リンけい酸ガラス（ＰＳＧ）、硼け
い酸ガラス（ＢＳＧ）、砒けい酸ガラス（ＡＳＳＧ）の
いずれかを用いたことを特徴とする特許請求の範囲第１
項記載の半導体装置の製造方法。(2) As the first and second insulating films, one of boron phosphosilicate glass (BPSG), phosphosilicate glass (PSG), borosilicate glass (BSG), and arsosilicate glass (ASSG) was used. Claim 1 characterized in that
A method for manufacturing a semiconductor device according to section 1.
ラス（ＢＰＳＧ）を用い、前記第２の絶縁膜のリン濃度
を８重量％未満としたことを特徴とする特許請求の範囲
第１項記載の半導体装置の製造方法。(3) Boron phosphosilicate glass (BPSG) is used as the first and second insulating films, and the phosphorus concentration of the second insulating film is less than 8% by weight. A method for manufacturing a semiconductor device according to section 1.
を形成する工程、前記絶縁膜に第１の熱処理を施して前
記絶縁膜の表面を平坦化する工程、前記絶縁膜上に所定
のレジストパターンを形成する工程、前記レジストパタ
ーンをマスクにして底面に前記絶縁膜を一部だけ残した
状態のコンタクト孔を形成する工程、前記レジストパタ
ーンを除去する工程、第２の熱処理によって前記コンタ
クト孔の開口部周縁および側壁部にスロープを形成する
工程、前記コンタクト孔の底部にある前記絶縁膜を除去
する工程、を有することを特徴とする半導体装置の製造
方法。(4) a step of forming an insulating film on a semiconductor substrate on which a semiconductor element is built; a step of subjecting the insulating film to a first heat treatment to flatten the surface of the insulating film; forming a resist pattern, using the resist pattern as a mask to form a contact hole with only a portion of the insulating film remaining on the bottom surface, removing the resist pattern, and performing a second heat treatment to form the contact hole. 1. A method of manufacturing a semiconductor device, comprising the steps of: forming a slope on a peripheral edge of an opening and a side wall; and removing the insulating film at the bottom of the contact hole.
Ｇ）、リンけい酸ガラス（ＰＳＧ）、硼けい酸ガラス（
ＢＳＧ）、砒けい酸ガラス（ＡＳＳＧ）のいずれかを用
いたことを特徴とする特許請求の範囲第４項記載の半導
体装置の製造方法。(5) Boron phosphosilicate glass (BPS) is used as the insulating film.
G), phosphosilicate glass (PSG), borosilicate glass (
5. The method of manufacturing a semiconductor device according to claim 4, wherein either BSG) or arsosilicate glass (ASSG) is used.
両側の前記半導体基板表面に形成した拡散層とからなる
ＭＯＳ型半導体素子を形成する工程、前記半導体基板上
に絶縁膜を形成する工程、前記絶縁膜に第１の熱処理を
施して前記絶縁膜の表面を平坦化する工程、前記絶縁膜
上に所定のレジストパターンを形成する工程、前記レジ
ストパターンをマスクにして、前記多結晶シリコンゲー
ト層上の前記絶縁膜に前記多結晶シリコンゲート層にま
で至る第１のコンタクト孔を開孔するとともに、前記拡
散層上の前記絶縁膜に底面に前記絶縁膜を一部だけ残し
た状態の第２のコンタクト孔を開孔する工程、前記レジ
ストパターンを除去する工程、第２の熱処理によって前
記第１、第２のコンタクト孔の開口部周縁および側壁部
にスロープを形成する工程、前記第２のコンタクト孔の
底面に残っている前記絶縁膜を除去する工程、を有する
ことを特徴とする半導体装置の製造方法。(6) forming on a semiconductor substrate a MOS type semiconductor element consisting of a polycrystalline silicon gate layer and diffusion layers formed on the surface of the semiconductor substrate on both sides; forming an insulating film on the semiconductor substrate; a step of flattening the surface of the insulating film by subjecting the insulating film to a first heat treatment; a step of forming a predetermined resist pattern on the insulating film; and a step of forming the polycrystalline silicon gate layer using the resist pattern as a mask. A first contact hole is formed in the upper insulating film up to the polycrystalline silicon gate layer, and a second contact hole is formed in the insulating film on the diffusion layer with only a portion of the insulating film remaining on the bottom surface. a step of forming a contact hole, a step of removing the resist pattern, a step of forming a slope at the opening periphery and a side wall of the first and second contact holes by a second heat treatment, and a step of forming the second contact. A method for manufacturing a semiconductor device, comprising the step of removing the insulating film remaining on the bottom surface of the hole.
Ｇ）、リンけい酸ガラス（ＰＳＧ）、硼けい酸ガラス（
ＢＳＧ）、砒けい酸ガラス（ＡＳＳＧ）のいずれかを用
いたことを特徴とする特許請求の範囲第６項記載の半導
体装置の製造方法。(7) Boron phosphosilicate glass (BPS) is used as the insulating film.
G), phosphosilicate glass (PSG), borosilicate glass (
7. The method of manufacturing a semiconductor device according to claim 6, wherein either BSG) or arsosilicate glass (ASSG) is used.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63-161751 | 1988-06-29 | ||
| JP16175188 | 1988-06-29 | ||
| JP63-175975 | 1988-07-14 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02125449A true JPH02125449A (en) | 1990-05-14 |
Family
ID=15741196
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16593389A Pending JPH02125449A (en) | 1988-06-29 | 1989-06-28 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02125449A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04174518A (en) * | 1990-11-07 | 1992-06-22 | Nec Corp | Forming method for contact hole in semiconductor device |
| JPH04269853A (en) * | 1990-12-19 | 1992-09-25 | Samsung Electron Co Ltd | Reflow method of semiconductor device |
| JPH05190512A (en) * | 1991-05-30 | 1993-07-30 | American Teleph & Telegr Co <Att> | Integrated-circuit window etching and flattening |
| JPH07307339A (en) * | 1994-04-12 | 1995-11-21 | Sgs Thomson Microelettronica Spa | Even process |
| US5486267A (en) * | 1994-02-28 | 1996-01-23 | International Business Machines Corporation | Method for applying photoresist |
| KR100422819B1 (en) * | 1997-06-30 | 2004-05-24 | 주식회사 하이닉스반도체 | Method for fabricating semiconductor device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56116641A (en) * | 1980-02-20 | 1981-09-12 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPS5870556A (en) * | 1981-10-22 | 1983-04-27 | Fujitsu Ltd | Preparation of semiconductor device |
| JPS62235752A (en) * | 1986-04-07 | 1987-10-15 | Matsushita Electronics Corp | Manufacture of semiconductor device |
-
1989
- 1989-06-28 JP JP16593389A patent/JPH02125449A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56116641A (en) * | 1980-02-20 | 1981-09-12 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPS5870556A (en) * | 1981-10-22 | 1983-04-27 | Fujitsu Ltd | Preparation of semiconductor device |
| JPS62235752A (en) * | 1986-04-07 | 1987-10-15 | Matsushita Electronics Corp | Manufacture of semiconductor device |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04174518A (en) * | 1990-11-07 | 1992-06-22 | Nec Corp | Forming method for contact hole in semiconductor device |
| JPH04269853A (en) * | 1990-12-19 | 1992-09-25 | Samsung Electron Co Ltd | Reflow method of semiconductor device |
| JPH05190512A (en) * | 1991-05-30 | 1993-07-30 | American Teleph & Telegr Co <Att> | Integrated-circuit window etching and flattening |
| US5399532A (en) * | 1991-05-30 | 1995-03-21 | At&T Corp. | Integrated circuit window etch and planarization |
| US5486267A (en) * | 1994-02-28 | 1996-01-23 | International Business Machines Corporation | Method for applying photoresist |
| JPH07307339A (en) * | 1994-04-12 | 1995-11-21 | Sgs Thomson Microelettronica Spa | Even process |
| KR100422819B1 (en) * | 1997-06-30 | 2004-05-24 | 주식회사 하이닉스반도체 | Method for fabricating semiconductor device |
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