JPH02133941A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To obviate a heat treatment at a temperature 900 deg.C or above and to make a stable transistor by a method wherein an upper-layer insulating film formed of a specific oxide film is wet-etched and, after that, a lower-layer insulating film formed of a specific oxide film is dry-etched. CONSTITUTION:A silicon oxide film 7 containing B and P is laminated on an N<+> diffusion layer 3, a P<+> diffusion layer 4 and a silicon oxide film 6 which have been formed on a silicon substrate 1. Then, a silicon oxide film 8 containing P is laminated; then, insulating films of two layers by the film 7 and the film 8 insulate wiring parts. After that, the insulating films are heat- treated. Then, a photoresist 9 is coated; regions used to form contact holes 10 are removed selectively. Then, the film 8 is etched by using a hydrofluoric acid-based wet etching liquid. Then, the film 7 remaining in the regions of the holes 10 is etched by using a dry etching method; the holes 10 are made. Then, gentle slopes can be made at the holes 10; it is possible to eliminate a disconnection of a wiring metal without executing a heat treatment at 900 deg.C or higher.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field 1] The present invention relates to a method for forming contact holes in a semiconductor device.

[Summary of the Invention 1] The present invention relates to a method for forming contact holes used in semiconductor devices. ), and has a two-layer structure in which the second layer is a silicon oxide film (PSG film) containing phosphorus. After selectively baking the resist in the area where the contact hole is to be formed using photolithography, HF (hydrofluoric acid) is applied.
The second layer of PS is made using a wet etching solution mainly composed of
After all the G film is etched, the first layer BPSG film is etched using a dry etching method to form a contact hole.

[Prior Art] A conventional method for manufacturing a semiconductor device will be described with reference to FIGS. 2fa) to 2(d). FIGS. 2(a) to 2(d) show a diffusion layer 23 with a high concentration of N-type impurities formed on a silicon substrate 21,
2 is a cross-sectional view of a semiconductor device having a diffusion layer 24 heavily doped with N-type impurities and a polycrystalline silicon film 25 doped with N-type impurities in the order of manufacturing steps. FIG. 2(a) shows a cross-sectional view of the semiconductor device after the polycrystalline silicon film 25, N° diffusion layer 23 and P00 diffusion 24 have been formed. BPSG after being heat-treated in a neutral atmosphere to form a thin oxide 11!26.
II27 is formed by CVD method. Thereafter, as shown in FIG. 2(C), a region where a contact hole 28 is to be formed is patterned using a photoresist 29, and a BP is etched using a dry etching method.
The SG film 27 is etched to form a contact hole 28.

Next, the photoresist is removed and heat treatment is performed to taper the sides of the contact hole as shown in Figure 2(d).
Even if the wiring metal 30 is laminated as shown in FIG. 3(d), the wiring metal 30 will not be disconnected at the contact hole.

[The section that the invention is trying to solve! ] After forming the contact hole described in the conventional method, the heat treatment temperature for rounding the contact hole must be 900° C. or higher. This heat treatment at a temperature of 900° C. or higher causes the N9 diffusion layer and the P0 diffusion layer to be significantly diffused, which hinders the miniaturization of semiconductor devices. Particularly in metal oxide (MOS) semiconductors, it has been difficult to form a transistor with a channel length less than a certain length because the effective channel length of the transistor becomes short and there is a risk of deteriorating the characteristics of the transistor.

[Means for Solving the Problems 1] In order to solve the above problems, the present invention provides an insulating film between the eyebrows in which the first layer is a BPSG film and the second layer is a PSG film.
It has a layered structure. Thereafter, the PSG film is wet etched, and then the BPSG film is dry etched.

[Effect] By using wet etching in combination with dry etching, it is possible to create a gentle slope in the contact hole.
Disconnection of metal wiring can be eliminated without heat treatment at 900° C. or higher.

[Example] FIGS. 1(a) to 1(d) show a diffusion layer 3 with a high concentration of N-type impurities formed on a silicon substrate 1. FIG. 1(a) shows a cross-sectional view of the steps in the manufacturing method of a semiconductor device having a diffusion layer 4 heavily doped with P-type impurities and a polycrystalline silicon film 5 doped with heavily N-type impurities. Diffusion layer 3, P0
After forming the diffusion layer 4 and the polycrystalline silicon film 5,
Lightly oxidize polycrystalline silicon lI5 to silicon oxide 11I
form 6. The purpose of this silicon oxide film is to prevent the diffusion of boron (B) and phosphorus (P) from the BPSG film 7 formed on it, in addition to removing damage and contamination generated in previous processes. . After that, a boron phosphorus silicade glass or BPSG film 7
Laminate. This BPSGII is produced by chemical vapor deposition (CVD).
) A zero-order phosphosilicate glass, so-called PSGR'A8, formed by the method is laminated. This PSG film is also formed by the CVD method. The two-layer insulating film of the BPSG film 7 and the PSG film 8 described above becomes an interlayer insulating film that insulates the wirings from each other. After this, heat treatment is performed to densify the insulating film. A temperature of 800°C or higher is sufficient for this heat treatment, but for the purpose of reflowing for planarization, BPSG and PS
Although it depends on the impurity concentration of the G film, a temperature of 850° C. or higher is required. Further, heat treatment can also be performed after laminating the BPSG film 7.

Next, as shown in FIG. 1(b), a photoresist 9 is applied, and the photoresist film in the area where the contact hole is to be formed is selectively removed using the photolithography method. ) type wet etching solution, such as diluted HF diluted with water (Hyo0) or buffered acid (BHFJ) diluted with ammonium ammonium chloride (NH,F).
PSGli8 is etched using a liquid or the like. The etching rate of BPSGMi with the above etching solution is P
Since the etching speed is considerably slower than that of the SG film, PS
It is fully possible to etch all of the GII 8 and leave the BPSG film 7, even considering the variation in the thickness of the PSG film 8. For example, B (8 degrees 3 wt% and P7m1 degrees 5
wt% BPSG film and 8wt% (1') P8
6 P S Gll with degrees! The etching rate with Dono 115 diluted hydrochloric acid has a ratio of 15 or more, so the BPSG film 7
P in the area of contact hole 10 without excessively etching
SGil! All can be etched. Also, as explained above, since the etching selection ratio is very high, PSG
Etching can also be performed with an etching time calculated from the film thickness. As a method of increasing the ratio of etching speed between psc crots and BPSGII7, increasing the phosphorus (Pla content) in PSC1m and boron (
B) It is effective to increase the temperature by 1 degree. Also, BPSGl
After forming lI7, heat treatment is performed, and PSG at this heat treatment temperature
If the heat treatment after film formation is performed at a higher temperature than 1 degree, the etching rate of the PSG film 8 can be made much higher than that of the BPSGIli7.

When wet etching is performed as described above, the etching also proceeds in the lateral direction, so that the shape of the contact has a gentle taper as shown in FIG. 1(b).

Next, as shown in FIG. 1(C), the BPSG film 7 remaining in the area of the contact hole IO is etched using a dry etching method.
The contact hole 10 is completely opened by etching. If anisotropic etching is used for this dry etching, the contact hole 10 will be the same size as the hole drilled with photoresist.
Since it is possible to drill a moldy contact hole, it is possible to form a moldy contact hole. In the contact hole formed as described above, the upper part of the contact hole is smoothly tapered by wet etching, and the lower part of the contact hole is formed as a fine contact hole.

Therefore, even if a metal interconnection 4211 made of aluminum or the like is formed as shown in FIG. 1(d), the metal interconnection 11 will not be disconnected near the contact hole 10.

In Figure 1 (C), before dry etching, 20 minutes
Baking at a temperature below 0°C is also necessary to stabilize the process. Further, after dry etching the contact hole and removing the photoresist 9, heat treatment can be performed to remove damage and various types of contamination by dry etching, and it is also possible to slightly round the contact hole 1O.

[Effect of the invention 1] As explained above, this invention makes the living room insulating film a two-layer film of a BPSG film and a PSG film, and uses both wet etching and dry etching in etching the contact hole to form a smooth slope. It is possible to form a contact hole with a slope, and there is no problem of disconnection of the F2 wiring in the contact hole. Also, contact reflow, which is a heat treatment at a temperature of 900°C or higher, is not required, so N9 and P44 The extension of diffusion is eliminated, allowing the formation of finer semiconductor devices. Especially M
Even if the channel length of a transistor in an O5 semiconductor is shortened, source/drain diffusion does not spread and a stable transistor can be manufactured.

Step-by-step cross-sectional views showing the manufacturing method of FIG. 2 (a) to (d)
1A and 1B are step-by-step cross-sectional views showing a conventional method for manufacturing a semiconductor device.

1.21...Silicon substrate 2.22... Oxide film for element isolation 3.23...N4 diffusion layer (N" ion implantation layer) 4.24...P00 diffusion (P" ion implantation layer) 5.25...Polycrystalline silicon film 6.26...Silicon oxide film 7.27...BPSG! I! 8...PSG pus 9.29...Photoresist film 1O128...Contact hole 1m 3C1...A9 wiring

[Brief explanation of drawings]

that's all

Claims (1)

[Claims] (1) An interlayer insulating film that electrically insulates a region or wiring containing a high concentration of impurities and the wiring placed above it is formed by using a silicon oxide film containing boron and phosphorus as the lower layer and a silicon oxide film containing phosphorus as the upper layer. A step of forming a certain two-layer film, a step of etching the PSG film, which is the upper layer of the interlayer insulating film, with a hydrofluoric acid-based wet etching solution when forming a contact hole in the interlayer insulating film, and a dry etching step. A method for manufacturing a semiconductor device, comprising a step of etching a BPSG film which is a lower layer of an interlayer insulating film using a method.