JPH0828363B2 - Method for manufacturing semiconductor device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device improved to have high reliability.

[Conventional Technology] Semiconductor device technology has already entered the submicron range.
4M DRAM is about to be put into practical use with a design rule of about 0.8 μm. At the same time as device miniaturization, the device pattern has a complicated shape, the steps are remarkable, and the aspect ratio is increasing. At present, the level of planarization technology is extremely important.

8A to 8I are cross-sectional views showing a manufacturing process of a semiconductor device incorporating a conventional planarization technique.

Referring to FIG. 8A, semiconductor substrate 1, for example, a silicon semiconductor substrate is prepared. Next, referring to FIG. 8B, a silicon oxide film 2 to be a gate oxide film is formed on semiconductor substrate 1. A polysilicon layer 3 to be a gate electrode is formed on the silicon oxide film 2. next,
The polysilicon layer 3 is doped with phosphorus for increasing conductivity. Instead of doping with phosphorus,
Polysilicon doped with phosphorus or arsenic may be deposited on the silicon oxide film 2.

Next, referring to FIGS. 8B and 8C, the gate oxide film 4 and the gate electrode 5 are formed on the semiconductor substrate 1 by patterning the silicon oxide film 2 and the polysilicon layer 3 into a desired shape. To be done.

Next, referring to FIG. 8D, in order to form the source / drain regions 6 on the main surface of the semiconductor substrate 1, B ⁺ , P ⁺ or
As ⁺ impurity ions 7 are implanted into the main surface of the semiconductor substrate 1. The concentration of impurity ions is 1 to 5 × 10 ¹⁵ ions / cm ² .

After that, referring to FIG. 8E, the interlayer insulating film 8 made of a silicon oxide film containing impurities such as boron, phosphorus and arsenic is formed.
Are deposited on the semiconductor substrate 1 including the gate electrode 5. Next, referring to FIG. 8F, in order to flatten the surface of the interlayer insulating film 8, it is called reflow, 700 to 1000 ° C.
A heat treatment at a temperature of about a certain degree is performed. By this reflow,
The surface of the interlayer insulating film 8 is flattened.

Next, referring to FIG. 8G, a resist 9 is applied on the entire surface, and the resist 9 is patterned so that an opening is formed in the upper portion of the contact region to be formed. Next, by using the patterned resist 9 as a mask, the interlayer insulating film 8 is etched to form a contact hole 10 in the interlayer insulating film 8. After that, the resist 9 is removed.

Next, referring to FIG. 8H, in order to enhance the electrical conductivity of the contact region 11, impurity ions 12 such as B ⁺ , P ⁺ and As ⁺ are added.
Are implanted in the contact region 11.

Next, referring to FIG. 8I, a wiring pattern 13 is formed on the interlayer insulating film 8 via the contact hole 10 to electrically connect to the source / drain region 6.

The method described above is the most standard planarization technique for interlayer insulating films.

However, in the technique for flattening the interlayer insulating film thus performed, as shown in FIG. 8F, the concentration of impurities implanted in the interlayer insulating film 8 is high and the reflow temperature is also high. The impurity implanted in the film 8 diffuses into the gate electrode 5 and other wiring layers, which causes a problem in reliability.

In order to solve such a problem, JP-A-56-4814
Publication 0 discloses an improved technique for planarizing an interlayer insulating film shown in FIGS. 9A to 9F.

Referring to FIG. 9A, LOCOS oxide film 14, gate oxide film 4, gate electrode 5, and source / drain regions 6 are formed on the main surface of semiconductor substrate 1. Next, referring to FIG. 9B, a silicon oxide film 15 containing 4 mol% of phosphorus is formed on the entire surface of the semiconductor substrate 1.
a is deposited, and a silicon oxide film 15b containing 10 mol% of phosphorus is further deposited thereon. Thus, the silicon oxide film 15a
A thick insulating film 16 composed of the silicon oxide film 15b and the silicon oxide film 15b is formed. Then, referring to FIG. 9C, heat treatment is performed in a nitrogen atmosphere at 1000 ° C. for 30 minutes. This heat treatment is called reflow. By this reflow, the surface of the thick insulating film 16 is flattened.

Next, referring to FIGS. 9C and 9D, the thick insulating film 16 is etched to a predetermined thickness to form the interlayer insulating film 8 having a predetermined thickness from the thick insulating film 16. Then, the portion 17 damaged by the above etching is removed by etching using an acid such as boric acid, phosphoric acid, hydrofluoric acid or the like. After that, referring to FIG. 9E, a resist 9 is applied to the entire surface, and the resist 9 is patterned.

Next, referring to FIGS. 9E and 9F, using the patterned resist 9 as a mask, a contact hole 10 is provided in the interlayer insulating film 8 and a wiring pattern 13 is formed.

[Problems to be Solved by the Invention] According to the above-described improved technique, the concentration of impurities implanted into the insulating film 16 can be lowered and the reflow temperature can be lowered. However, even in the above-mentioned improved technique, a reflow process is always necessary to flatten the insulating film 16. Since the reflow is performed at a high temperature of 700 to 1000 ° C., the impurities implanted in the insulating film 16 diffuse to the wiring layer and the like to some extent. Therefore, even with this improved technique, it is not possible to completely prevent the impurities implanted in the insulating film 16 from thermally diffusing into the wiring layer or the like. Further, in this improved technique, referring to FIG. 9D, there is a disadvantage that the acid such as boric acid, phosphoric acid, hydrofluoric acid used for etching permeates and remains in the surface layer portion of the interlayer insulating film 8. It was
If the acid remains on the surface layer portion of the interlayer insulating film, the adhesion between the photoresist 9 and the interlayer insulating film 8 deteriorates, and the processing accuracy decreases, which is a problem.

Therefore, it is an object of the present invention to provide a semiconductor device manufacturing method improved so as to have high reliability.

[Means for Solving the Problem] The present invention provides an element formed in a concavo-convex pattern on a substrate and a flattened predetermined film thickness formed on the substrate so as to cover the element. A method for manufacturing a semiconductor device including an interlayer insulating film having the same. A silicon oxide film having a film thickness 1.5 times or more the predetermined film thickness and containing boron and phosphorus is deposited on the semiconductor substrate having the element having the concavo-convex pattern. Reflow the silicon oxide film. The silicon oxide film is etched back until it has the predetermined film thickness. After the above-mentioned etch back, the following (a), (b), (c) and (d) are formed on the surface of the obtained interlayer insulating film.
Perform a process selected from the group consisting of.

(A) Forming a thin film on the interlayer insulating film.

(B) Heat treating the surface of the interlayer insulating film at a temperature of 600 to 900 ° C.

(C) Treating the surface of the interlayer insulating film with plasma.

(D) Annealing the surface of the interlayer insulating film in the presence of O ₃ gas.

[Operation] According to the method of manufacturing a semiconductor device according to the present invention, a silicon oxide film having a thickness of 1.5 times or more of a predetermined film thickness and containing boron and phosphorus is formed on a semiconductor substrate having an element having an uneven pattern. Since the film is deposited, the recess is filled and the surface of the uppermost layer of the silicon oxide film is planarized. Furthermore, since this silicon oxide film is subjected to reflow processing,
The stepped portion on the surface of the silicon oxide film is further sufficiently flattened.

Further, after etching the silicon oxide film, the above (a), (b) and (c) are formed on the surface of the obtained interlayer insulating film.
A process selected from the group consisting of and (d) is performed. By this treatment, the surface of the interlayer insulating film is cleaned, the adhesion between the resist formed next and the interlayer insulating film is improved, and the processing accuracy of the subsequent steps is improved.

Embodiment An embodiment of the present invention will be described below with reference to the drawings.

Embodiment 1 FIGS. 1A to 1J are sectional views showing manufacturing steps of a semiconductor device according to a first embodiment of the present invention.

Referring to FIG. 1A, semiconductor substrate 1 such as a silicon semiconductor substrate is prepared. Next, referring to FIG. 1B, a silicon oxide film 2 to be a gate oxide film is formed on semiconductor substrate 1. A polysilicon layer 3 to be a gate electrode is formed on silicon oxide film 2. Next, the polysilicon layer 3 is doped with phosphorus for increasing conductivity. Instead of doping with phosphorus, polysilicon doped with phosphorus or arsenic may be deposited on the silicon oxide film 2.

Then, referring to FIG. 1C, the gate oxide film 4 and the gate electrode 5 are formed on the semiconductor substrate 1 by patterning the silicon oxide film 2 and the polysilicon layer 3 into a desired shape.

Next, referring to FIG. 1D, in order to form source / drain regions on the main surface of the semiconductor substrate 1, B ⁺ , P ⁺ or As is formed.
⁺ Impurity ions 40 are implanted into the main surface of semiconductor substrate 1.

Next, referring to FIG. 1E, a silicon oxide film 18 is formed on the semiconductor substrate 1 using TEOS (tetraethoxysilane) / O ₃ or S.
Deposition is carried out using atmospheric pressure or reduced pressure CVD method using iH ₄ / O ₂ . The film thickness of the silicon oxide film 18 is set to be equal to or more than the film thickness necessary for flattening the concavo-convex pattern such as the gate electrode 5 formed on the semiconductor substrate 1. This film thickness is about 1.5 times or more the film thickness required for the interlayer insulating film. When such a thick silicon oxide film 18 is deposited on the semiconductor substrate 1, the recesses are filled and the surface of the uppermost layer of the silicon oxide film 18 is flattened.

Although it is possible to form a contact hole in the state shown in FIG. 1F, the workability is poor because the contact hole becomes too deep. Therefore, referring to FIGS. 1E and 1F, the silicon oxide film 18 is formed into a desired film thickness (about 3000 to 80).
Etching (wet etching or dry etching) until it reaches 00Å). Then, a thin interlayer insulating film 19 having a desired film thickness is obtained. Since the surface of the silicon oxide film 18 has already been flattened, the surface of the interlayer insulating film 19 obtained by etching back the silicon oxide film 18 is also flattened. However, acid and moisture adhere to the surface of the interlayer insulating film 19 and permeate the surface layer portion thereof. The presence of this acid and water deteriorates the adhesion between the resist to be applied next and the interlayer insulating film 19. Therefore, referring to FIG. 1G, the interlayer insulating film
A new film 20 is formed on 19 to cover the acid and water. As the new film 20, a silicon oxide film, a silicon oxynitride film, a silicon nitride film, or a combination thereof is selected. Note that instead of forming a new film 20 on the interlayer insulating film 19, heat treatment is performed to remove moisture and acid adsorbed on the interlayer insulating film 19 and clean the surface of the interlayer insulating film 19. May be turned into. Further, the surface of the interlayer insulating film 19 is oxidized by O ₂ plasma and O ₃ annealing to remove the acid and moisture adsorbed on the surface of the interlayer insulating film 19.
The surface of may be cleaned.

Oxidation treatment with O ₂ plasma is significant when the interlayer insulating film 19 is formed between metals. This is because in such a case, high temperature heat treatment is impossible.

Next, referring to FIG. 1H, a resist 9 is formed on the interlayer insulating film 19 on which the new film 20 is formed. Interlayer insulation film 19
Since the surface of the is cleaned by the new film 20, the adhesion between the interlayer insulating film 19 and the resist 9 is improved, and the processing accuracy of the subsequent steps is improved. Next, the resist 9 is formed so that an opening is formed in a portion where a contact hole is to be formed.
Pattern.

Next, referring to FIGS. 1H and 1I, the interlayer insulating film 19 is etched using the patterned resist 9 as a mask. Then, the contact hole is formed in the interlayer insulating film 19.
10 are formed. Next, the resist 9 is removed. After the resist 9 is removed, phosphorus or boron ions 12 are implanted in the contact region.

Thereafter, referring to FIG. 1J, an aluminum wiring pattern 13 is formed on interlayer insulating film 19 including contact hole 10. The aluminum wiring pattern 13 is electrically connected to the source / drain region 6 of the transistor through the contact hole 10. As described above, in this embodiment,
Referring to FIG. 1E, impurity ions are not implanted in silicon oxide film 18. Further, high temperature heat treatment called reflow is not performed. Therefore, when flattening the interlayer insulating film, the situation that the impurity ions diffuse into the gate electrode 5 observed in the prior art is avoided. Therefore, a highly reliable semiconductor device can be obtained.

Embodiment 2 FIGS. 2A to 2G are sectional views showing manufacturing steps of a semiconductor device according to a second embodiment of the present invention.

First, the steps shown in FIGS. 1A to 1D are performed. Next, referring to FIG. 2A, a silicon oxide film 22 containing at least one kind of impurities such as boron, phosphorus and arsenic is deposited on the semiconductor substrate 1. Impurity concentration is 10mo each
Selected below l%. The film thickness of the silicon oxide film 22 is set to be equal to or larger than the film thickness required for flattening the uneven pattern of the gate electrode 5 formed on the semiconductor substrate 1. This film thickness is about 1.5 times or more the film thickness required for the interlayer insulating film. As described above, when the thick silicon oxide film 18 is deposited on the semiconductor substrate, the recess is filled and the surface of the uppermost layer of the silicon oxide film 18 is flattened.

Next, referring to FIG. 2B, the step portion of the surface of the silicon oxide film 22 is sufficiently flattened by subjecting the silicon oxide film 22 to a heat treatment called so-called reflow, and at the same time, the silicon oxide film 22 is The product itself is baked.
Since the silicon oxide film 22 is considerably thick, a low reflow temperature of about 600 to 900 ° C. is sufficient. Well, the first
It may be possible to form a contact hole in the state shown in FIG. 2B, but the contact hole becomes too deep, resulting in poor workability. Therefore, referring to FIGS. 2B and 2C, the silicon oxide film 18 is etched (wet etching with hydrofluoric acid or anisotropic dry etching) until a desired film thickness (about 3000 to 8000Å) is reached. . Then, a thin interlayer insulating film 19 having a desired film thickness is obtained. Since the silicon oxide film 22 is sufficiently flattened as described above, the surface of the interlayer insulating film 19 obtained by etching back the silicon oxide film 22 is also sufficiently flattened. Also, although reflow is applied,
Since this reflow is performed at a low temperature of about 600 to 900 ° C., impurities introduced into the silicon oxide film 22 are
It becomes difficult to diffuse into the gate electrode 5 and the like.

By the way, on the surface of the interlayer insulating film 19, acid and water used in the etching process adhere and soak into the surface layer portion thereof. The acid and water deteriorate the adhesion between the resist that will be applied next and the interlayer insulating film 19.
Therefore, referring to FIG. 2D, a new film 20 is formed on the interlayer insulating film 19 to cover the acid, moisture and the like. A new film 20 is formed on the interlayer insulating film 19 in the same manner as described in the first embodiment.
Instead of being formed on the interlayer insulating film 19, heat treatment at 600 to 900 ° C. may be performed to remove moisture and acid adsorbed on the interlayer insulating film 19 to clean the surface of the interlayer insulating film 19. Further, similarly to the first embodiment, the surface of the interlayer insulating film 19 may be oxidized by O ₂ plasma and O ₃ annealing to remove the acid and water adsorbed on the surface.

The effect of cleaning the surface of the interlayer insulating film 19 by heat treatment at 600 to 900 ° C. will be described with reference to FIG. In FIG. 3, the horizontal axis X represents the film thickness of the silicon oxide film, and the vertical axis Y represents the boron concentration. Point A represents the surface of the silicon oxide film 22 after reflow, and point B represents the surface of the interlayer insulating film 19 after etching. A curve 23 represents the profile of the boron concentration from the surface of the silicon oxide film 22 in the direction of arrow 25 with reference to FIG. 2B. The curve 24 indicates the arrow 26 when the interlayer insulating film 19 is heat-treated with reference to FIG. 2D.
The profile of the boron concentration over the direction is shown. Now, referring to curve 24, by performing the heat treatment on interlayer insulating film 19, the boron concentration is reduced in the surface layer portion thereof. Therefore, boron hardly diffuses into the wiring layer to be formed later. As a result, the reliability of the semiconductor device is improved.

Next, returning to FIG. 2E, a resist 9 is formed on the interlayer insulating film 19 on which the new film 20 is formed. Since the surface of the interlayer insulating film 19 is cleaned by the new film 20, the adhesion between the interlayer insulating film 19 and the resist 9 is improved, and therefore the processing accuracy of the subsequent steps is improved. Next, so that the opening is formed in the portion where the contact hole is to be formed,
The resist 9 is patterned.

Next, referring to FIGS. 2E and 2F, the contact hole 10 is formed by etching the interlayer insulating film 19 using the patterned resist 9 as a mask. After that, the resist 9 is removed. After the resist 9 is removed, phosphorus or boron ions 12 are implanted in the contact region 11.

Next, referring to FIG. 2G, an aluminum wiring pattern 13 is formed on the interlayer insulating film 19 including the contact holes 10.
The aluminum wiring pattern 13 is electrically connected to the source / drain region 6 of the transistor through the contact hole 10. Further, according to this embodiment, referring to FIG. 2G, since the film 20 which is a barrier layer is formed between the interlayer insulating film 19 and the aluminum wiring pattern 13, it is included in the interlayer insulating film 19. Boron does not diffuse into the aluminum wiring pattern 13. Therefore, the reliability of the semiconductor device is further improved.

Embodiment 3 FIGS. 4A to 4G show a third embodiment of the present invention.

First, the steps shown in FIGS. 1A to 1D are performed. Next, referring to FIG. 4A, a thin silicon oxide film 27 is formed on the semiconductor substrate 1 including the gate electrode 5. Next, on the semiconductor substrate 1, a silicon oxide film 22 containing at least one impurity such as boron, phosphorus or arsenic is deposited. The concentration of impurities is selected to be 10 mol% or less. The film thickness of the silicon oxide film 22 is set to be equal to or larger than the film thickness required for flattening the uneven pattern of the gate electrode 5 formed on the semiconductor substrate 1. This film thickness is about 1.5 times or more the film thickness required for the interlayer insulating film. This thick silicon oxide film 18
Is deposited on the semiconductor substrate 1, the recess is filled, and the surface of the uppermost layer of the silicon oxide film 22 is flattened.

Next, referring to FIG. 4B, the step portion on the surface of the silicon oxide film 22 is sufficiently flattened by subjecting the silicon oxide film 22 to a heat treatment called so-called reflow, and at the same time, the silicon oxide film 22 is The itself is also baked.
Since the silicon oxide film 22 has a large film thickness, a low temperature of about 600 to 900 ° C. is sufficient for the heat treatment.

Although it is possible to form a contact hole in the state of FIG. 4B, the workability is poor because the contact hole becomes too deep. Therefore, referring to FIGS. 4B and 4C, the silicon oxide film 22 is formed into a desired film thickness (about 3000 to 80).
Etching (wet etching or dry etching) until it reaches 00Å). Then, a thin interlayer insulating film 19 having a desired film thickness is obtained. Since the surface of the silicon oxide film 22 is flattened, the surface of the interlayer insulating film 19 obtained by etching this is also flattened. However, acid and moisture adhere to the surface of the interlayer insulating film 19 and soak into the surface layer portion thereof. The presence of this acid and water deteriorates the adhesion between the resist that will be applied next and the interlayer insulating film 19. Therefore, referring to FIG. 4D, a new film 20 is formed on the interlayer insulating film 19 to cover the acid and the water. Instead of forming a new film 20 on the interlayer insulating film 19, heat treatment is performed to remove moisture and acid adsorbed on the interlayer insulating film 19 and clean the surface of the interlayer insulating film 19. May be turned into. Further, the surface of the interlayer insulating film 19, O ₂
The acid and water adsorbed on the surface may be removed by oxidation by plasma or O ₃ annealing.

Next, referring to FIG. 4E, a resist 9 is formed on the interlayer insulating film 19 on which the new film 20 is formed. Interlayer insulation film 19
Since the surface of the is cleaned by the new film 20, the adhesion between the interlayer insulating film 19 and the resist 9 is improved, and the processing accuracy of the subsequent steps is improved. Next, the resist 9 is formed so that an opening is formed in a portion where a contact hole is to be formed.
Pattern.

Next, referring to FIGS. 4E and 4F, the contact hole 10 is formed by etching the interlayer insulating film 19 using the patterned resist 9 as a mask. After that, the resist 9 is removed. After the resist 9 is removed, phosphorus or boron ions 12 are implanted in the contact region 11.

Next, referring to FIG. 4G, an aluminum wiring pattern 13 is formed on the interlayer insulating film 19 including the contact holes 10.
The aluminum wiring pattern 13 is electrically connected to the source / drain region 6 of the transistor through the contact hole 10.

As described above, in this embodiment, referring to FIG. 4A, since the thin silicon oxide film 27 is formed on the semiconductor substrate 1 including the gate electrode 5, it is included in the silicon oxide film 22. Impurity ions present are blocked by the thin silicon oxide film 27 and are not diffused into the gate electrode 5 and the source / drain regions 6. As a result, the reliability of the semiconductor device is further improved.

Embodiment 4 FIGS. 5A to 5F show a fourth embodiment of the present invention.

First, the steps shown in FIGS. 1A to 1D are performed. Next, referring to FIG. 5A, a thin silicon oxide film 27 is formed on the semiconductor substrate 1 including the gate electrode 5. Then, a silicon oxide film 18 is deposited on the semiconductor substrate 1. The silicon oxide film 18 contains no impurities. The film thickness of the silicon oxide film 18 is set to be equal to or more than the film thickness required for flattening the uneven pattern of the gate electrode 5 formed on the semiconductor substrate 1. This film thickness is about the thickness required for the interlayer insulating film.
It is more than 1.5 times. When the thick silicon oxide film 18 is deposited on the semiconductor substrate 1 as described above, the recesses are filled and the steps on the surface of the uppermost layer of the silicon oxide film 18 are flattened.

It may be possible to form a contact hole in the state shown in FIG. 5A, but the workability is poor because the contact hole becomes too deep. Therefore, referring to FIGS. 5A and 5B, the silicon oxide film 18 is formed into a desired film thickness (about 3000 to 8000Å).
Etching (wet etching or dry etching). Then, a thin interlayer insulating film 19 having a desired film thickness is obtained. Since the surface of the silicon oxide film 18 is flattened, the surface of the interlayer insulating film 19 obtained by etching the silicon oxide film 18 is also flattened. However, the interlayer insulation film
Acid and moisture adhere to the surface of 19, and these penetrate into the surface layer. This acid and water deteriorate the adhesion between the resist that will be applied next and the interlayer insulating film 19. Therefore, referring to FIG. 5C, a new film 20 is formed on the interlayer insulating film 19 to cover the acid and the water. Note that instead of forming a new film 20 on the interlayer insulating film 19, heat treatment is performed to remove moisture and acid adsorbed on the interlayer insulating film 19 and clean the surface of the interlayer insulating film 19. May be turned into. Alternatively, the surface of the interlayer insulating film 19 may be oxidized by O ₂ plasma or O ₃ annealing to remove the acid and water adsorbed on the surface. Next, referring to FIG. 5D, a resist 9 is formed on the interlayer insulating film 19 on which the new film 20 is formed. Interlayer insulation film
Since the surface of 19 has been cleaned by the new membrane 20,
The adhesion between the interlayer insulating film 19 and the resist 9 is improved, and the processing accuracy in the subsequent steps is improved. Next, the resist 9 is patterned so that an opening is formed in a portion where a contact hole is to be formed.

Next, referring to FIGS. 5D and 5E, contact hole 10 is formed by etching interlayer insulating film 19 using patterned resist 9 as a mask. After that, the resist 9 is removed. After the resist 9 is removed, phosphorus or boron ions 12 are implanted in the contact region 11.

Next, referring to FIG. 5F, an aluminum wiring pattern 13 is formed on the interlayer insulating film 19 including the contact holes 10.
The aluminum wiring pattern 13 is electrically connected to the source / drain region 6 of the transistor through the contact hole 10.

In this embodiment, referring to FIG. 5A, a thin silicon oxide film 27 is formed on semiconductor substrate 1 including gate electrode 5. Further, no impurities are implanted into the thick silicon oxide film 18. In addition, no reflow process is performed. Therefore, the gate electrode 5 and the source / drain region 6
Impurities are not diffused into.

Fifth Embodiment FIGS. 6A to 6Q are a fifth embodiment in which the present invention is applied to a method of manufacturing a semiconductor device having a multilayer wiring structure.

Referring to FIG. 6A, semiconductor substrate 1 such as a silicon semiconductor substrate is prepared. Next, referring to FIG. 6B, a silicon oxide film 2 to be a gate oxide film is formed on semiconductor substrate 1. A polysilicon layer 3 to be a gate electrode is formed on the silicon oxide film 2. Next, the polysilicon layer 3 is doped with phosphorus for increasing conductivity. Instead of doping with phosphorus, polysilicon doped with phosphorus or arsenic may be deposited on the silicon oxide film 2.

Next, referring to FIGS. 6B and 6C, the gate oxide film 4 and the gate electrode 5 are formed on the semiconductor substrate 1 by patterning the silicon oxide film 2 and the polysilicon layer 3 into a desired shape. It is formed.

Next, referring to FIG. 6D, in order to form the source / drain regions 6 on the main surface of the semiconductor substrate 1, B ⁺ , P ⁺ or
As ⁺ impurity ions 40 are implanted into the main surface of the semiconductor substrate 1.

Next, referring to FIG. 6E, on the semiconductor substrate 1, boron,
A silicon oxide film 22 containing at least one impurity such as phosphorus or arsenic is deposited. The concentration of impurities is 10mo each
Selected below l%. The film thickness of the silicon oxide film 22 is set to be equal to or larger than the film thickness required for flattening the uneven pattern of the gate electrode 5 formed on the semiconductor substrate 1. This film thickness is about 1.5 times or more the film thickness required for the interlayer insulating film. When the thick silicon oxide film 22 is deposited on the semiconductor substrate 1 as described above, the concave portion is filled and the step portion of the uppermost layer portion of the silicon oxide film 22 is flattened.

Next, referring to FIG. 6F, the silicon oxide film 22 is subjected to a heat treatment called so-called reflow so that the step portion on the surface of the silicon oxide film 22 is sufficiently flattened and the silicon oxide film 22 itself. Is toasted. As the temperature for the heat treatment, a low temperature of about 600 to 900 ° C. is sufficient because the silicon oxide film 22 is considerably thick.

Although it is possible to form a contact hole in the state shown in FIG. 6F, the workability is poor because the contact hole becomes too deep. Therefore, referring to FIGS. 6F and 6G, the silicon oxide film 22 is formed into a desired film thickness (about 3000 to 80).
Etching (wet etching or dry etching) until it reaches 00Å). Then, a thin interlayer insulating film 19 having a desired film thickness is obtained. Since the surface of the silicon oxide film 22 is flattened, the surface of the multilayer insulating film 19 obtained by etching this is also flattened. However, acid and moisture adhere to the surface of the interlayer insulating film 19, and these penetrate into the surface layer portion of the interlayer insulating film 19. This acid and water deteriorate the adhesion between the resist that will be applied next and the interlayer insulating film 19. Therefore, referring to FIG. 6G, a new film 20 is formed on the interlayer insulating film 19 to cover the acid and the water. Note that instead of forming a new film on the interlayer insulating film 19, heat treatment is performed to remove moisture and acid adsorbed on the interlayer insulating film 19.
The surface of may be cleaned. Alternatively, the surface of the interlayer insulating film 19 may be oxidized by O ₂ plasma or O ₃ annealing to remove the acid and water adsorbed on the surface.

Next, referring to FIG. 6H, a resist 9 is formed on the interlayer insulating film 19 on which the new film 20 is formed. Interlayer insulation film 19
Since the surface of is cleaned by a new film, the adhesion between the interlayer insulating film 19 and the resist 9 is improved, and the processing accuracy thereafter is improved. Next, the resist 9 is patterned so that an opening is formed in a portion where a contact hole is to be formed.

Next, referring to FIGS. 6H and 6I, contact hole 10 is formed by etching interlayer insulating film 19 using patterned resist 9 as a mask. After that, the resist 9 is removed. After removing the resist 9, phosphorus or boron ions are implanted into the contact region 11.

Next, referring to FIG. 6I, an aluminum wiring layer 28 is formed on the interlayer insulating film 19 including the contact holes 10.

Next, referring to FIG. 6J, the aluminum wiring pattern 13 is patterned into a desired shape to form an aluminum wiring pattern 13.

Next, referring to FIG. 6K, a silicon oxide film 29 is formed on the semiconductor substrate 1 including the aluminum wiring pattern 13.

Next, referring to FIG. 6L, a silicon oxide film 18 is deposited on the semiconductor substrate 1. Impurity ions are not contained in the silicon oxide film 18. The thickness of the silicon oxide film 18 is
The film thickness is set to be equal to or larger than the film thickness required to flatten the uneven pattern of the aluminum wiring pattern 13. This film thickness is about 1.5 times or more the film thickness required for the interlayer insulating film. When such a thick silicon oxide film 18 is deposited on the semiconductor substrate, the recesses are filled and the steps on the surface of the uppermost layer of the silicon oxide film 18 are flattened.

Although it is possible to form a through hole in the state shown in Fig. 6L, the workability is poor because the through hole becomes too deep. Therefore, referring to FIGS. 6L and 6M, the silicon oxide film 18 is etched (wet etching or dry etching) until a desired film thickness (about 3000 to 8000 Å) is reached. Then, a thin interlayer insulating film 30 having a desired film thickness is obtained. Since the surface of the silicon oxide film 18 is flattened, an interlayer insulating film obtained by etching this
The surface of 30 is also flattened. However, acid and moisture adhere to the surface of the interlayer insulating film 30, and these penetrate into the surface layer portion of the interlayer insulating film 30. The acid and water deteriorate the adhesion between the resist that will be applied next and the interlayer insulating film 30. Therefore, referring to FIG. 6N, the interlayer insulating film 30
A new film 31 is formed on the top surface to cover the acid and water. Note that instead of forming a new film 31 on the interlayer insulating film 30, heat treatment is performed to remove moisture and acid adsorbed on the interlayer insulating film 30 to clean the surface of the interlayer insulating film 30. May be turned into. Further, the surface of the interlayer insulating film 30 O ₂
The acid and water adsorbed on the surface may be removed by oxidation by plasma or O ₃ annealing.

Next, referring to FIG. 60, a resist 32 is formed on the interlayer insulating film 30 on which the new film 31 is formed. Interlayer insulation film 30
Since the surface of is cleaned by the new film 31, the adhesion between the interlayer insulating film 30 and the resist 32 is improved, and the processing accuracy in the subsequent steps is improved. Next, the resist 32 is patterned so that an opening is formed in a portion where a through hole is to be formed.

Next, referring to FIG. 60 and FIG. 6P, through holes 33 are formed by etching interlayer insulating film 30 using patterned resist 32 as a mask.

Next, referring to FIG. 6Q, an aluminum wiring pattern 34 is formed on the interlayer insulating film 30 including the through holes 33. The aluminum wiring pattern 34 is electrically connected to the aluminum wiring pattern 13 via the through hole 33.

Also in this embodiment, when flattening the interlayer insulating films 19 and 30, the diffusion of impurity ions into the wiring layer itself is avoided, and a highly reliable semiconductor device can be obtained.

Sixth Embodiment FIGS. 7A to 7F show a sixth embodiment in which the present invention is applied to a method of manufacturing a semiconductor device having a multilayer wiring structure.

First, the steps shown in FIGS. 6A to 6K are performed. Next, referring to FIG. 7A, a silicon oxide film 18 is deposited on the semiconductor substrate 1. Impurities are not contained in the silicon oxide film 18. The film thickness of the silicon oxide film 18 is set to be equal to or larger than the film thickness required for flattening the uneven pattern of the aluminum wiring pattern 13. This film thickness is about 1.5 times or more the film thickness required for the interlayer insulating film. When the thick silicon oxide film 18 is deposited on the semiconductor substrate 1 as described above, the concave portion is filled and the stepped portion on the surface of the upper layer portion of the silicon oxide film 18 is flattened.

Next, referring to FIG. 7B, the silicon oxide film 18 is etched until the flat portion 29a of the silicon oxide film 29 is exposed. As a result, the concave portion of the aluminum wiring pattern 13 is filled with the silicon oxide film 18 and planarized. Next, 7C
Referring to the figure, the silicon oxide film 3 is formed by the plasma CVD method.
5 is deposited on the entire surface of the semiconductor substrate 1 to a thickness of 1000 to 3000Å. Next, referring to FIG. 7D, a resist 9 is formed on the silicon oxide film 35. The surface of the silicon oxide film 35 formed by the plasma CVD method is beautiful. Therefore, the adhesion between the silicon oxide film 35 and the resist 9 is great. Next, the resist 9 is patterned so that an opening is formed in a portion where a through hole is to be formed.

Next, referring to FIGS. 7D and 7E, through holes 33 are formed by etching silicon oxide film 35 using patterned resist 9 as a mask.

Next, referring to FIG. 7F, an aluminum wiring pattern 34 is formed on the silicon oxide film 35 including the through holes 33.
The aluminum wiring pattern 34 is electrically connected to the aluminum wiring pattern 13 through the through hole 33.

Even in the above-described embodiment, since the impurity ions do not diffuse into the wiring layer or the like when the interlayer insulating film is flattened, a highly reliable semiconductor device can be obtained.

[Effects of the Invention] As described above, according to the present invention, a semiconductor substrate having an element having a concavo-convex pattern has a film thickness of 1.5 times or more the film thickness required as an interlayer insulating film, and Since the silicon oxide film containing boron and phosphorus is deposited, the recess is filled and the surface of the uppermost layer of the silicon oxide film is flattened. Further, the silicon oxide film is subjected to a reflow process, whereby the stepped portion on the surface of the silicon oxide film is further flattened. Further, since the surface of the interlayer insulating film is cleaned, the adhesion between the interlayer insulating film and the resist to be formed next is improved, and the processing accuracy in the subsequent steps is improved. As a result, there is an effect that a highly reliable semiconductor device can be obtained.

[Brief description of drawings]

1A to 1J are sectional views showing steps of a method for manufacturing a semiconductor device according to the first embodiment of the present invention. 2A to 2G are sectional views showing steps of the method for manufacturing a semiconductor device according to the second embodiment of the present invention. FIG. 3 shows the profile of the boron concentration in the silicon oxide film in FIGS. 2B and 2D. 4A to 4G are cross-sectional views of the steps of the method for manufacturing a semiconductor device according to the third embodiment of the present invention. 5A to 5F are sectional views showing steps of the method for manufacturing a semiconductor device according to the fourth embodiment of the present invention. 6A to 6Q are sectional views of the steps of the fifth embodiment in which the present invention is applied to the method for manufacturing a semiconductor device having a multilayer wiring structure. 7A to 7F are sectional views of the steps of the sixth embodiment in which the present invention is applied to the method for manufacturing a semiconductor device having a multilayer wiring structure. 8A to 8I are cross-sectional views of steps of the method for manufacturing a semiconductor device according to the first conventional example. 9A to 9F are cross-sectional views of the steps of the method for manufacturing a semiconductor device according to the second conventional example. In the figure, 1 is a semiconductor substrate, 4 is a gate oxide film, 5 is a gate electrode, 6 is a source / drain region, 10 is a contact hole, 13 is a wiring pattern, 18 is a silicon oxide film, 19
Is an interlayer insulating film. In each drawing, the same reference numerals indicate the same or corresponding parts.

 ─────────────────────────────────────────────────── --- Continued from the front page (56) References JP-A-57-43433 (JP, A) JP-A-58-176950 (JP, A) JP-A-57-143846 (JP, A) JP-A 61- 206242 (JP, A)

Claims (1)

[Claims] 1. A semiconductor including an element formed in a concavo-convex pattern on a substrate, and a flattened interlayer insulating film formed on the substrate so as to cover the element. A method of manufacturing a device, comprising the step of depositing a silicon oxide film containing boron and phosphorus, which has a film thickness 1.5 times or more the predetermined film thickness, on a semiconductor substrate having the elements of the concavo-convex pattern. A step of reflowing the silicon oxide film, a step of etching back the silicon oxide film to the predetermined film thickness, and a step of etching back the surface of the obtained interlayer insulating film,
A method of manufacturing a semiconductor device, wherein a process selected from the group consisting of the following (a), (b), (c) and (d) is performed. (A) Forming a thin film on the interlayer insulating film. (B) Heat treating the surface of the interlayer insulating film at a temperature of 600 to 900 ° C. (C) Treating the surface of the interlayer insulating film with plasma. (D) Annealing the surface of the interlayer insulating film in the presence of O ₃ gas.