JPS57143846A - Formation of multi-layer wiring compostion - Google Patents

Formation of multi-layer wiring compostion

Info

Publication number
JPS57143846A
JPS57143846A JP2777781A JP2777781A JPS57143846A JP S57143846 A JPS57143846 A JP S57143846A JP 2777781 A JP2777781 A JP 2777781A JP 2777781 A JP2777781 A JP 2777781A JP S57143846 A JPS57143846 A JP S57143846A
Authority
JP
Japan
Prior art keywords
layer
insulation film
flat
wiring
thickness
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2777781A
Other languages
Japanese (ja)
Inventor
Hiroshi Goto
Hiroshi Tokunaga
Ryoji Abe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP2777781A priority Critical patent/JPS57143846A/en
Publication of JPS57143846A publication Critical patent/JPS57143846A/en
Pending legal-status Critical Current

Links

Landscapes

  • Magnetic Heads (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To make layer insulation film flat by a method wherein the layer insulation film is formed to the thickness more than approximately two times of the minimum interval of electrode wiring by vapor phase growth to make its surface flat, then the layer insulation film is etched from the surface. CONSTITUTION:Wiring 2 of the first layer is formed on an Si substrate on which insulation film is formed and PSG film 3 is formed on the whole surface by vapor phase growth. With the growth of the PSG film, the difference in level along the cross sectional shape of the first layer wiring is relieved and the surface of the insulation film becomes almost flat after the growth reaches to the thickness approximately two times of the interval of the first layer wiring. After that the surface is etched to the specified thickness more uniformly by isotropic etching such as ion milling or reactive sputter etching, so that the flat layer insulation layer of the specified thickness can be obtained.
JP2777781A 1981-02-27 1981-02-27 Formation of multi-layer wiring compostion Pending JPS57143846A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2777781A JPS57143846A (en) 1981-02-27 1981-02-27 Formation of multi-layer wiring compostion

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2777781A JPS57143846A (en) 1981-02-27 1981-02-27 Formation of multi-layer wiring compostion

Publications (1)

Publication Number Publication Date
JPS57143846A true JPS57143846A (en) 1982-09-06

Family

ID=12230397

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2777781A Pending JPS57143846A (en) 1981-02-27 1981-02-27 Formation of multi-layer wiring compostion

Country Status (1)

Country Link
JP (1) JPS57143846A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60229349A (en) * 1984-04-27 1985-11-14 Nec Corp Formation of internal wiring of semiconductor device
JPS63122269A (en) * 1986-11-12 1988-05-26 Nec Corp Manufacture of semiconductor integrated circuit
JPH0256933A (en) * 1988-05-18 1990-02-26 Mitsubishi Electric Corp Manufacture of semiconductor device

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5094892A (en) * 1973-12-22 1975-07-28
JPS5444482A (en) * 1977-09-14 1979-04-07 Matsushita Electric Ind Co Ltd Mos type semiconductor device and its manufacture
JPS5511354A (en) * 1978-07-12 1980-01-26 Chiyou Lsi Gijutsu Kenkyu Kumiai Manufacture of semiconductor

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5094892A (en) * 1973-12-22 1975-07-28
JPS5444482A (en) * 1977-09-14 1979-04-07 Matsushita Electric Ind Co Ltd Mos type semiconductor device and its manufacture
JPS5511354A (en) * 1978-07-12 1980-01-26 Chiyou Lsi Gijutsu Kenkyu Kumiai Manufacture of semiconductor

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60229349A (en) * 1984-04-27 1985-11-14 Nec Corp Formation of internal wiring of semiconductor device
JPS63122269A (en) * 1986-11-12 1988-05-26 Nec Corp Manufacture of semiconductor integrated circuit
JPH0256933A (en) * 1988-05-18 1990-02-26 Mitsubishi Electric Corp Manufacture of semiconductor device

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