JPS63260050A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent disconnection and shorting of a metallic wiring which is formed on a layer insulation film, by providing the layer insulation film with ion implantation to form a difference in the doping amount between a flat surface of the layer insulation and its inclined surface and next by utilizing an etching speed difference based on a concentration difference of the doping amount to flatten the surface by wet etching. CONSTITUTION:A layer insulation film 4 is formed on a MOS transistor whose source and drain are formed on a silicon substrate 2 by impurity diffusion. Next the whole surface is provided with ion implantation of phosphorus. Thereupon, the concentration of phosphorus implantation is high at a flat part of the layer insulation film 4 and low at an inclined surface of its recessed part. In succession, when the layer insulation film 4 is etched with a solution of hydrofluoric acid, the flat part of highly concentrated phosphorus implantation is etched in a great degree and the inclined part is etched in a small degree, and hence the layer insulation film 4 remains in the form of side walls of a gate electrode 8 and a field oxidizing film 10, and so the surface becomes smooth in its recessed and projected degrees. Thereafter, a PSG film 12 with a prescribed concentration of phosphorus is formed on the remaining layer insulation film 4a by a CVD method. This layer insulation film, whose surface is relaxed in its unevenness and flattened, can be formed accordingly.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a method of manufacturing a semiconductor device including a step of planarizing the surface of an interlayer insulating film.

(Prior art) When an interlayer insulating film is formed by vapor phase growth (CVD) on elements such as MOS transistors, wiring, etc., the surface of the interlayer insulating film becomes uneven, reflecting the unevenness of the underlying elements and wiring. appear. Metal wiring is further formed on the interlayer insulation film, but if the surface of the interlayer insulation film has large irregularities, the wiring formed on top of it may become constricted or disconnected, resulting in poor reliability. decreases.

Therefore, various methods have been tried to planarize the surface of the interlayer insulating film.

An example of a planarization method is to reflow the interlayer insulating film by heat treatment. However, with the miniaturization of semiconductor devices, low-temperature processing is performed, but the flow does not occur sufficiently, resulting in insufficient planarization and no improvement in reliability.

(Objective) An object of the present invention is to provide a method for planarizing the surface of an interlayer insulating film in order to improve the reliability of a semiconductor device.

(Structure) In the present invention, the interlayer insulating film once formed is etched back. At this time, ions that increase the etching rate are implanted into the interlayer insulating film, and the surface of the interlayer insulating film is flattened by utilizing the difference in etching rate due to the difference in the doping amount of the implanted ions.

In addition to the SiO:: film, the interlayer insulating film is PSG (Phosph), which is a phosphorus-doped 5iO film.

BSG (Boro-Si) film, which is a boron-doped Sin film;
licat, e Glass) film, Si3N4 film, etc. are used. These interlayer insulating films are formed by the CVD method.

On the other hand, it is known that in PSG films and BSG films, the etching rate of the etching solution increases as the amount of phosphorus or boron doped increases (Japanese Unexamined Patent Publication No. 58-13
(See Publication No. 1).

The PSG film or BSG film may be one in which phosphorus or boron is implanted into the 5iC)2 film by ion implantation, or may be grown as a PSG film or BSG film by CVD.

Examples will be specifically described below.

As shown in FIG. 1, an interlayer insulating film 4 is formed on a MOS transistor whose source and drain are formed in a silicon substrate 2 by impurity diffusion. Here, 6 is a gate oxide film, 8 is a gate electrode, and 10 is a field oxide film formed by the LOCO8 method for element isolation. The interlayer insulating film 4 is 5 iOz containing no impurities or a low concentration of impurities. For example, phosphorus is used as the impurity, and its concentration is 0 to 5% by weight. Usually, the phosphorus concentration of a PSG film used as an interlayer insulating film is 5 to 10% by weight.

In the figure, since the gate electrode 8 and the field oxide film 10 are raised on the surface of the silicon substrate 2, the surface of the interlayer insulating film 4 is depressed in the area between the gate electrode 8 and the field oxide film 10, and unevenness occurs on the surface. are doing.

Next, phosphorus ions are implanted into the entire surface. By this ion implantation, phosphorus is implanted at a high concentration into the flat portion of the interlayer insulating film 4, and phosphorus is implanted only at a low concentration into the sloped surface of the recess. The amount of phosphorus injected at this time is 1 normal PSG
The concentration is about 5 to 10% by weight, which is the concentration of the film.

Next, heat treatment is applied to activate the implanted phosphorus and to flatten the surface of the interlayer insulating film 4 to some extent by reflow.

Next, as shown in FIG. 2, the interlayer insulating film 4 is etched with an etching solution until the thickness becomes about 1/10 to 1/2. The etching solution is hydrofluoric acid (HF).
In the diagram using a solution, the symbol 4a indicates the interlayer insulating film remaining after etching, and the symbol 4b indicates the etched interlayer insulating film.

In this etching process, the flat areas where phosphorus is implanted at a high concentration are etched to a large extent, and the sloped areas are etched less, so that the interlayer insulating film 4 remains in the form of sidewalls of the gate electrode 8 and the field oxide film 10. The surface unevenness becomes gentle.

After that, as shown in FIG. 3, the remaining interlayer insulating film 4a
A single PSG film with a predetermined phosphorus concentration is formed thereon by a 2VD method until the required thickness is reached.

As a result, surface irregularities are alleviated and a flattened interlayer insulating film is formed.

After that, contact holes are formed according to the normal process, and a fully bent wiring is formed.

In the embodiment, phosphorus is implanted into the interlayer insulating film, but boron can also be used.

(Effect) In the present invention, ions are implanted into the interlayer insulating film to create a difference in the doping amount between the flat surface and the inclined surface of the interlayer insulating film, and wet etching is performed to etching the surface by utilizing the difference in etching speed due to the difference in concentration of the doping amount. By flattening the interlayer insulation film and then forming an interlayer insulation film to obtain a flattened interlayer insulation film, it is possible to prevent disconnections and short circuits in the fully bent wiring formed on one interlayer insulation film, thereby increasing reliability. Improves sex. And it becomes easy to form multilayer metal wiring.

Compared to the conventional method of simply reflowing and flattening the interlayer insulating film through high-temperature treatment, the reflow process may not be sufficient, so reflow can be performed at a low temperature, making it possible to miniaturize semiconductor devices. It is convenient for doing so.

[Brief explanation of drawings]

FIG. 1, FIG. 2, and FIG. 3 are cross-sectional views showing one embodiment in the order of steps. 2... Silicon substrate, 4.12... Interlayer insulating film 4a... Remaining interlayer insulating film, 4b... Interlayer insulating film removed by etching.

Claims (1)

[Claims] (1) A step of forming an interlayer insulating film by a vapor phase growth method, a step of implanting ions into the interlayer insulating film to increase the etching rate of the interlayer insulating film, and etching the interlayer insulating film to a predetermined thickness. A method for manufacturing a semiconductor device having an interlayer insulating film with a planarized surface, the method comprising the steps of forming an interlayer insulating film to a predetermined thickness by a vapor phase growth method.